behavioural modeling.docx

8/20/2019 behavioural modeling.docx

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Verilog HDL Abstraction Levels

• Behavioral Models : Higher level of modeling where

behavior of logic is modeled.

• RTL Models : Logic is modeled at register level

• Structural Models : Logic is modeled at both register

level and gate level.

Procedural Blocks

Verilog behavioral code is inside procedure blocs! butthere is an e"ception: some behavioral code also e"istoutside procedure blocs. #e can see this in detail as wemae progress.

There are two t$pes of procedural blocs in Verilog:

• initial : initial blocs e"ecute onl$ once at time %ero&start e"ecution at time %ero'.

• always : alwa$s blocs loop to e"ecute over andover again( in other words! as the name suggests! ite"ecutes alwa$s.


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Example initial

1 module initial_example(); 2 reg clk,reset,enable,data; 34 initial begin

5 clk ! 0; 6 reset ! 0; 7 enable ! 0; 8 data ! 0; 9 end 1011 endmodule

)ou could download file initial*e"ample.v here

+n the above e"ample! the initial bloc e"ecution andalwa$s bloc e"ecution starts at time ,. -lwa$s bloc waitsfor the event! here positive edge of cloc! whereas initialbloc ust e"ecuted all the statements within begin and endstatement! without waiting.

Example always

1 module ala!s_example();

2 reg clk,reset,enable,"_in,data; 34 always " (posedge clk)

5 i# (reset) begin

6 data $! 0; 7 end else i# (enable) begin 8 data $! "_in;

9 end 1011 endmodule

)ou could download file alwa$s*e"ample.v here

http://www.asic-world.com/code/verilog_tutorial/initial_example.vhttp://www.asic-world.com/code/verilog_tutorial/always_example.vhttp://www.asic-world.com/code/verilog_tutorial/always_example.vhttp://www.asic-world.com/code/verilog_tutorial/always_example.vhttp://www.asic-world.com/code/verilog_tutorial/initial_example.v


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Example &ood procedural assignment

1 module initial_#$$d(); 2 reg clk,reset,enable,data; 34 initial begin

5 clk ! 0; 6 reset ! 0; 7 enable ! 0; 8 data ! 0; 9 end 10

11 endmodule)ou could download file initial*good.v here

Procedural Assignment &roups

+f a procedure bloc contains more than one statement!those statements must be enclosed within

• Se0uential begin end bloc

• /arallel #ork 'oin bloc

#hen using begin1end! we can give name to that group.This is called named blocks.

Example (beginend(

http://www.asic-world.com/code/verilog_tutorial/initial_good.vhttp://www.asic-world.com/code/verilog_tutorial/initial_good.v


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1 module initial_be#in_end(); 2 reg clk,reset,enable,data;

34 initial begin

5 )monitor (

6 (*g clk!*b reset!*b enable!*b data!*b(,7 )time, clk, reset, enable, data);

8 +, clk ! 0; 9 +,- reset ! 0;

10 +. enable ! 0; 11 +/ data ! 0;

12 +, )#inis0; 13 end 14

15 endmodule)ou could download file initial*begin*end.v here

Begin : cl gets , after 2 time unit! reset gets , after 22time units! enable after 23 time units! data after 24 units. -llthe statements are e"ecuted se0uentiall$.

%imulator 1utput

, cl5" reset5" enable5" data5" 2 cl5, reset5" enable5" data5" 22 cl5, reset5, enable5" data5" 23 cl5, reset5, enable5, data5" 24 cl5, reset5, enable5, data5,

Example (#ork'oin(

http://www.asic-world.com/code/verilog_tutorial/initial_begin_end.vhttp://www.asic-world.com/code/verilog_tutorial/initial_begin_end.vhttp://www.asic-world.com/code/verilog_tutorial/initial_begin_end.v


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1 module initial_%$rk_&$in(); 2 reg clk,reset,enable,data; 34 initial begin

5 )monitor ((*g clk!*b reset!*b enable!*b data!*b(,

6 )time, clk, reset, enable, data); 7 #ork

8 +, clk ! 0; 9 +,- reset ! 0; 10 +. enable ! 0; 11 +/ data ! 0; 12 'oin 13 +, )display ((*g 2erminating simulation(, )time); 14 )#inis0; 15 end 1617 endmodule

)ou could download file initial*for*oin.v here

3ork : cl gets its value after 2 time unit! reset after 2, timeunits! enable after 6 time units! data after 7 time units. -llthe statements are e"ecuted in parallel.

%imulator 1utput

, cl5" reset5" enable5" data5" 2 cl5, reset5" enable5" data5" 7 cl5, reset5" enable5" data5, 6 cl5, reset5" enable5, data5, 2, cl5, reset5, enable5, data5, 22 Terminating simulation

http://www.asic-world.com/code/verilog_tutorial/initial_fork_join.vhttp://www.asic-world.com/code/verilog_tutorial/initial_fork_join.v


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%e4uential %tatement &roups

The begin end e$words:

• 8roup several statements together.

• 9ause the statements to be evaluated se0uentiall$

&one at a time'

o -n$ timing within the se0uential groups is

relative to the previous statement.

o ela$s in the se0uence accumulate &eachdela$ is added to the previous dela$'

o Bloc finishes after the last statement in the

bloc.

Example se4uential

1 module se"'ential(); 23 reg a;

4

5 initial begin 6 )monitor ((*g a ! *b(, )time, a);

7 +,- a ! 0; 8 +,, a ! 1;

9 +,5 a ! 0;

10 +,/ a ! 1; 11 +,6 )#inis0; 12 end 1314 endmodule

)ou could download file se0uential.v here

http://www.asic-world.com/code/verilog_tutorial/sequential.vhttp://www.asic-world.com/code/verilog_tutorial/sequential.v


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%imulator 1utput

, a 5 " 2, a 5 , ;2 a 5 2 77 a 5 ,


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1819 endmodule

)ou could download file for*oin.v here

%imulator 1utput

, cl5" reset5" enable5" data5" 2 cl5, reset5" enable5" data5" ; cl5, reset5" enable5" data5, 6 cl5, reset5, enable5, data5, 26 Terminating simulation

Blocking and 8onblocking assignment

Blocing assignments are e"ecuted in the order the$ arecoded! hence the$ are se0uential. Since the$ bloc thee"ecution of ne"t statment! till the current statement ise"ecuted! the$ are called blocing assignments.

-ssignment are made with =5= s$mbol. >"ample a 5 b(

?onblocing assignments are e"ecuted in parallel. Sincethe e"ecution of ne"t statement is not bloced due toe"ecution of current statement! the$ are called nonblocingstatement. -ssignments are made with =@5= s$mbol.>"ample a @5 b(

8ote : 9orrect wa$ to spell AnonblocingA is AnonblocingAand not Anon1blocingA.

http://www.asic-world.com/code/verilog_tutorial/fork_join.vhttp://www.asic-world.com/code/verilog_tutorial/fork_join.v


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Example blocking and nonblocking

1 module bl$ckin#_n$nbl$ckin#(); 23 reg a,b,c,d;

4 99 Blocking Assignment 5 initial begin

6 +,- a ! 0; 7 +,, a ! 1; 8 +,5 a ! 0; 9 +,/ a ! 1; 10 end

1112 initial begin 13 +,- b $! 0;

14 +,, b $! 1; 15 +,5 b $! 0; 16 +,/ b $! 1; 17 end 1819 initial begin

20 c ! /10 0; 21 c ! /11 1;

22 c ! /12 0;

23 c ! /13 1; 24 end 2526 initial begin 27 d $! +,- 0; 28 d $! +,, 1; 29 d $! +,5 0; 30 d $! +,/ 1; 31 end 3233 initial begin

34 )monitor ((27E ! *g A ! *b B ! *b ; ! *b D ! *b(,)time, a, b, c, d);

35 +.- )#inis0; 36 end 3738 endmodule

)ou could download file blocing*nonblocing.v here

http://www.asic-world.com/code/verilog_tutorial/blocking_nonblocking.vhttp://www.asic-world.com/code/verilog_tutorial/blocking_nonblocking.v


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%imulator 1utput

T+M> 5 , - 5 " B 5 " 9 5 " 5 " T+M> 5 2, - 5 , B 5 , 9 5 , 5 , T+M> 5 22 - 5 , B 5 , 9 5 , 5 2 T+M> 5 2; - 5 , B 5 , 9 5 , 5 , T+M> 5 27 - 5 , B 5 , 9 5 , 5 2 T+M> 5 ;2 - 5 2 B 5 2 9 5 2 5 2 T+M> 5 77 - 5 , B 5 , 9 5 , 5 2 T+M> 5


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1 module assi#n_deassi#n (); 23 reg clk,rst,d,preset;

4 wire "; 5

6 initial begin 7 )monitor (("*g clk *b rst *b preset *b d *b 4 *b(,

8 )time, clk, rst, preset, d, "); 9 clk ! 0;

10 rst ! 0; 11 d ! 0;

12 preset ! 0; 13 +,- rst ! 1;

14 +,- rst ! 0; 15 repeat (10) begin

16 " (posedge clk); 17 d $! )random; 18 " (negedge clk) ; 19 preset $! = preset; 20 end

21 +, )#inis0; 22 end

23 99 ;lock generator

24 always +, clk ! =clk; 25

26 99 assign and deassign 4 o# #lip #lop module 27 always "(preset)

28 i# (preset) begin 29 assign " ! 1; 99 assign procedural statement

30 end else begin

31 deassi#n "; 99 deassign procedural statement 32 end 3334 d_%% (clk,rst,d,"); 35

36 endmodule 3738 99 D 3lip3lop model 39 module d_%% (clk,rst,d,"); 40 input clk,rst,d; 41 output "; 42 reg "; 43

44 always " (posedge clk) 45 i# (rst) begin

46 " $! 0; 47 end else begin

48 " $! d; 49 end 5051 endmodule

)ou could download file assign*deassign.v here

http://www.asic-world.com/code/verilog_tutorial/assign_deassign.vhttp://www.asic-world.com/code/verilog_tutorial/assign_deassign.v


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%imulator 1utput

, cl , rst , preset , d , 0 " 2 cl 2 rst , preset , d , 0 , ; cl , rst , preset , d , 0 , 7 cl 2 rst , preset , d , 0 , < cl , rst , preset , d , 0 , 6 cl 2 rst , preset , d , 0 , 3 cl , rst , preset , d , 0 , C cl 2 rst , preset , d , 0 , D cl , rst , preset , d , 0 ,

4 cl 2 rst , preset , d , 0 , 2, cl , rst 2 preset , d , 0 , 22 cl 2 rst 2 preset , d , 0 , 2; cl , rst 2 preset , d , 0 , 27 cl 2 rst 2 preset , d , 0 , 2< cl , rst 2 preset , d , 0 , 26 cl 2 rst 2 preset , d , 0 , 23 cl , rst 2 preset , d , 0 , 2C cl 2 rst 2 preset , d , 0 , 2D cl , rst 2 preset , d , 0 , 24 cl 2 rst 2 preset , d , 0 , ;, cl , rst , preset , d , 0 , ;2 cl 2 rst , preset , d , 0 ,

;; cl , rst , preset 2 d , 0 2 ;7 cl 2 rst , preset 2 d 2 0 2 ;< cl , rst , preset , d 2 0 2 ;6 cl 2 rst , preset , d 2 0 2 ;3 cl , rst , preset 2 d 2 0 2 ;C cl 2 rst , preset 2 d 2 0 2 ;D cl , rst , preset , d 2 0 2 ;4 cl 2 rst , preset , d 2 0 2 7, cl , rst , preset 2 d 2 0 2 72 cl 2 rst , preset 2 d 2 0 2 7; cl , rst , preset , d 2 0 2 77 cl 2 rst , preset , d 2 0 2 7< cl , rst , preset 2 d 2 0 2 76 cl 2 rst , preset 2 d , 0 2 73 cl , rst , preset , d , 0 2 7C cl 2 rst , preset , d 2 0 , 7D cl , rst , preset 2 d 2 0 2 74 cl 2 rst , preset 2 d 2 0 2


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#orce and release

-nother form of procedural continuous assignment isprovided b$ the force and release procedural statements.These statements have a similar effect on the assign1

deassign pair! but a force can be applied to nets as well asto registers.

Ene can use force and release while doing gate levelsimulation to wor around reset connectivit$ problems. -lsocan be used insert single and double bit errors on dataread from memor$.

Example #orce and release

1 module %$rce_release (); 23 reg clk,rst,d,preset;

4 wire "; 5

6 initial begin 7 )monitor (("*g clk *b rst *b preset *b d *b 4 *b(,

8 )time, clk, rst, preset, d, "); 9 clk ! 0;

10 rst ! 0; 11 d ! 0; 12 preset ! 0; 13 +,- rst ! 1; 14 +,- rst ! 0; 15 repeat (10) begin

16 " (posedge clk); 17 d $! )random; 18 " (negedge clk) ; 19 preset $! = preset; 20 end 21 +, )#inis0; 22 end 23 99 ;lock generator

24 always +, clk ! =clk;


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2526 99 #orce and release o# #lip #lop module 27 always "(preset) 28 i# (preset) begin 29 %$rce " ! preset; 99 #orce procedural statement 30 end else begin

31 release "; 99 release procedural statement 32 end 3334 d_%% (clk,rst,d,"); 3536 endmodule 3738 99 D 3lip3lop model

39 module d_%% (clk,rst,d,"); 40 input clk,rst,d; 41 output "; 42 wire "; 43 reg "_re#;

4445 assign " ! "_re#; 4647 always " (posedge clk) 48 i# (rst) begin 49 "_re# $! 0; 50 end else begin 51 "_re# $! d; 52 end 5354 endmodule

)ou could download file force*release.v here

%imulator 1utput

, cl , rst , preset , d , 0 " 2 cl 2 rst , preset , d , 0 , ; cl , rst , preset , d , 0 ,

7 cl 2 rst , preset , d , 0 , < cl , rst , preset , d , 0 , 6 cl 2 rst , preset , d , 0 , 3 cl , rst , preset , d , 0 , C cl 2 rst , preset , d , 0 , D cl , rst , preset , d , 0 , 4 cl 2 rst , preset , d , 0 , 2, cl , rst 2 preset , d , 0 , 22 cl 2 rst 2 preset , d , 0 , 2; cl , rst 2 preset , d , 0 ,

http://www.asic-world.com/code/verilog_tutorial/force_release.vhttp://www.asic-world.com/code/verilog_tutorial/force_release.v


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27 cl 2 rst 2 preset , d , 0 , 2< cl , rst 2 preset , d , 0 , 26 cl 2 rst 2 preset , d , 0 , 23 cl , rst 2 preset , d , 0 , 2C cl 2 rst 2 preset , d , 0 , 2D cl , rst 2 preset , d , 0 , 24 cl 2 rst 2 preset , d , 0 , ;, cl , rst , preset , d , 0 , ;2 cl 2 rst , preset , d , 0 , ;; cl , rst , preset 2 d , 0 2 ;7 cl 2 rst , preset 2 d 2 0 2 ;< cl , rst , preset , d 2 0 , ;6 cl 2 rst , preset , d 2 0 2 ;3 cl , rst , preset 2 d 2 0 2 ;C cl 2 rst , preset 2 d 2 0 2 ;D cl , rst , preset , d 2 0 2 ;4 cl 2 rst , preset , d 2 0 2 7, cl , rst , preset 2 d 2 0 2 72 cl 2 rst , preset 2 d 2 0 2 7; cl , rst , preset , d 2 0 2

77 cl 2 rst , preset , d 2 0 2 7< cl , rst , preset 2 d 2 0 2 76 cl 2 rst , preset 2 d , 0 2 73 cl , rst , preset , d , 0 2 7C cl 2 rst , preset , d 2 0 , 7D cl , rst , preset 2 d 2 0 2 74 cl 2 rst , preset 2 d 2 0 2

behavioural modeling.docx

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