beamreach patent portfolio overview - ipmetrics...beamreach patent portfolio overview created date...
TRANSCRIPT
Beamreach Technologies O
verview
7|
Th
in W
afe
r –
Ba
se
d
(1) “EPI” Epitaxial Thin Wafer
(2) IBC(*)Front End
(3) Sheet Line Back End,F
lexib
le M
od
ule
(3
) H
igh
Vo
lta
ge
Sm
art
Mo
du
le
Co
nve
ntio
na
l Wa
fer-B
ase
d
Pu
rch
ase
d W
afe
r
(2) IBC Front End PVD
(**)/Electroplate Metal
Co
nve
ntio
na
l Mo
du
le o
r
(3
)Lo
w o
r H
igh
Vo
lta
ge
Sm
art
Mo
du
le
(4) Sprint™ Com
mercial Rooftop System
29
Pe
nd
ing
Ap
plic
atio
ns
Be
am
re
ach
Pa
te
nt A
sse
ts
23
U.S
., 38
Fo
re
ign
, 30
Pe
nd
ing
Ap
plic
atio
ns
34
U.S
., 24
Fo
re
ign
, 83
Pe
nd
ing
Ap
plic
atio
ns
6 U
.S., 2
Fo
re
ign
, 31
Pe
nd
ing
Ap
plic
atio
ns
2 U
.S., 5
Fo
re
ign
, 36
Pe
nd
ing
Ap
plic
atio
ns
* IBC = “Inte
rd
igit
ate
d B
ack Contact”
** PVD = “Ph
ysic
al V
ap
or Deposition”
**
*iCell™
= Proprietary Cell Concept
No
n-P
V
Ap
plic
atio
ns
This is an actively prosecuted portfolio -This summary table is based on patent asset counts as of April 2017
Patent Portfolio Covers Wafer -to -System
Value Stream
(4) Integrated lightweight racking
for fast install, increased packing density –
4 patent applications
Prepreg
Backplane
(100mm)
Epitaxial Silicon (n-type)
Plating: Cu + Sn
Al-alloy Metal Paste
Al-alloy Metal Paste
Plating: Cu + Sn
Via Holes
Via Holes
(4) Plastic frame (instead of
aluminum
) avoids grounding –saves
cost and time –
2 patent applications
(2) Cell designs that use aluminum
paste instead of silver paste –
much
lower cost –
78+ patent applications
(1) (2) (3) Much thinner solar cells are
less fragile; enabling thinner cover glass and rem
oval of aluminum
frame –
25%
of patent applications directed towards
thinning silicon or thin silicon processing (80+ patent applications)
(2) Back-contact cell design im
proves efficiency (no bus bars that reduce effective cell area) –50%
+ of entire patent portfolio (160+ patent applications)
(3) Monolithic backplane attaches
30 solar cells to one sheet; avoids cell-to-cell stringing –
the main
cause of reliability issues in solar panels –
78+ patent applications
(2) (3) Integrated cell-level and m
odule-level shade managem
ent allow
s closer row-to-row
spacing –25 patent applications
Num
bers in ( ) are the associated Patent Fam
ily Num
bers
Wafer to M
odule Process
ReusableSilicon
Template
Porous Silicon Grow
th
Thin Epi Silicon
Deposition
Cell Processing
FlexBackplane
Epi ReleaseTem
plate Re-useFlex Sm
artCell
High-Performance
Smart M
odule
•Reusable Tem
plate –Fo
un
da
tio
n fo
r T
hin
Ce
ll
Pro
ce
ssin
g; R
eu
sa
ble
>1
00
x
•Releasable Thin M
ono-Crystalline-Silicon •
High Efficiency Back Contact/Back-Junction Cell Design –
20
%+
De
mo
nstra
te
d –
24
%+
Ach
ieva
ble
•Planar Flex Backplane –
Stre
ngth
& S
up
po
rt fo
r C
ell;
Sm
art C
ells
an
d M
od
ule
s fo
r High Energy Yield
Te
ch
no
log
y F
am
ily 1
Te
ch
no
log
y
Fa
mily
1
Te
ch
no
log
y
Fa
mily
3
Te
ch
no
log
y
Fa
mily
2
Te
ch
no
log
y
Fa
milie
s 2
& 3
EP
I/P
oro
us S
ilico
n W
afe
r T
ech
no
log
y
Te
ch
no
log
y F
am
ily 1
10|
1. Epitaxial Silicon (EPI) / Porous Silicon / Epitaxial Lift-Off (ELO
) Technology
11|
1.
Th
in, in
exp
en
siv
e S
ilico
n w
afe
r fa
bric
atio
n
a.
Mu
lti-
laye
r p
oro
us s
ilico
n fo
rm
atio
n o
n r
eu
sa
ble
su
bstra
te
b.
Va
po
r p
ha
se
or liq
uid
ph
ase
ep
ita
xy
th
in la
ye
r g
ro
wth
c.
In-sit
u d
op
an
t p
ro
file
co
ntro
l
d.
Hig
h w
ith
in w
afe
r d
op
an
t u
nifo
rm
ity
an
d w
afe
r-to
-w
afe
r r
ep
ea
ta
bilit
y
2.
En
ab
ling
te
ch
no
log
y fo
r t
hin
wa
fer h
an
dlin
g:
a.
Mo
bile
ele
ctro
sta
tic
ch
ucks (
ME
SC
)
b.
Mo
bile
va
cu
um
ca
rrie
rs (
MO
VA
C)
c.
Ap
plic
ab
le t
o P
V, s
em
ico
nd
ucto
r M
EM
S a
nd
mic
ro
ele
ctro
nic
s, L
ED
s.
3.
So
lar c
ell p
ro
ce
ssin
g w
ith
EP
atta
ch
ed
to
su
bstra
te
a.
Hig
h e
ffic
ien
cy
IBC
ce
ll pro
ce
ss o
n f
re
e s
urfa
ce
b.
La
se
r-b
ase
d E
PI la
ye
r r
ele
ase
c.
“Sheet Line” technology enables flexible backplane module
ma
nu
factu
re
4.
Co
mp
atib
le w
ith
:
a.
Hig
h v
olt
ag
e c
ells
an
d m
od
ule
s (iC
ell)
b.
“Smart” M
odule design for shade tolerance and distributed control.
NREL-Certified Full-Area
Cell Efficiency = 20.13%
1. Epitaxial Silicon (EPI) / Porous Silicon / Epitaxial Lift-Off Technology
Po
ro
us S
ilico
n
Fo
rm
atio
n
La
se
r-b
ase
d D
ry
Lif
t-o
ff
(C
lick t
o W
atch
Vid
eo
)
1. Epitaxial Silicon (EPI) / Porous Silicon / Epitaxial Lift-Off Technology
3D
Ep
ita
xy
Po
ro
us S
ilico
n a
nd
Ep
ita
xy
To
ol D
esig
ns
(C
lick t
o W
atch
Vid
eo
)
1. Epitaxial Silicon (EPI) / Porous Silicon / Epitaxial Lift-Off Technology
Bi-layer porous silicon
Epi Silicon
Te
mp
late
for r
e-u
se
Spontaneous Release
TFSSP
ost E
pi
TFS
S t
op
vie
w S
EM
Po
st E
pi
TFS
S b
ack
vie
w S
EM
3D
Pa
tte
rn
ed
Film
s –
As-G
ro
wn
Ba
ck
Co
nta
ct S
ola
r C
ell
Te
ch
no
log
y F
am
ily 2
15|
2. Interdigitated Back-Contact Solar Cell Technology
16|
1.
Hig
h E
ffic
ien
cy
a.
20
.8%
ave
ra
ge
ach
ieve
d –
Pro
ce
ss c
on
tro
l de
mo
nstra
te
d
b.
24
%+
atta
ina
ble
c.
On
ly IB
C a
nd
He
te
ro
jun
ctio
n p
ro
ce
sse
s c
ap
ab
le o
f >
22
%
2.
Lo
w M
an
ufa
ctu
rin
g C
ost:
a.
$0
.25
4/W
for P
erm
ian
1.0
Ce
ll
b.
$0
.23
0/W
for P
erm
ian
2.0
Ce
ll (sa
me
as 2
0.8
% P
ER
C)
c.
Lo
w c
ell c
ost a
t h
igh
po
we
r y
ield
s $
0.1
3/W
low
er s
yste
m c
ost t
ha
n P
ER
C
3.
Hig
h R
elia
bilit
y:
a.
Op
tim
ize
d A
nti-
re
fle
ctio
n la
ye
r: N
o P
ote
ntia
l Ind
uce
d D
eg
ra
da
tio
n (
PID
)
b.
N-Ty
pe
Su
bstra
te
ha
s n
o L
igh
t In
du
ce
d D
eg
ra
da
tio
n (
LID
)
4.
Hig
h P
ro
ce
ss Y
ield
Sta
bilit
y:
a.
Hig
h e
mit
te
r f
ra
ctio
n r
ed
uce
s s
en
sit
ivit
y t
o s
ub
stra
te
qu
alit
y
b.
Se
lf-a
lign
ed
em
itte
r e
limin
ate
s a
lign
me
nt e
rro
r
c.
Pro
prie
ta
ry
se
lf-d
op
ing
die
lectric
sta
ck
d.
Ro
bu
st, c
om
me
rcia
lly a
va
ilab
le e
qu
ipm
en
t s
et
5.
Ba
ck c
on
ta
ct is
a u
niq
ue
ly e
na
blin
g t
ech
no
log
y fo
r:
a.
Hig
h v
olt
ag
e c
ells
an
d m
od
ule
s (
iCe
ll)
b.
Ba
ckp
lan
e m
od
ule
asse
mb
ly
c.
“Smart” M
odule design for shade tolerance and distributed control.
Consistent Baseline IBC Process
17|
•2
1.8
% A
ve
ra
ge
Ce
ll
Eff
icie
ncy
(O
ve
r 3
,00
0
Ce
lls)
•<
1%
(re
lativ
e)
Co
eff
icie
nt o
f V
aria
tio
n
(C
oV
) –
Lo
we
r fo
r m
ost
re
ce
nt lo
ts
•Id
en
tif
ied
sh
ort-te
rm
pa
th
to
23
%+
Eff
icie
ncy
–3
20
W M
od
ule
Champion M
odule3
rdParty Test at 315.6 W
Proven Module Pow
er
Increased Equivalent Module Pow
er with Larger W
afers
19|
•La
rg
er w
afe
rs h
ave
th
e
sa
me
21
.8%
Ave
ra
ge
Ce
ll Eff
icie
ncy
•6
W h
igh
er e
qu
iva
len
t
mo
du
le e
ffic
ien
cy
du
e
to
larg
er a
re
a
•E
qu
iva
len
t t
o 1
0
mo
du
les p
ro
du
ce
d
2. Interdigitated Back-Contact Solar Cells -Additional Technology
20|
1.
An
cilla
ry
Ce
ll Pro
ce
ssin
g T
ech
no
log
ies In
clu
de
a.
Ion
imp
lan
ta
tio
n
b.
La
se
r p
atte
rn
ing
c.
La
se
r d
op
ing
d.
He
te
ro
stru
ctu
re
de
vic
es
2.
Co
mp
lime
nta
ry
Ce
ll Stru
ctu
re
-iCell™ High Voltage Cell Technology
a.
Hig
h v
olt
ag
e c
ells
en
ab
led
by
IBC
te
ch
no
log
y
b.
Ca
pit
al lig
ht a
nd
low
co
st c
ell p
ro
ce
ss
a.
Scre
en
prin
te
d A
lum
inu
m m
eta
lliza
tio
n
b.
No
ma
sk
ing
–La
se
r d
efin
ed
pa
tte
rn
s
c.
No
PV
D
d.
No
pla
tin
g –
Mo
re
en
vir
on
me
nta
lly f
rie
nd
ly t
ha
n
co
nve
ntio
na
l IBC
c.
En
ab
les h
igh
vo
lta
ge
, low
cu
rre
nt m
od
ule
s
a.
Re
du
ce
d w
irin
g c
ost
b.
Incre
ase
d s
ha
de
to
lera
nce
d.
Co
mp
lime
nts:
a.
EP
I Silic
on
th
in c
ell p
ro
ce
ss (
Fa
mily
1)
b.
Mo
no
lith
ic b
ack
pla
ne
mo
du
le a
rch
ite
ctu
re
(Fa
mily
3)
Prepreg
Backplane
(100mm)
50-150mm Silicon –
from Solar W
afer (n-type)
P-P
+
APCVD B-AlO
x
Al-alloy Metal
PasteO
n Emitter
Contacts
Texture
Al-alloy Metal
PasteO
n Base ContactsN
+
PECVD AlOx
+ SiN
x
Self-aligned
PSG
Self-aligned
iCell Cut
iCell Cut
PVDPVD
Via Holes
Via Holes
Monolithic IBC iCell
iCell Technology –C
ell S
tru
ctu
re
& Im
pro
ve
me
nts
Prepreg
Backplane
(100mm)
50-150mm Silicon –
from Solar W
afer (n-type)
P-P
+
APCVD B-AlO
x
Al-alloy Metal
PasteO
n Emitter
Contacts
Texture
Al-alloy Metal
PasteO
n Base ContactsN
+
PECVD AlOx
+ SiN
x
Self-aligned
PSG
Self-aligned
iCell Cut
iCell Cut
PVDPVD
Via Holes
Via Holes
Epi-Based IBC Cell
Prepreg
Backplane
(100mm)
10-50mm Epitaxial Silicon (n-type)
P-
Plating: Cu + Sn
APCVD BSG1
Texture
PECVD a-Si + SiNx
N+
Al-alloy Metal
PasteO
n Base ContactsPSG
PSG
BSG2
P+
Al-alloy Metal
PasteO
n Emitter
ContactsBSG
2
Plating: Cu + Sn
PVDPVD
Via Holes
Via Holes
Monolithic IBC iCell
Benefits with M
onolithicS
ilico
n S
ola
r W
afe
r (
n-ty
pe
, mo
no
)S
ta
nd
ard
pro
ce
ss t
oo
ls
AP
CV
D B
-A
lOx
Hig
he
r V
oc ;
HF
etch
sto
p a
fte
r a
nn
ea
l
Pic
ose
co
nd
lase
r (
gre
en
53
2n
m) a
bla
tio
n
are
a is
re
du
ce
d w
ith
se
lf-a
lign
ed
co
nta
cts
Hig
he
r V
oc ;
gre
en
(vs. U
V) e
na
ble
slo
we
r-co
st,
lon
ge
r-life
lase
r o
ptic
s
PE
CV
D A
l2O
3+
Si3N
4U
V-re
sis
ta
nt p
assiv
atio
n (
no
LID
)
La
se
r p
atte
rn
ing
of iC
ell c
uts in
silic
on
Cu
rre
nt r
ed
uctio
n (
vo
lta
ge
incre
ase
) to
en
ab
le
th
inn
er m
eta
l laye
r; le
ss c
ell-
to
-m
od
ule
losse
s
Pa
tte
rn
ed
prin
t o
f A
l-a
lloy
pa
ste
+ P
VD
sp
utte
r o
xid
e e
tch
+ A
l/S
n
+ L
ase
r p
atte
rn
ing
of m
eta
l on
pre
pre
g
All-
dry
me
ta
l pro
ce
ssin
g;
re
du
ce
d p
ro
ce
ss s
te
ps
Monolithic IBC iCell
AttributeEpi-Based IBC Cell
Silic
on
Op
tic
al A
bso
rb
er
Ep
ita
xia
l CV
D (
n-ty
pe
, mo
no
)
Ba
cksid
e E
mit
te
rP
assiv
atio
nA
PC
VD
BS
G
Ba
cksid
e A
PC
VD
Oxid
e P
atte
rn
ing
Pic
ose
co
nd
lase
r (U
V 3
55
nm
)a
bla
tio
n
Su
nn
ysid
e S
urfa
ce
Pa
ssiv
atio
nP
EC
VD
am
orp
ho
us-S
i + S
i3N
4
iCe
llS
ilico
n C
ut
No
ne
Me
ta
lliza
tio
n &
Me
ta
lP
atte
rn
ing
Pa
tte
rn
ed
prin
t o
f A
l-a
lloy
pa
ste
+ P
VD
sp
utte
r o
xid
e e
tch
+ A
l/N
i-V
+ P
atte
rn
ed
prin
t o
f r
esis
t/m
ask
+ P
latin
gC
u/S
n
+ R
esis
t &
me
ta
l etch
iCell Technology –C
ell S
tru
ctu
re
& Im
pro
ve
me
nts
Prepreg
Backplane
(100mm)
50-150mm Silicon –
from Solar W
afer (n-type)
P-P
+
APCVD B-AlO
x
Al-alloy Metal
PasteO
n Emitter
Contacts
Texture
Al-alloy Metal
PasteO
n Base ContactsN
+
PECVD AlOx
+ SiN
x
Self-aligned
PSG
Self-aligned
iCell Cut
iCell Cut
PVDPVD
Via Holes
Via Holes
Epi-Based IBC Cell
Prepreg
Backplane
(100mm)
10-50mm Epitaxial Silicon (n-type)
P-
Plating: Cu + Sn
APCVD BSG1
Texture
PECVD a-Si + SiNx
N+
Al-alloy Metal
PasteO
n Base ContactsPSG
PSG
BSG2
P+
Al-alloy Metal
PasteO
n Emitter
ContactsBSG
2
Plating: Cu + Sn
PVDPVD
Via Holes
Via Holes
Monolithic IBC iCell
1.EPI/Porous Silicon W
afer Technology
2.Interdigitated Back Contact (IBC) Solar Cell Technology
3.Backplane/Smart Monolithic Solar Module Technology
Ba
ck
pla
ne
Arch
ite
ctu
re
Te
ch
no
log
y F
am
ily 3
23|
3. Monolithic Backplane Architecture (Sheet) Technology
24|
1.
Fle
xib
le m
od
ule
te
ch
no
log
y
2.
Ea
sily
cu
sto
miz
ab
le (
lase
r s
oftw
are
), lo
w c
ost m
eta
lliza
tio
n
3.
No
inte
rco
nn
ect t
ab
s
4.
Ro
bu
st, P
rin
te
d C
ircu
it B
oa
rd
(P
CB
) lik
e a
sse
mb
ly
5.
Ca
n b
e in
te
gra
te
d w
ith
:
a.
EP
I Te
ch
no
log
y (
Fa
mily
1)
b.iC
ell T
ech
no
log
y (
Fa
mily
2)
c.
Sm
art M
od
ule
Te
ch
no
log
y (
Fa
mily
3)
d.
Sp
rin
t T
ech
no
log
y (
Fa
mily
4)
6.
Ba
ck
pla
ne
mo
du
le c
an
be
cu
sto
m-co
nfig
ure
d fo
r
ap
plic
atio
n-sp
ecif
ic:
a.
Dis
trib
ute
d s
ha
de
ma
na
ge
me
nt
b.
Se
rie
s/P
ara
llel c
on
ne
ctio
n
c.
Co
nfo
rm
an
ce
to
no
n-p
lan
ar s
urfa
ce
s (
e.g
. Ro
ofin
g
sh
ing
les, a
uto
mo
bile
su
n r
oo
fs)
25|
(3) Monolithic M
odule & (2) iCell Technology
Silicon Side
Metal Side
iCell Cuts in Silicon
Cell-to-Cell Metal
Interconnect Pattern on Prepreg
Integrated Smart
Chip on Prepreg
•Flexible m
onolithic sheet•
5x6=30 156mm
cells are laminated
onto a large-area prepreg sheet•
Cell-to-cell interconnections by laser patterning of PVD m
etal on prepreg (no soldering)
•iCelllaser cut of silicon enables current decrease and voltage increase
•Integrated chips that are directly soldered onto m
onolithic enable cell-level, em
bedded smart electronics
•U
L Certification tests successfully passed in M
arch 2016
(3) Monolithic M
odule & (2) iCell Technology
De
mo
nstra
te
d H
igh
Eff
icie
ncy
–5
x6
30
-C
ell M
on
olit
hic
Sh
ee
ts (
Are
a 7
37
7cm
2)
•Sheet Pow
er•
Sheet Aperture Efficiency
•Sheet Voc
•Voc per iCell
•Sheet Isc
•Jsc
per iCell•
FF
Sh
ee
t ID
: 5x6
-1
2x-4
92
EL Images
Sh
ee
t ID
: 5x6
-1
2x-4
91
155.3W21.0%
249.4V693m
V0.797A38.9m
A/cm2
78.1%
153.9W20.9%
248.8V691m
V0.793A38.7m
A/cm2
78.0%
Sh
ee
t ID
: 5x6
-1
2x-5
09
155.9W21.1%
250.9V697m
V0.793A38.7m
A/cm2
78.3%
Sh
ee
t ID
: 5x6
-1
2x-5
10
156.6W21.2%
250.9V697m
V0.795A38.8m
A/cm2
78.5%
Average peak pow
er is 5.0-5.2W
per 156mm
x 156m
m cell area
Prepreg
Backplane
(100mm)
10-50mm Epitaxial Silicon (n-type)
P-
Plating: Cu + Sn
APCVD BSG1
Texture
PECVD a-Si + SiNx
N+
Al-alloy Metal Paste
On Base Contacts
PSGPSG
BSG2
P+
Al-alloy Metal Paste
On Em
itter ContactsBSG
2
Plating: Cu + Sn
PVDPVD
Via HolesVia Holes
AttributeEpi-Based IBC Cell
Silic
on
Op
tic
al A
bso
rb
er
Ep
ita
xia
l CV
D (
10
-5
0mm
, n-ty
pe
, mo
no
crysta
lline
)
Ba
cksid
e E
mit
te
rP
assiv
atio
nA
PC
VD
BS
G (
no
va
cu
um
pro
ce
ssin
g)
Ba
cksid
e A
PC
VD
Oxid
e P
atte
rn
ing
Pic
ose
co
nd
lase
r (
UV
35
5n
m) a
bla
tio
n(n
o w
et p
ro
ce
ssin
g)
Ba
ck
pla
ne
Pre
pre
g (
~1
00m
m)
Su
nn
ysid
e S
urfa
ce
Pa
ssiv
atio
nP
EC
VD
am
orp
ho
us-S
i + S
i3N
4a
t 2
00
C
Me
ta
lliza
tio
n &
Me
ta
l Pa
tte
rn
ing
Pa
tte
rn
ed
scre
en
prin
t o
f A
l-a
lloy
pa
ste
+ P
VD
sp
utte
r o
xid
e e
tch
+ A
l/N
iV
+ P
atte
rn
ed
scre
en
prin
t o
f r
esis
t/m
ask
+ P
late
d C
u/S
n
+ R
esis
t &
me
ta
l etch
3. Monolithic Backplane Architecture (Sheet) Technology
•IB
C (
Inte
rd
igit
ate
d B
ack
Co
nta
ct) s
ola
r c
ell
de
sig
n
•V
ery
th
in (
10
-5
0 µ
m) e
pit
axia
l silic
on
ab
so
rb
er
•P
re
pre
g b
ack
pla
ne
(1
00
µm
)
•C
ell is
fle
xib
le w
ith
are
a 1
56
x 1
56
mm
2
•N
o s
ilve
r (
Ag
)
In-house Tester 20.8%
CellTester
VocIsc
FFEff
67-69N
REL2.745
9.81578.65
21.19
67-69SLXL
2.7259.70
78.7120.80
67-70N
REL2.76
9.7478.42
21.10
67-70SLXL
2.7129.77
78.6220.87
Subsequently im
proved in-house by 0.7%
to 21.5%
Equivalent to 21.8%
at NREL
Thin Silicon Wafer: 1) Arlon Prepreg, 2) iCell, 3) 219cm
2M
ay 29th2013 Î
21.2% N
REL Certified
3. Additional Module Technology -Sm
art Module Electronics
29|
1.
En
ab
ling
te
ch
no
log
ies fo
r h
igh
-p
erfo
rm
an
ce
(h
igh
po
we
r a
nd
hig
h
en
erg
y y
ield
) S
ma
rt M
od
ule
s a
nd
Sm
art P
V S
yste
ms. T
he
se
te
ch
no
log
ies in
clu
de
a.
Dis
trib
ute
d M
PP
T p
ow
er o
ptim
ize
r c
hip
s e
mb
ed
de
d w
ith
in t
he
PV
mo
du
le la
min
ate
to
ma
xim
ize
dis
trib
ute
d e
ne
rg
y h
arve
stin
g
an
d t
o s
ub
sta
ntia
lly m
itig
ate
sh
ad
ing
an
d s
oilin
g e
ffe
cts o
n
po
we
r g
en
era
tio
n;
b.
Dis
trib
ute
d s
ha
de
ma
na
ge
me
nt a
nd
mit
iga
tio
n o
f s
ha
din
g a
nd
so
iling
effe
cts u
sin
g a
dis
trib
ute
d a
rra
y o
f lo
w-co
st S
BR
(S
ch
ottky
Ba
rrie
r R
ectif
iers) e
mb
ed
de
d in
th
e P
V m
od
ule
lam
ina
te
s
c.
Re
mo
te
Acce
ss M
od
ule
Sw
itch
(R
AM
S) a
nd
PV
Arra
y C
on
tro
l an
d
Sta
tu
s m
on
ito
rin
g (
PA
CS
) t
o e
na
ble
co
mm
an
d-b
ase
d r
em
ote
sw
itch
ing
(O
N/O
FF
) o
f t
he
ind
ivid
ua
l mo
du
les a
nd
re
mo
te
mo
nit
orin
g o
f t
he
he
alt
h a
nd
po
we
r g
en
era
tio
n a
mo
un
t o
f e
ach
mo
du
le w
ith
in t
he
insta
lled
PV
syste
ms in
th
e f
ield
.
2.
Co
mp
lime
nts S
prin
t P
V S
yste
m (
Fa
mily
4)
Au
to
ma
te
d D
iod
e A
tta
ch
me
nt
(C
lick
to
Wa
tch
Vid
eo
)
Monolithic M
odule & iCell Technology (IP Cluster 3)
Fie
ld P
erfo
rm
an
ce
of P
V S
yste
ms fo
r V
ario
us S
ha
din
g C
on
dit
ion
s
En
erg
y Y
ield
for B
ea
mre
ach
vs. C
om
pe
tit
ion
(~
4 M
on
th
s o
f F
ield
Da
ta
)
Beamreach
vs. Others
Beamreach
Monolithic PV system
provides higher energy yield values compared to other system
s:U
nder Most Conditions: Beam
reach> SunPow
er> SolarWorld
+ SolarEdge> Trina + Tigo