basics of energy & power dissipation

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Basics of Energy & Power Dissipation. Lecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary. Outline. Basic Concepts Dynamic power Static power Time, Energy, Power Tradeoffs Activity model for power estimation Combinational and sequential logic. Reading. - PowerPoint PPT Presentation



Basics of Energy & Power DissipationLecture notes S. Yalamanchili, S. Mukhopadhyay. A. Chowdhary(#)OutlineBasic ConceptsDynamic powerStatic powerTime, Energy, Power TradeoffsActivity model for power estimationCombinational and sequential logic

(#)Reading Goal: UnderstandThe sources of power dissipation in combinational and sequential circuitsPower vs. energyOptions for controlling power/energy dissipation

(#)Where Does the Power Go in CMOS?Dynamic Power ConsumptionCaused by switching transitions cost of switching stateStatic Power ConsumptionCaused by leakage currents in the absence of any switching activityPower consumption per transistor changes with each technology generationNo longer reducing at the same rateWhat happens to power density?

AMD Trinity APUVinVoutVddPMOSGroundNMOS(#)n-channel MOSFET LGATESOURCEBODYDRAINtoxGATESOURCEDRAIN LVgs < Vt transistor off - Vt is the threshold voltageVgs > Vt transistor onImpact of threshold voltage Higher Vt, slower switching speed, lower leakageLower Vt, faster switching speed, higher leakageActual physics is more complex but this will do for now!

(#) Abstracting Energy BehaviorHow can we abstract energy consumption for a digital device?Consider the energy cost of charge transferVinVoutVddPMOSGroundNMOSModeled as an on/off resistanceModeled as an output capacitanceVinVout0110(#)Switch from one state to anotherTo perform computation, we need to switch from one state to another

Logic 1: Cap is chargedLogic 0: Cap is discharged+-Connect the cap to GND thorough an ON NMOSConnect the cap to VCC thorough an ON PMOSThe logic dictates whether a node capacitor will be charged or discharged.

(#)Dynamic PowerTimeVDDVoltage0TOutput Capacitor ChargingOutput Capacitor DischargingInput to CMOS inverterVDDVDDiDDiDDCLCLDynamic power is used in charging and discharging the capacitances in the CMOS circuit.

CL = load capacitance(#)Switching DelayVddCharging to logic 1 VoutVdd

(#)Switching DelayVddDischarging to logic 0 VoutVdd

(#)Switching Energy

CL is the load capacitanceEnergy dissipated per transition?Courtesy: Prof. A. Roychowdhury(#)Power Vs. EnergyEnergy is a rate of expenditure of energyOne joule/sec = one wattBoth profiles use the same amount of energy at different rates or power Power(watts)P0P1P2Same Energy = area under the curvePower(watts)TimeP0Time(#)Dynamic Power vs. Dynamic EnergyTimeVDDVoltage0TVDDVDDOutput Capacitor ChargingOutput Capacitor DischargingInput to CMOS inverteriDDiDDCLCLDynamic power: consider the rate at which switching (energy dissipation) takes place

activity factor = fraction of total capacitance that switches each cycle

(#)abcxyCharge as a State VariableabcxyFor computation we should be able to identify if each of the variable (a,b,c,x,y) is in a 1 or a 0 state.

We could have used any physical quantity to do thatVoltageCurrentElectron spinOrientation of magnetic field

We choose voltage distinguish between a 0 and a 1.All nodes have some capacitance associated with themLogic 1: Cap is chargedLogic 0: Cap is discharged+-(#)Higher Level BlocksACBABVddABCVddABAVddCBABC(#)Gate Power DissipationSwitching activity depends on the input pattern and combinational logicConsider a 01 transition on the output of a gate

Probability gate output was 0Probability gate output is 1

= number of 0s in the truth tableExample:(#)

ALU Energy Consumption03ResultOperationa1CarryInCarryOut01Binvertb2LessCan we count the number of transitions in each 1-bit ALU for an operation?Can we estimate static power?Computing per operation energy(#)17Closer Look: A 4-bit Ripple Adder Critical Path = DXOR+4*(DAND+DOR) for 4-bit ripple adder (9 gate levels)For an N-bit ripple adderCritical Path Delay ~ 2(N-1)+3 = (2N+1) Gate delaysActivity (and therefore power) is a function of the input data values!S0A0B0CinS1A1B1S2A2B2S3A3B3Carry(#)18ImplicationsWhat if I halved the frequency?What if I lower the voltage?How can I reduce the capacitance?

Combinational Logicclkclkcondinputclk

We will see later that these two are interrelated!(#)Technology scaling has caused transistors to become smaller and smaller. As a result, static power has become a substantial portion of the total power. Static PowerGate Leakage Junction Leakage Sub-threshold Leakage GATESOURCEDRAIN

(#)EnergyDelayEnergy or delayVDDVDDEnergy-Delay Product (EDP)Energy-Delay InteractionDelay decreases with supply voltage but energy/power increases

Power StateTarget of optimization

(#)leakage or delayVthleakagedelayStatic Energy-Delay InteractionStatic energy increases exponentially with decrease in threshold voltageDelay increases with threshold voltagetoxSOURCEDRAIN LGATE

(#)Temperature DependenceAs temperature increases static power increases1

#Transistors Technology DependentNormalized Leakage Current

Supply voltage1J. Butts and G. Sohi, A Static Power Model for Architects, MICRO 2000(#)The World TodayYesterday scaling to minimize time (max F)

Maximum performance (minimum time) is too expensive in terms of powerImaging scaling voltage by 0.7 and frequency by 1.5 how does dynamic power scale?Today: trade/balance performance for power efficiency

(#)Factors Affecting PowerTransistor sizeAffects capacitance (CL)Rise times and fall times (delay)Affects short circuit power (not in this course)Threshold voltage Affects leakage powerTemperatureAffects leakage powerSwitching activityFrequency (F) and number of switching transistors ( )


(#)Low Power Design: Options?

Reduce VddIncreases gate delayNote that this means it reduces the frequency of operation of the processor!Compensate by reducing threshold voltage?Increase in leakage powerReduce frequencyComputation takes longer to completeConsumes more energy (but less power) if voltage is not scaled

(#)ExampleAMD Trinity A10-5800 APU: 100W TDP

CPU P-stateVoltage (V)Freq (MHz)HWOnly (Boost)Pb012400Pb10.8751800SW-VisibleP00.8251600P10.8121400P20.7871300P30.7621100P40.75900

(#)Optimizing Power vs. Energy

Thermal envelopes minimize peak powerMaximize battery life minimize energyExample:(#)Should we reduce clock frequency by 2 (reduce dynamic power) or reduce voltage and frequency by 2 (reduce both static and dynamic power). Let power be P and time T.

Option 1: (p/2 + P)2T = 3PTOption 2: (P/8 + P/2)2T = 1.25PT

But takes twice as long28Modeling Component EnergyPer-use energies can be estimated from Gate level designs and analysesCircuit-level designs and analysesImplementation and measurementThere are various open-source tools for analysisMentor, Cadence, Synopsys, etc. Hardware Design Technology ParametersCircuit-levelEstimation ToolEstimation Results:Area, Energy, Timing, etc.

(#)Datapath ElementsALUHiMultiply DivideLo$0$1$31FP ALU$0$1$31CPU/Core Co-Processor 1Vector ALUXMM0XMM1XMM15SIMD Registers Can we measure (offline) the average energy consumed by each component?Can we measure (offline) the average energy consumed by each component?(#)A Simple Power Model for ProcessorsPer instruction energy measurementsPermits a software model of energy consumption of a programExecution time use to assess power requirementsA first order model of energy consumption for softwareA table of energy consumption per instructionMore on this later!(#)What About Wires?We will not directly address delay or energy expended in the interconnect in this classSimple architecture model: lump the energy/power with the source component

Capacitance per unit length

Resistance per unit length

Lumped RC Model(#)SummaryTwo major classes of energy/power dissipation static and dynamicManaging energy is different from managing power leads to different solutionsTechnology plays a major role in determining relative costsEnergy of components are often estimated using approximate models of switching activity(#)Study GuideExplain the difference between energy dissipation and power dissipationDistinguish between static power dissipation and dynamic power dissipationWhat is the impact of threshold voltage on the delay and energy dissipation?As you increase the supply voltage what is the behavior of the delay of logic elements? Why?As you increase the supply voltage what is the behavior of static and dynamic energy and static and dynamic power of logic elements?(#)Study Guide (cont.)Do you expect the 0-1 and 1-0 transitions at the output of a gate to dissipate the same amount of energy?For a mobile device, would you optimize power or energy? Why? What are the consequences of trying to optimize one or the other?Why does the energy dissipation of a 32-bit integer adder depend on the input values?If I double the processor clock frequency and run the same program will it take less or more energy?

(#)Study Guide (cont.)When the chip gets hotter, does it dissipate more or less energy? Why? How can you reduce dynamic energy of a combinational logic circuit?How can you reduce static energy of a combinational logic circuit?

(#)GlossaryDynamic EnergyDynamic PowerLoad capacitanceStatic EnergyStatic Power

Time constantThreshold voltageSwitching delaySwitching energy(#)


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