Basic Microcontroller System

Microcontroller-Based System

CPUMemoryI/O

Interface

BUS

Microcontroller e.g. M68HC11

To I/O

CPU: Central Processor UnitI/O: Input/OutputMemory: Program and DataBus: Address signals, Control signals, and Data signals

Central Processing Unit (CPU)

68HC11

68HC11 Register Set

Accumulator A7 0

Accumulator B7 0

015

INDEX REGISTER X015

STACK POINTER015

015

INDEX REGISTER Y015

PROGRAM COUNTER015

Double Accumulator D

Clock is implied

68HC11 Memory Address Space

$0000

$0001

$0002

$0003

$FFFF

$FFFE$FFFD

$FFFC

8 bits

Instruction Execution Cycle

• Fetch – Decode - Execute– Fetch stage

• Operations code (op-code) is loaded from memory into the Instruction Register (IR)

– Decode stage• Instruction is “decoded” into a set of “micro-

instructions” (e.g. FSM)

– Execution stage• The micro-instructions are executed. This may

involve loading the “operand” from memory.

Instruction Execution Cycle

• Comments:– Each instruction requires N clock cycles for

execution. N varies from 2 to 12– An Op-code is also referred to as

• Machine code which are the binary codes that are used to represent the instruction.

Simple ExampleReset EQU $FFFE ; Set symbol Reset to FFFE16

Program EQU $E000 ; Set symbol Program to E00016

ORG Program ; Set the assembler’s location to the value ; represented by symbol Program.

Top: LDAA #$23 ; Load the A register with 2316

LDAB #$BE ; Load the B register with BE16

ABA ; Add the A and B registers. Result is stored in A. STAA $1000 ; Store the value in the A register in ; memory location $1000. The A reg is ; unchanged.

L0: BRA L0 ; Branch to Label L0 Org Reset ; set the assembler’s location to the value ; represented by symbol Reset.

FDB Top ; Form a double byte from symbol TOP. Stored it at the

; current memory location.

Simple Example

• We can also represent this as:– A $23 ; The A register is assigned $23– B $BE ; The B register is assigned $BE– A A + B ; A = A + B– ($1000) A ;The contents at memory location

; $0100 is replaced with $23+$BE

Simple Example (cont)

• The assembler will convert our program to:

Address Opcode Operand Operand$E000 86 23$E002 c6 be$E004 1b$E005 b7 10 00$E008 20 fe……..$FFFE e0 00

What do all of these numbers mean?What do all of these numbers mean?

Simple Example (cont)

• Example: $E000 86 23• $E000:

– This is the memory location or address where the program or data is located.

• $86– This is the Operation Code or opcode– The opcode is the Hex (i.e. binary) representation of the

instruction.• $86 means LDAA # or

– Load the A register with a constant value for the 68HC11• Where is the value to be loaded?

• $23– This is the operand for the opcode. For this instruction, 23 is the

constant value to be loaded into the A register.

Simple Example (cont)

• Example: $E002 c6 be• $E002:

– This is the memory location or address where this program or data is located.

• $C6 (note the change from the previous instruction)– This is the Operation Code or opcode– The opcode is the Hex (i.e. binary) representation of the

instruction.• $c6 means LDAB # or

– Load the B register with a constant value for the 68HC11• Where is the value to be loaded?

• $be– This is the operand for the opcode. For this instruction, 23 is the

constant value to be loaded into the A register.

Simple Example (cont)

• $E004 1b– $1b = ABA – Note: we don’t need an operand for this one

• $E005 b7 10 00– $b7 = STAA in an extended memory address– address is stored at the operand – $1000 is the storage address

• Note: the contents at location $1000 are overwritten

Simple Example (cont)

• $E008 20 fe– $20 = This is the BRAnch opcode.

• The program counter (PC) is set to• PC= PC + relative address (signed addition)

– $fe is the relative address. – After fetching the instruction, the PC points to the next

instruction.– In this case

• PC = $E00A, after fetching this instruction• PC = $E00A + $FE = $E00A + $FFFE(sign extended)• PC = $E008 (or we branch right back to this instruction)• This is an infinite loop. How do we get out of this?

Simple Example (cont)• Hit the RESET button!!!!!!

• $FFFE E0 00– This is data (not program) stored in the

Interrupt Vector Table (IVT) at the Reset interrupt location.

– This will cause our program to begin executing the program stored at location $E000 whenever we hit the Reset button.

Simple Example (cont)• In memory, our program appears as

$E000: 86 23 c6 be 1b b7 10 00 20 fe ……….. $FFFE: E0 00

When we hit the Reset button, the Program counter is set equal to the data stored at location $FFFE.

Instruction Execution Cycle• How does this all work?

– Recall, Instruction Execution Cycle– Fetch – Decode – Execute

• Fetch stage– Operations code (op-code) is loaded from memory into

the Instruction Register (IR)

• Decode stage– Instruction is “decoded” into a set of “micro-instructions”

(e.g. FSM)

• Execution stage– The micro-instructions are executed. This may involve

loading the “operand” from memory.

Simple Example (cont)

• When we hit the Reset button, the Program counter is set equal to the data stored at location $FFFE, or

1. PC ($FFFE) = $E000– Program counter is loaded with the contents

of memory location $FFFE

Simple Example (cont)2. Fetch Opcode

IR ($E000) = 86

3. Decode OpcodeCPU decodes as LDAA #

4. Execute opcodeCPU fetches operand as next byte from program memory.Instruction is executed. Program counter is incremented PC = PC + 2

• Process repeats for next byte

Simple Example (cont)2. Fetch Opcode

IR ($E002) = c6

3. Decode OpcodeCPU decodes as LDAB #

4. Execute opcodeCPU fetches operand as next byte from program memory.Instruction is executed. Program counter is incremented PC = PC + 2

• Process repeats for next byte• …………..

TPS Quiz

THRSIM11

Design Procedure

1. Use THRSIM11 to develop program

2. Assemble program with THRSIM11 assembler

3. Correct any assembly errors

4. Simulate program using THRSIM11 simulator

5. Correct any logical errors

6. Download program to board (if needed)

7. Correct any hardware errors

Assembler

• An assembler converts the assembly language program into machine code.

• The machine code is also known as the op-code. We will use a Mnemonic (e.g. LDAA) to represent this op-code.

Assembler – THRSIM 11

• We’ll use the THRSIM11 assembler

• Syntax: () = Optional– (Label) Opcode (Operand) (Comment)– Ex:

• Loop: LDAA #$2F Load Accumulator A with

• Hex $2f

•

Label Field - Optional

• Must start in the first position of line• One to fifteen characters

– Upper- and lower-case letters a-z• Case sensitive

– Digits 0-9, Period (.), Dollar sign ($), or underscore (_)

• First character must be– Alphabetic, period, or underscore

• Last character should be a colon (:) (BP)• Label may be by itself

Label Field - Optional

• Labels must be unique

• If an asterisk (*) is the first character, the rest of the line is considered a Comment.

Op-code or Operation Field

• Required field

• Contains mnemonic for the operation or assembler directive (or pseudo-operation)

• Not case sensitive

• Must not begin in the first position– Will be treated as label if it begins in the first

position

Operand Field

• Operand of Op-Code (if, needed)

• Can consist of:– Symbols – assembler replaces the symbol

with its value• Ex: COUNT EQU $5F• LDAA COUNT• EQU is an assembler directive. It instructions the

assembler to replace the symbol COUNT with the value of $5F, so the above is equivalent to:

– LDAA $5F

Operand Field

• Constants - Value does not change– Formats:

• $ = Hex: Ex: COUNT EQU $5A• % = Binary: Ex: COUNT EQU %01011010• Blank = Decimal: Ex: COUNT EQU 70• ‘ = ASCII: COUNT EQU ‘0 (i.e. $30)• Note: assembler will convert each format to HEX

– Constants must be consistent with • bit width (i.e. 8-bit or 16-bit)• type (i.e. signed or unsigned)

Operand Field

• Expressions –Assembler can evaluate simple expressions to compute the value of the operand– Operators

• + = Addition• - = Subtraction• * = Multiplication• / = Division

Operand Field

• Expressions –– Operators (continued)

• % = Remainder after division• & = Bitwise AND• | = Bitwise OR• ^ = Bitwise XOR

– Evaluated by assembler from left to right– Signed two’s complement arithmetic– Can use only constants

Operand Field

• Expressions –– Examples

• COUNT EQU $1F• EX1: LDAA COUNT+$0A

– A ($1F+$0A) = ($19)

Assembler Directive: EQU

• Equates a symbol to a value• Syntax:• Label EQU Expression (comment)• Note: the Label is NOT stored in memory. Label

is just an alias for expression• Ex:

– TEST EQU $3000– LDX #TEST– This is the same as

LDX #$3000

Assembler Directive: ORG

• Set assembler’s counter to expression• Syntax: • (Label) ORG Expression (comment)• Ex:

– Code EQU $3000– ORG Code – Assembler assumes Program Counter now

contains the value of $3000

Assembler Directive: RMB

• Reserve memory bytes• Syntax: • (Label) RMB Expression (comment)• Ex:

– Buffer1 RMB $10– Buffer2 RMB $10– The assembler saves $10 bytes of RAM for a data

buffer located at address Buffer1. For example, if Buffer1 is located at address $2000, assembler will locate Buffer2 at $2000+$0010 = $2010.

Assembler Directive: FCB

• Form constant byte• Syntax: • (Label) FCB Expression, (Exp), (Exp), (comment)

• Stores a constant byte in a memory location. Note: difference with EQU

• Ex:– Data EQU $1000 – ORG Data– Buffer1 FCB $10,$FA,$2F– Result is at memory address $1000, we have– $1000: 10 FA 2F

Assembler Directive: FDB• Stands for “Form Double-Byte constant”• Syntax:

– [label][:] FDB expression [, expression] … [, expression] [comment]

• Semantics (meaning, function, behavior): – Stores one or more 16-bit values in subsequent memory

locations.• Uses “Big Endian” format: stores MSB first, LSB second.

• Note the difference between this and EQU!– EQU assigns the symbol (label) to the value of given Expression– FCB, FDB, etc. assign the symbol to the current address, and

specify the contents of memory starting at that address

• Example: Buffer1 FDB $10FA,$2FFF

– Contents of memory bytes starting at address Buffer1: • $10, $FA, $2F, $FF

Using square brackets [ ] to denote optional elements

Assembler Directive: FCC• Stands for “Form Constant Character string”• Syntax:

– [label][:] FCC “string“ [comment]

• Converts the given string into its ASCII equivalent.– ASCII = American Standard Code for Information

Interchange• See http://www.asciitable.com for a list of codes.

• Example:String: FCC “Hello“

– The data bytes stored at address String are• $48, $65, $6c, $6c, $6f

A few other useful directives• BSZ – “Block Storage of Zeros”

– A.k.a. ZMB “Zero Memory Bytes”– Like RMB, but clears each memory byte to 0.

• FILL – “Fill memory with constant”– Syntax: FILL value, howMany– Stores value at next howMany bytes.

• OPT – “Assembler output options”– Syntax: OPT opt1 [, opt2 …]

• Each opti is one of these tags: c, cre, l, noc, nol, or s.

– See textbook, pp.29 & 31 for details.

• PAGE – “Output a page break in program listing”

Comment Field

• Available with all assembler directives and instructions.

• Placed after operand field– Use asterisk to indicate comment in first

character position

• Need comments at the beginning of program (BP)

• Need comment on every line. (BP)

EEL-4746 Best Practices

EEL-4746 Best Practices

1. All programs submitted for homework assignments must begin with the following comment:

**************************** EEL-4746 Spring 2004 Semester* Homework #N – Due (Due Date)* Problem #M* Name of Partner A* Name of Partner B***************************** Description of Program

EEL-4746 Best Practices

2. All subroutines must begin with the following comment**************************** Subroutine Name: Mysub* Input parameter list:* Output parameter list:* Registers changed list:***************************** Description of Subroutine

EEL-4746 Best Practices

3. All lines must contain a comment

4. All labels must end with a colon (“:”)

5. Must declare and use a symbol for all constants, using EQU.

EEL-4746 Best Practices6. Program must have a well-organized overall format, such

as: Header Comment, from previously************************ Standard Symbols

Data EQU $0200 ; Start of RAM in U5, to $FFFProgram EQU $1040 ; Just above config registersStack EQU $7FFF ; Top of RAM in U5Reset EQU $FFFE ; Reset vector location************************(Define your own symbols here)

************************ Program area

ORG ProgramStart: 1st program line ; comment

************************ Data area

ORG DataSymbol Directive …

Example

• Write an 68HC11 assembly language program to monitor the temperature of a power plant. If the temp >= 50C, sound the alarm.– Given the following memory addresses

• Analog to digital converter = temperature (in Hex)• Port B – bit 0 = Output alarm

– 0 – no alarm– 1 – alarm will sound

Pseudo-Code

MC68HC11 Instruction Set

M68HC11 Instruction Set

• Categories– Load and Store– Stack– Transfer– Decrement and Increment– Clear and Set – Shift and Rotate– Arithmetic Instructions

Arithmetic Instructions

• Add and Subtract

• Decimal Arithmetic

• Negating Instruction

• Multiplication

• Division

Other Instructions

• Logic

• Data Test

• Conditional Branch

• Unconditional Jump and Branch

• Subroutines

• Interrupt

• Miscellaneous

Instruction Cycle

1. IR (PC) Opcode is fetched into Instruction Register

2. Instruction is decoded

3. Data or address is loaded from memory (if needed) Program Counter is updated

4. Instruction is executed (if needed)

Load Instructions

• Mnemonic Operation– LDAA – Load Accumulator A – LDAB – Load Accumulator B– LDD - Load Accumulator D– LDS - Load Stack Pointer– LDX - Load Index X Register– LDY - Load Index Y Register

• Addressing modes: All except INH• Condition codes: Set N,Z and V=0

Mnemonic Machine Code

• Immediate Mode– LDAA #$02 86 02

• Direct Addressing Mode– LDAA $02 96 02

• Extended Addressing Mode– LDAA $1002 B6 10 02

• Register Indexed (X = $1000)– LDAA $02, X A6 02

• Register Indirect (X = $1002)– LDAA 0,X A6 00

Store Instructions

• Mnemonic Operation– STAA – Store Accumulator A– STAB – Store Accumulator B– STD – Store Accumulator D– STS – Store Stack Pointer– STX – Store Index X Register– STY – Store Index Y Register

• Addressing modes: All except IMM and INH• Condition codes: N,Z and V=0

Mnemonic Machine Code

• Immediate Mode– STAA #$02 (Illegal operation)

• Direct Addressing Mode– STAA $02 5A 02

• Extended Addressing Mode– STAA $1002 7A 10 02

• Register Index (X = $1000)– STAA $02, X 6A 02

• Register Indirect (X = $1002)– STAA 0,X 6A 00

Notation: Memory Locations

• $C000: 12 34 56 78 9A BC DE F0– This means the hex bytes shown are

contained in consecutive memory locations starting from address $C000.

• In other words:– [$C000]=$12, [$C001]=$34, [$C002]=$56,

[$C003]=$78, [$C004]=$9A, [$C005]=$BC,[$C006]=$DE, [$C007]=$F0

Notation: Memory Locations

• You can visualize the memory bytes as arranged in a table…– $C000: 12 34 56 78

9A BC DE F0– Gives this table:

Address Data

$C000 $12

$C001 $34

$C002 $56

$C003 $78

$C004 $9A

$C005 $BC

$C006 $DE

$C007 $F0

16-bit Load and Store

• For a 16-bit (2 byte) load and store, the high byte is stored at the

lower address and the low byte is stored at the higher address. – This is called “big endian” byte ordering

• The “big end” of the word comes first.

• Ex: $C000: 12 34 56 78 9A BC DE• LDAA $C001 A ($C001) = $34• LDX $C002 X $5678• STX $C004 ($C004) $5678• $C000: 12 34 56 78 56 78

Transfer Register Instructions

• Mnemonic Operation– TAB : Transfer A to B: B (A)– TBA : Transfer B to A: A (B)– TSX : Transfer SP to X: X (SP) + 1– TSY : Transfer SP to Y: Y (SP) +1– TXS : Transfer X to SP: SP (IX) -1– TYS : Transfer X to SP: SP (IY) – 1– XGDX: Exchange D and X: X D– XGDY: Exchange D and Y: Y D

• Addressing modes: INH Only• Condition codes: N,Z and V=0 (TAB and TBA

only)

Decrement Instructions

• Mnemonic Operation– DECA : Decrement A: A <- (A) – 1– DECB : Decrement B: B <- (B) – 1– DES : Decrement SP: SP <- (SP) -1– DEX : Decrement X : X <- (X) - 1– DEY : Decrement Y : Y <- (Y) – 1

• Addressing modes: INH Only• Condition codes:

– DECA,DECB: N,Z and V– DEX, DEY: Z– DES: none

Decrement Instructions

• Mnemonic Operation– DEC : Decrement Mem: (M) <- (M) -1

• Addressing modes: All but INH

• Condition codes: N,Z and V

Increment Instructions

• Mnemonic Operation– INCA : Increment A: A <- (A) + 1– INCB : Increment B: B <- (B) + 1– INS : Increment SP: SP <- (SP) + 1– INX : Increment X : X <- (X) + 1– INY : Increment Y : Y <- (Y) + 1

• Addressing modes: INH Only• Condition codes:

– INCA,INCB: N,Z and V– INX, INY: Z– INS: none

Increment Instructions

• Mnemonic Operation– INC : Increment Mem: (M) <- (M) +1

• Addressing modes: All but INH

• Condition codes: N,Z and V

Clear Instructions

• Mnemonic Operation– CLR : Clear Memory: (M) <- 0– CLRA : Clear A: A <- 0– CLRB : Clear B: B <- 0

• Addressing modes: – CLR: EXT, IX, IY– CLRA, CLRB: INH only

• Condition codes: N=0,Z=1,V=0,C=0

Clear and Set Bit Instructions

• Mnemonic Operation– BCLR : Clear Bits– BSET : Set Bits

• Addressing modes: Direct, Index

• Condition codes: N,Z,V=0

• Example:– BCLR $33 $AA

• Clear bits 2,4,6, and 8 at memory add $33

Arithmetic Instructions - ADD

• Mnemonic Operation– ABA: Add B to A: A <- (A) + (B)– ABX: Add B to X: X <- (X) + (B)– ABY: Add B to Y: Y <- (Y) + (B)– ADDA: Add memory to A: A <- (A) + (M)– ADDB: Add memory to B: B <- (B) + (M)– ADDD: Add memory to D: D <- (D) + (M:M+1)– ADCA: Add memory to A and C: A<- (A)+ (M) +C– ADCB: Add memory to B and C: B<- (B)+ (M) +C

• Addressing modes: INH or All except IHN• Condition codes: N,Z,V,C (except X and Y)

Arithmetic Instructions - Sub

• Mnemonic Operation– SBA: Sub B from A: A <- (A) + (B)– SUBA: Sub memory from A: A <- (A) - (M)– SUBB: Sub memory from B: B <- (B) - (M)– SUBD: Sub memory from D: D <- (D) - (M:M+1)– SBCA: Sub memory and C from A: A<- (A)-(M)-C– SBCB: Sub memory and C from B: B<- (B)-(M)-C

• Addressing modes: INH or All except IHN• Condition codes: N,Z,V,C

Arithmetic Instructions - Neg

• Mnemonic Operation– NEG: 2’s comp memory: (m) -1*(M)– NEGA: 2’s comp A : A -1*(A)– NEGB: 2’s comp B : B -1*(B)

• Addressing modes: INH or Ext, Ix, Iy• Condition codes: N,Z,V,C

Condition Code Register

• Special Register used for control and provide arithmetic information to programmer and CPU.

S X H I N Z V C

Condition Code Register

Condition Code Register

S X H I N Z V C

7 6 5 4 3 2 1 0

S = StopX = X Interrupt BitI = Interrupt Mask

N = NegativeZ = ZeroV = OverflowC = CarryH = Half Carry

Control BitsArithmetic Bits

Compare Instructions - CMP

• Mnemonic Operation– CBA: Compare B to A: A - B– CMPA: Compare memory to A: A - (M)– CMPB: Compare memory to B: B - (M)– CMPD: Compare memory to D: D - (M:M+1)– CMPX: Compare memory to X: X - (M:M+1)– CMPY: Compare memory to Y: Y – (M:M+1)

• Addressing modes: INH or All except IHN• Condition codes: N,Z,V,C

– Note: Only Condition Code Register (CCR) is changed by these instructions. All other registers unaffected.

Examples of SBA (A−B) resultsMinuend (A)

A−B 00(0)

01(1)

7F(127)

80(128, −128)

81(129, −127)

FF(255, −1)

Su

btrah

end

(B)

00(0)

00NZVC

01NZVC

7F NZVC

80NZVC

81NZVC

FFNZVC

01(1)

FFNZVC

00NZVC

7E NZVC

7FNZVC

80NZVC

FENZVC

7F(127)

81NZVC

82NZVC

00NZVC

01NZVC

02NZVC

80NZVC

80(128, −128)

80NZVC

81NZVC

FFNZVC

00NZVC

01 NZVC

7F NZVC

81(129, −127)

7FNZVC

80NZVC

FENZVC

FFNZVC

00NZVC

7E NZVC

FF(255, −1)

01NZVC

02NZVC

80NZVC

81NZVC

82NZVC

00NZVC

Branch Instructions

• A Branch Instruction typically follows a Compare instruction. The Branch instruction will branch if certain CCR bits are set or clear

Branch Instructions

• BRA – Branch Always– Unconditional “Branch” (i.e. GoTo)

• BEQ - Branch if equal– Z bit = 1

• BNE – Branch if not equal– Z bit = 0

• BCC – Branch if Carry Clear– C bit = 0

• BCS – Branch if Carry Set– C bit = 1

Branch Instructions

• BMI - Branch if Minus– Branch if N = 1

• BPL – Branch if “Plus” (Positive or Zero)– Branch if N = 0

• BVS – Branch if Overflow Set– Branch if V=1

• BVC – Branch if Overflow Clear– Branch if V=0

Branch InstructionsUnsigned

• BHI - Branch if High– Unsigned, Branch if C OR Z = 0

• BHS – Branch if Higher or Same– Unsigned, Branch if C=0

• BLO – Branch if Low– Unsigned, Branch if C = 1

• BLS – Branch if Lower or Same– Unsigned, Branch if C OR Z = 1

Branch InstructionsSigned

• BGE - Branch if Greater Than or Equal– Signed, Branch if N XOR V = 0

• BGT – Branch if Greater Than– Signed, Branch if Z OR (N XOR V) = 0

• BLE – Branch if Less Than or Equal– Signed, Branch if Z OR (N XOR V) = 1

• BLT – Branch if Less Than– Signed, Branch if (N XOR V) = 1

Signed vs. Unsigned Inequalities

Branch Test Rationale

Signed

BLT NV = 1 A<B if A−B is really negative; but if V=1 then the sign bit is wrong.

BGE NV = 0 A≥B if it’s not true that A<B.

BLE Z+(NV) = 1 A≤B if either A<B,or if A=B (that is if A−B=0, so Z=1).

BGT Z+(NV) = 0 A>B if it’s not true that A≤B.

Unsigned

BLO,BCS C = 1 A<B if A−B produced a carry(borrow) out of its high-order bit.

BHS,BCC C = 0 A≥B if it’s not true that A<B.

BLS C+Z = 1 A≤B if either A<B or A=B (Z=1).

BHI C+Z = 0 A>B if it’s not true that A≤B.

The Seven Possible Subtraction/ Comparison Outcomes

ExamplesCondition

Code Flags

Universal Signed Only UnsignedSubtract

B from A (SBA)BNE

BEQ

BMI

BPL

BGE

BLE

BGT

BLT

BVS

BVC

BHI

BHS

BLO

BLSA − B = ? N Z V C

FF − 80 = 7F N Z V C

01 − FF = 02 N Z V C

81 − 7F = 02 N Z V C

80 − 80 = 00 N Z V C

FF − 7F = 80 N Z V C

80 − 81 = FF N Z V C

7F − 81 = FE N Z V C

• They are: (1) Normal, (2) Carry, (3) Overflow, (4) Zero, (5) Negative, (6) Negative-Carry, and(7) Negative-Overflow-Carry.

Proof this list is exhaustive

• If Z=1, then clearly N=V=C=0.– Thus our list only includes one line where Z=1.

• If V=1, then C=N, because:– If V=1, then either A−B>127, or A−B < −128.

• If A−B>127, then A>0, and B<0 (so that −B>0).– Thus, A<$80 and B≥$80, so A−B will do a carry (C=1).– Also, the result of A−B will be <0 (≥$80), so N=1.

• If A−B<−128, then A<0 and B>0 (so that −B<0).– Thus, A≥$80 and B<$80, so A−B causes no carry (C=0).– Also, the result of A−B will be >0 (<$80), so N=0.

– In either case, we note that C=N.• For V=0 we list all 4 combinations of C and N,

but for V=1 we need only C=N=0 and C=N=1.

Branch Examples• Example 1

– LDAA #$F2 (-14, signed) (242 unsigned)– LDAB #$F0 (-16 signed) (240 unsigned)– CBA (Compute A-B)

• Result is $F2-$F0 = $F2 + $10 = $102 => $02– N bit = 0 (result is not negative)– Z bit = 0 (result is not zero)– V bit = 0 (2’s comp overflow did not occur)– C bit = 0 (this is really, not carry out)

– Note: A > B for both signed and unsigned numbers.– The following instructions will branch

• BNE,BGE,BGT,BHI,BHS

Branch Example

• Example 2– LDAA #$F2 (-14, signed) (242 unsigned)– LDAB #$F2 (-14, signed) (242 unsigned)– CBA (Compute A-B)

• Result is $F2-$F2 = $F2+$0E=$100 => $00– N bit = 0– Z bit = 1 (result is zero)– V bit = 0– C bit = 0 (not carry out)

– Note: A = B for both signed and unsigned numbers.– The following instructions will branch

• BEQ,BGE,BLE,BHS,BLS

Branch Example

• Example 3– LDAA #$F2 (-14, signed) (242 unsigned)– LDAB #$FF (-1, signed) (255 unsigned)– CBA (Compute A-B)

• Result is $F2-$FF = $F2 + $01 = $0F3– N bit = 1 (result is negative: -13)– Z bit = 0– V bit = 0– C bit = 1 (not carry out)

Note: A < B for both signed and unsigned numbers.Note: A < B for both signed and unsigned numbers.The following instructions will branchThe following instructions will branch

BNE,BLE,BLT,BLO,BLSBNE,BLE,BLT,BLO,BLS

Branch Example

• Example 4– LDAA #$F2 (-14, signed) (242 unsigned)– LDAB #$02 (2, signed) (2 unsigned)– CBA (Compute A-B)

• Result is $F2-$02 = $F2+$FE=$1F0– N bit = 1 (result is negative: signed- positive unsigned)– Z bit = 0– V bit = 0– C bit = 0 (not carry out)

– Note: A < B for signed and A>B unsigned numbers.– The following instructions will branch

• BNE,BLE,BLT,BHI,BHS

Branch Example

• Example 5– LDAA #$02 (2, signed) (2 unsigned)– LDAB #$F2 (-14, signed) (242 unsigned)– CBA (Compute A-B)

• Result is $02-$F2 = $02+$0E=$10– N bit = 0 (result is positive signed: negative unsigned)– Z bit = 0– V bit = 0– C bit = 1 (not carry out)

– Note: A > B for signed and A<B unsigned numbers.– The following instructions will branch

• BNE,BGE,BGT,BLO,BLS

Branch Example

• Example 6– LDAA #$80 (-128 signed, +128 unsigned)– LDAB #$7F (+127 signed, +127 unsigned)– CBA (Compute A-B)

• Result is $80-$7F = $80+$81=$101– N bit = 0 (result is negative unsigned, positive signed)– Z bit = 0– V bit = 1 (Two’s comp overflow)– C bit = 0 (not carry out)

• Two’s comp overflow occurs when the carry into the MSB is not equal to the carry out of the MSB. In this case, carry in =0 and carry out = 1

Branch Example

• Example 6– LDAA #$80 (-128 signed, +128 unsigned)– LDAB #$7F (+127 signed, +127 unsigned)– CBA (Compute A-B)

• Result is $80-$7F = $80+$81=$101– N bit = 0 (result is negative unsigned, positive signed)– Z bit = 0– V bit = 1 (Two’s comp overflow)– C bit = 0 (not carry out)

– Note: A < B for signed and A>B unsigned numbers.– The following instructions will branch

• BNE,BLE,BLT,BHS,BHI

Example 4-43• Let A=$FF and ($1000) = $00

• Given Code Fragment:– CMPA $1000

• Indicate whether each of the following branches will be taken

• BGE, BLE, BGT, BLT, BEQ, BNE, BHS, BLS, BHI, BLO

Example 4-43: Solution• Let A=$FF and ($1000) = $00

• BGE, BLE, BGT, BLT, BEQ, BNE, BHS, BLS, BHI, BLO

• CMPA $1000– As an unsigned number A = 255– So, for unsigned numbers A>$00, A <> $00

• Unsigned Branches– BHS yes, BLS no, BHI yes, BLO no

Example 4-43: Solution• Let A=$FF and ($1000) = $00

• BGE, BLE, BGT, BLT, BEQ, BNE, BHS, BLS, BHI, BLO

• CMPA $1000– As a signed number A = -1– So, for signed numbers A<$00, A <> $00

• Signed Branches– BGE no, BLE yes, BGT no, BLT yes

Example 4-43: Solution Summary

• Signed Branches– BGE no, BLE yes, BGT no, BLT yes

• Unsigned Branches– BHS yes, BLS no, BHI yes, BLO no

• Other Branches– BEQ no, BNE yes

TPS Quiz

Test Instructions - TST

• Test if Memory = 0• Mnemonic Operation

– TST: Test memory = 0: (m) - 0– TSTA: Test A = 0 : A - 0– TSTB: Test B = 0: B - 0

• Addressing modes: INH or Ext, X, Y• Condition codes: N,Z,V=0,C=0

Test Example

PULA ; A (SP)

* Pull instruction does not affect CCR

TSTA ; Tests if A=0

* This instruction will set N and Z bits

BPL Label ; Branch if A>0

•

Test Bits Instructions - BIT

• Mnemonic Operation– BITA: AND Register A with memory: A AND (MEM)– BITB: AND Register B with memory: B AND (MEM)

• Addressing modes: IMM,DIR, Ext, X, Y• Condition codes: N,Z,C=V=0• Note: Memory does NOT change, Only CCR

Bit Example

Memory EQU $1000 MASK EQU %10000000……… LDAA #MASK ; A ($80) BITA Memory ; Result = $80 AND $FF = $80 ; N=1 and Z=0

ORG DataMemory FCB $FF*

Shifting Instructions

Shift Bit Instructions - ASL

• Mnemonic Operation– ASL Arithmetic Shift Left Memory– ASLA: Arithmetic Shift Left A– ASLB: Arithmetic Shift Left B– ASLD: Arithmetic Shift Left D (16 bits)

• Addressing modes: INH or Direct, Index• Condition codes: N,Z,V,C

7 2356 4 1 0C 0

ASL

Multiplies by 2

Shift Bit Instructions - ASR

• Mnemonic Operation– ASR Arithmetic Shift Right Memory– ASRA: Arithmetic Shift Right A– ASRB: Arithmetic Shift Right B– ASRD: Arithmetic Shift Right D (16 bits)

• Addressing modes: INH or Direct, Index• Condition codes: N,Z,V,C

7 2356 4 1 0 C

ASR

Sign bit preserved Divides by 2

Shift Bit Instructions - LSL

• Mnemonic Operation– LSL Logical Shift Left Memory– LSLA: Logical Shift Left A– LSLB: Logical Shift Left B– LSLD: Logical Shift Left D (16 bits)

• Addressing modes: INH or Direct, Index• Condition codes: N,Z,V,C

Multiplies by 2

7 2356 4 1 0C 0

LSL

Shift Bit Instructions - LSR

• Mnemonic Operation– LSR Logical Shift Right Memory– LSRA: Logical Right Left A– LSRB: Logical Right Left B– LSRD: Logical Right Left D (16 bits)

• Addressing modes: INH or Direct, Index• Condition codes: N=0,Z,V,C

Divides by 2

7 2356 4 1 0 C0

LSR

Shift Bit Instructions - ROR

• Mnemonic Operation– ROR Rotate Right Memory– RORA: Rotate Right A– RORB: Rotate Right B

• Addressing modes: INH or Direct, Index• Condition codes: N,Z,V,C

7 2356 4 1 0 C

ROR

Shift Bit Instructions - ROL

• Mnemonic Operation– ROL Rotate Left Memory– ROLA: Rotate Left A– ROLB: Rotate Left B

• Addressing modes: INH or Direct, Index• Condition codes: N,Z,V,C

7 2356 4 1 0 C

ROL

Logic Instructions

• Mnemonic Operation– ANDA: Logical A and mem: A A AND (M)– ANDB: Logical B and mem: B B AND (M)– EORA: Exclusive OR A and mem: AA XOR (M)– EORB: Exclusive OR B and mem: BB XOR (M)– ORAA: OR A and mem: A A OR (M)– ORAB: OR B and mem: B B OR (M)

• Addressing modes: All except IHN• Condition codes: N,Z,V,C

Complement Instructions

• Mnemonic Operation– COM: 1’s Complement of mem: (M) (M)– COMA: 1’s Comp of A: A (A) – COMB: 1’s Comp of B: B(B)

• Addressing modes: INH or EXT, X, Y (mem)• Condition codes: N,Z,V=0,C=1

Subroutine Instructions

JMP/JSR/BSR/RTS

JMP Instructions

• Jump to Address– Similar to BRA but uses absolute address

• Mnemonic Operation– JMP Address

• Addressing modes: EXT, X, Y – Condition codes: none– PC Address

JMP Example

Program EQU $E000

Stack EQU $00FF

ORG Program

E000: 8E 00 FF Top: LDS #Stack

E003: 7E E0 03 Done: JMP Done

********** Compare with

E000: 8E 00 FF Top: LDS #Stack

E003: 20 FE Done: BRA Done

Why use JMP instead of BRA?Why use JMP instead of BRA?

Why use JMP instead of BRA?We can only Branch up to -128 to +127 bytes from the

current address. If we need to Branch to an address outside of this range, we’ll need to use JMP instruction.

* EXAMPLE. Assume FAR_LABEL is +$1000 bytes away from this address

TSTA

BEQ FAR_LABEL

LDAA #NUMA ; This is the A<>0 code

* This code will give us an error (out of range)

Why use JMP instead of BRA?

* We need to use a JMP instead

TSTA

BNE L1 ; Use a BNE because the label

; is local.

JMP FAR_LABEL

L1: LDAA #NUMA ; This is the A<>0 code

JSR Instructions

• Jump to Subroutine– Similar to JMP except we have the ability to return to

the calling program. Same as HLL.

• Mnemonic Operation– JSR Address

• Addressing modes: DIR, EXT, X, Y – Condition codes: none

• PSH PC ; Program Counter pushed onto stack• PC Address

JSR Instruction

• JSR– Pushes Program Counter onto Stack

• Note: PC is pointing to the next instruction

– Loads PC with Addressing of Subroutine• Starts executing program beginning at EA

– How do we return from the subroutine?

BSR Instructions

• Branch to Subroutine• Mnemonic Operation

– BSR Relative_Address

• Addressing modes: REL – Condition codes: none

• PSH PC ; Program Counter pushed onto stack• PC PC + Relative_Address• Note: PC is pointing to the NEXT instruction.

JMP/JSR/BSR Instructions

• JMP – Jump to Address– Unconditional jump to address

• JSR- Jump to Subroutine– Unconditional jump to subroutine

• BSR – Branch to Subroutine– Unconditional branch to a subroutine

RTS - Instruction

• RTS – Return from Subroutine– PULL PC from Stack

• Recall this contains the EA of the instruction following the original JSR/BSR

– PC Value pulled from stack• Execute program

– Note: You must POP anything you have PUSHed onto the stack or the RTS will start executing the wrong program

Special Arithmetic Operations

Hexadecimal Number System

• Base 16• Sixteen Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F• Example: EF5616

• Positional Number System • 1 4 3 2 1 016 16 16 16 1616n 0000 0

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 A

1011 B

1100 C

1101 D

1110 E

1111 F

Packed Binary Coded Decimals (Packed BCDs)

• Use 4-bits 0-9 to represent a decimal number

• Example: 123410

– As hex = $4D2– As BCD =$0102, $0304– As Packed BCD = $1234

• Example: 5137 – As Hex = $1411– As BCD = $0501,$0307– As Packed BCD = $5137

Subroutine Example************************** Subroutine Name: Bcd2Asc* Input parameter list: A* Output parameter list: A,B***************************** This routine converts a Packed BCD byte in A* into a pair of ASCII characters in A,B.**************************************************LOWER EQU $0F ; Mask for low nybbleUPPER EQU $F0 ; Mask for high nybbleASCII EQU $30 ; ASCII code for numeral 0Bcd2Asc: TAB ; Copy A register to B ANDB #LOWER ; Mask-select lower nybble of B ADDB #ASCII ; Convert B to ASCII code ANDA #UPPER ; Mask-select upper nybble of A LSRA ; Logical shift right 4 positions LSRA LSRA LSRA ADDA #ASCII ; Convert A to ASCII RTS ; Return result in A,B

Using Subroutine * Standard equatesCODE EQU $E000 ; Start code in EEPROMDATA EQU $0000 ; Start data in page 0 internal RAMSTACK EQU $7FFF ; Start stack at top of external RAM.EOS EQU $FF ; We’ll use hex $FF to mark end-of-string of BCD bytes.

ORG DATA ; Begin data segment.array FCB $01,$23,$45,$67,$89,EOS ; Array of packed BCD bytesresult RMB 10 ; We'll put the resulting chars here

ORG CODE ; Begin code segment.Main: LDS #STACK ; Load stack pointer LDX #array ; Load address of data array LDY #result ; Ditto for result arrayLoop: LDAA 0,X ; Get byte to convert CMPA #EOS ; Compare byte with end of string BEQ Done ; If end of string, then stop JSR BCD2ASC ; Call subroutine to do conversion STD 0,Y ; Store D in result array INX ; Go to the next input byte INY ; Go to next output word INY BRA Loop ; Do it all againDone: WAI ; End of main program, wait for interruptsInfloop: BRA Infloop ; If we ever get here, stay here

Decimal Arithmetic Instruction

• DAA – Decimal Adjust A Instruction– Used to adjust the result of the addition of two

packed BCDs– Use immediately after the ADDA instruction.

• Affects the A register

– Example:• 34 = $22 (hex) or $34 as packed BCD

• 29 = $1D (hex) or $29 as packed BCD

• $34+$29 = $5D (not a valid packed BCD)

• DAA: A (A) +$06 = $63 (correct packed BCD)

Decimal Arithmetic Instruction

• DAA – Decimal Adjust Instruction– Why do we add $06?– Note:

• $01+$09 = $0A + $06 = $10

– What about $01+$02 = $03?– DAA checks CCR to determine if adjust is

needed, so DAA: $03+$00 = $03– See reference manual (p.536) for a

complete list of cases

MUL Instruction

• MUL – Multiply Instruction– Multiplies 8-bit unsigned numbers loaded into the A

and B registers– D AB– Max result = $FF$FF = $FE01 = 65,020 =2552

– For signed multiplication:• Determine sign of A and B

– (−)(−)=(+), (+)(+)=(+), (−)(+)=(−), (+)(−)=(−)– NEG negative numbers– MUL, NEG (if needed)

• Range: -1282 = -16,384 = $E100 to +1272 = 16,129 = $3F01

IDIV Instruction • IDIV – Integer Divide Instruction

– Divides 16-bit unsigned D register by the 16-bit unsigned X register

– Quotient is stored in the X register• X Integer portion of D/X

– Remainder is stored in the D register • D D – Integer portion of D/X

– If X is $0000, C 1, and D $FFFF– For signed division

• Determine sign of A and B– (-)/(-)=+ (+)/(+)=+ (-)/(+)=(-) (+)/(-)=-– NEG negative numbers– IDIV, NEG (if, needed)

Fractional Numbers

• Recall 20=1, 21=2, 22=4, ….

• But, we can also go the other way– 2-1=0.5, 2-2=0.25, 2-3=0.125, 2-4=0.0625,…

• In general, we have 2-n=1/2n

• So, for example, to represent– 2.5 = %10.10 and 5.25 = %101.01

• Check: 2+0+0.5+0=2.5• Check: 4+0+1+0+0.25=5.25

Fractional Numbers• We have

– 2.5 = %10.10 and 5.25 = %101.01

• As 8 bit numbers, these become– %000010.10 and %000101.01

• Now, we really DON’T have a way to represent the decimal point in our numbers, so we have to remember where it is located.

• So really, we have • 2.5 = %00001010 = $0A• 5.25 = %00010101 = $15• And we remember that we are using 2 bits for the

fractional part.

Fractional Numbers

• Let’s use 16-bit numbers where 4-bits (or one nybble) are reserved for the fractional part

• So, Y = $NNN.N• Example, What is 375.875 in Hex?• 375 $177• 0.875 = 1*0.5+1*0.25+1*0.125+0*0.0625

= %1110 = $E

• Or, 375.875 = $177E

Fractional Numbers

• Let’s use 16-bit numbers where 4-bits (or one nybble) are reserved for the fractional part

• So, Y = $NNN.N• Example, What is $24E3 as a fractional decimal?

• $24E 590• $3 = 0*0.5+0*0.25+1*0.125+1*0.0625=0.1875• Or, $24E3 = 590.1875

FDIV Instruction • FDIV – Fractional Divide Instruction

– Divides 16-bit unsigned D register by the 16-bit unsigned X register

– D register is assumed less than X register. (Answer is less than one)

– Radix point is assumed to be the same– Fractional quotient is stored in the X register.

Ex: %0.1010….– Remainder is stored in the D register – If X is $0000, C 1, and D $FFFF

Miscellaneous Instructions

NOP Instruction

• NOP – No operation– Performs “no operation”– Can be used for “crude” timing routines

• 2 Clock Cycles for each instruction

– Also used for debugging• Insert NOPs in place of SWI

– Software Interrupts

STOP Instruction

• STOP– STOP operation– Puts the CPU “to sleep”

• Can be “awakened” by using an interrupt

– Can be disabled by setting the STOP bit

InterruptInstructions

Interrupt Instructions

• CLI– Clear Interrupt Mask – Clears I bit to 0

• SEI – Set Interrupt Mask– Sets I bit to 0

• RTI – Return from Interrupt

• SWI – Software Interrupt

• WAI – Wait for Interrupt

End of Section

TPS Quiz

Example 4-43• Let A=$FF and ($1000) = $00• A = -1 (signed), A=255 (unsigned)• Given Code Fragment:

– CMPA $1000– $FF - $00 = $FF+$00 = $FF– Condition Code Register

• N = 1• Z = 0• V = 0• C = 0

Example 4-43: Solution• We have: A=$FF, Mem=$00 (CMPA Mem)

• CCR: N=1, Z=0, V=0, C=0• Mnemonic:Condition checked|Our example| Yes or No

• BEQ: Z = 1| Z = 0 | No• BNE: Z = 0| Z = 0 | Yes

Example 4-43: SolutionUnsigned Branches

• We have: A=$FF, Mem=$00 (CMPA MEM)

• CCR: N=1, Z=0, V=0, C=0• Condition | Example | Yes or No• BHS: C =0| C=0| Yes• BLS: C OR Z = 1| 0 or 0 = 0| No• BHI: C OR Z = 0 | 0 or 0 = 0| Yes• BLO: C = 1| C=0| No

Example 4-43: SolutionSigned Branches

• We have: A=$FF, Mem=$00 (CMPA Mem)

• CCR: N=1, Z=0, V=0, C=0• Branch : Condition | Example | Yes or No• BGE: (N XOR Z) = 0 | (1 XOR 0) = 1 | No• BLE: Z OR (N XOR Z) = 1| (0 OR (1 XOR 0)) =1|Yes• BGT: Z OR (N XOR Z) = 0| (0 OR ( 1 XOR 0)) =1| No• BLT: (N XOR Z) = 1 | (1 XOR 0) = 1 | YES