basic logic gates - oakland universitypolis/lectures/eg… · ppt file · web view ·...
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Basic Logic Gates
Discussion D5.1Section 8.6.2
Sections 13-3, 13-4
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Basic Logic Gates and Basic Digital Design
• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
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NOT Gate -- Inverter
X Y
01
10
X Y
Y
NOTX Y
Y = ~X
NOT
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• Y = ~X (Verilog)• Y = !X (ABEL)• Y = not X (VHDL)• Y = X’• Y = X• Y = X (textook)• not(Y,X) (Verilog)
NOT
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NOT
X ~X ~~X = X
X ~X ~~X0 1 01 0 1
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AND GateAND
X
Y
Z
Z = X & Y
X Y Z0 0 00 1 01 0 01 1 1
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• X & Y (Verilog and ABEL)• X and Y (VHDL)• X Y• X Y• X * Y• XY (textbook)• and(Z,X,Y) (Verilog)
AND
U
V
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OR GateOR
X
YZ
Z = X | Y
X Y Z0 0 00 1 11 0 11 1 1
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OR
• X | Y (Verilog)• X # Y (ABEL)• X or Y (VHDL)• X + Y (textbook)• X V Y• X U Y• or(Z,X,Y) (Verilog)
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Basic Logic Gates and Basic Digital Design
• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
![Page 11: Basic Logic Gates - Oakland Universitypolis/Lectures/EG… · PPT file · Web view · 2006-05-16Basic Logic Gates Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4 Basic Logic Gates](https://reader034.vdocuments.mx/reader034/viewer/2022052319/5afd41867f8b9a944d8d2c15/html5/thumbnails/11.jpg)
NAND GateNAND
X
Y
Z
X Y Z0 0 10 1 11 0 11 1 0
Z = ~(X & Y)nand(Z,X,Y)
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NAND GateNOT-AND
X
Y
Z
W = X & Y
Z = ~W = ~(X & Y)
X Y W Z0 0 0 10 1 0 11 0 0 11 1 1 0
W
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NOR GateNOR
X
YZ
X Y Z0 0 10 1 01 0 01 1 0
Z = ~(X | Y)nor(Z,X,Y)
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NOR GateNOT-OR
X
Y
W = X | Y
Z = ~W = ~(X | Y)
X Y W Z0 0 0 10 1 1 01 0 1 01 1 1 0
ZW
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Basic Logic Gates and Basic Digital Design
• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
![Page 16: Basic Logic Gates - Oakland Universitypolis/Lectures/EG… · PPT file · Web view · 2006-05-16Basic Logic Gates Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4 Basic Logic Gates](https://reader034.vdocuments.mx/reader034/viewer/2022052319/5afd41867f8b9a944d8d2c15/html5/thumbnails/16.jpg)
NAND GateX
Y
X
Y
Z Z
Z = ~(X & Y) Z = ~X | ~Y
=
X Y W Z0 0 0 10 1 0 11 0 0 11 1 1 0
X Y ~X ~Y Z0 0 1 1 10 1 1 0 11 0 0 1 11 1 0 0 0
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De Morgan’s Theorem-1
~(X & Y) = ~X | ~Y
• NOT all variables• Change & to | and | to &• NOT the result
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NOR GateX
YZ
Z = ~(X | Y)
X Y Z0 0 10 1 01 0 01 1 0
X
YZ
Z = ~X & ~Y
X Y ~X ~Y Z0 0 1 1 10 1 1 0 01 0 0 1 01 1 0 0 0
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De Morgan’s Theorem-2
~(X | Y) = ~X & ~Y
• NOT all variables• Change & to | and | to &• NOT the result
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De Morgan’s Theorem• NOT all variables• Change & to | and | to &• NOT the result• --------------------------------------------• ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y)• ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y• ~X & !Y = ~(~~X | ~~Y) = ~(X | Y)• ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y
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Basic Logic Gates and Basic Digital Design
• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
![Page 22: Basic Logic Gates - Oakland Universitypolis/Lectures/EG… · PPT file · Web view · 2006-05-16Basic Logic Gates Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4 Basic Logic Gates](https://reader034.vdocuments.mx/reader034/viewer/2022052319/5afd41867f8b9a944d8d2c15/html5/thumbnails/22.jpg)
Exclusive-OR Gate
X Y ZXOR
XY
Z 0 0 00 1 11 0 11 1 0
Z = X ^ Yxor(Z,X,Y)
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XOR
• X ^ Y (Verilog)• X $ Y (ABEL)• X @ Y
• xor(Z,X,Y) (Verilog) X Y (textbook)
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Exclusive-NOR Gate
X Y ZXNOR
XY
Z 0 0 10 1 01 0 01 1 1
Z = ~(X ^ Y)Z = X ~^ Yxnor(Z,X,Y)
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XNOR
• X ~^ Y (Verilog)• !(X $ Y) (ABEL)• X @ Y
• xnor(Z,X,Y) (Verilog) X Y
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Basic Logic Gates and Basic Digital Design
• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
![Page 27: Basic Logic Gates - Oakland Universitypolis/Lectures/EG… · PPT file · Web view · 2006-05-16Basic Logic Gates Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4 Basic Logic Gates](https://reader034.vdocuments.mx/reader034/viewer/2022052319/5afd41867f8b9a944d8d2c15/html5/thumbnails/27.jpg)
Multiple-input Gates
Z 1 2
3 4 Z Z
Z
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Multiple-input AND Gate
Z 1
Output is HIGH only if all inputs are HIGHZ 1
An open input will float HIGH
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Multiple-input OR Gate
Output is LOW only if all inputs are LOWZ 2
2 Z
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Multiple-input NAND Gate
Output is LOW only if all inputs are HIGHZ 3
3 Z
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Multiple-input NOR Gate
Output is HIGH only if all inputs are LOWZ 4
4 Z