basic adc design - 東京工業大学 · 2010. 4. 2. · 5 b 6 msb lsb v fs v 0 binary search v in...

2009/10/19 A. Matsuzawa,Titech 1

Basic ADC design

A. Matsuzawa


ADC architectures and performance


ADC performance and conversion architecture

4 6 8 10 12 14 16

10M

1M

100k

10k

100M

1G

10G

184 6 8 10 12 14 16

10M

1M

100k

10k

100M

1G

10G

18

Con

vers

ion

freq

. (H

z)

Resolution (bit)

Flash

Pipeline

ΔΣSAR

Sub-ranging


SAR ADC


SAR ADC

b1 b2 b3 b4 b5 b6

MSB LSBVFS

V0

Binary search

Vin

VDACVin

VFS21

VFS21 VFS4

1+

VFS21 VFS8

1+

VFS21 VFS8

1+ VFS161+

b1=1b1=1b2=0

b1= b3= 1b2=0

b1= b3= b4= 1b2=0

S/HVin Successive-approximation register and control logic

b1 b2 b3 Bout

DAC Vref

VDAC

Comparator

CMPin

SAR ADC uses binary search method.

・Low power・No Op Amp・multi cycles


Question

S11 S12 S13 S14 S15 S16 S17

S2

S02C

4C

8C

16C

32C

64C

64C

Vin

Vref

Comparator

Cp

Cp is a parasitic cap.

Obtain the charge Q stored on the node x

Node x Q


Answer

S11 S12 S13 S14 S15 S16 S17

S2

S02C

4C

8C

16C

32C

64C

64C

Vin

Vref

Cp

inin CVCCCVQ

64.......

42

Q


Question

S11 S12 S13 S14 S15 S16 S17

S2

S02C

4C

8C

16C

32C

64C

64C

Vin

Vref

Vx

Cp

Obtain the voltage x and proof the MSB conversion is possible.

Comparator


Answer

CC

VVV

p

refin

x

1

21

S11 S12 S13 S14 S15 S16 S17

S2

S02C

4C

8C

16C

32C

64C

64C

Vin

Vref

Vx

Cp

inxprefx CVVCCVVC

22


SAR ADC

Vin

Vref

Comparator Logics

Switches

Capacitor

bcT

bcc

c TNf

T 21

digcmpsetbc TTTT timedelayLogicT

timedecisionComparatorTtimesettlingSwitchT

timecycleBitT

dig

cmp

set

bc

:

:::

bcd ENfP 2

convEnergyEb /:

Low power but needs multi-conversion steps.This limits high speed operation.


FoM of SAR ADC

FoM

0.1

1

10

100

1000

2005 2006 2007 2008 2009 2010Year

FoM

[fJ/c

onv.

step

]

SAR ADC Power vs Sampling Freq.

0.001

0.01

0.1

1

10

100

1000

10000

0.1 1 10 100 1000 10000 100000

Sampling Freq.[MSps]

Pow

er[m

W] 14bit

12bit10-9bit7-5bit

ISSCC2008

Courtesy Y. Kuramochi

1/200

SAR ADC has reduced the FoM down to 1/200 in three years

ENOBc

d

fPFoM2


World lowest FoM SAR ADC

2beq

2b

eqdiss VC2n

1nVC

21nE

+ + +

Multi-step charging

Multi-step charging can reduce energy more

Simple SA architecture

M. van Elzakker, Ed van Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, “A 1.9uW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” IEEE ISSCC 2008, Dig. of Tech. Papers, pp.244-245, Feb. 2008.


Measured performance

FOM

(fJ

/ con

vers

ion-

step

)

ISSCC 2007 ISSCC 2008

1

10

100

1000

This workFO

M (f

J/ c

onve

rsio

n-st

ep)

ISSCC 2007 ISSCC 2008

1

10

100

1000

This work

4.42Figure Of Merit(fJ / conversion-step)

1.9Econversion (pJ/conversion)8.75ENOB (bit)54.4SNDR (dB)2.24INL (LSB)0.49DNL (LSB)-61.1THD (dB)55.6SNR (dB)

Average

4.42Figure Of Merit(fJ / conversion-step)

1.9Econversion (pJ/conversion)8.75ENOB (bit)54.4SNDR (dB)2.24INL (LSB)0.49DNL (LSB)-61.1THD (dB)55.6SNR (dB)

Average

Attained amazing low FoM of 4.4fJ/conv-step.

Conventional FoM

1.9uW, 10bit, 1MSps @ 90nm CMOS


Issue of comparator

5b Charge Redistribution (CR) SAR ADC

INp SAR0/1Vin

CLK

Vref

Vref

INn

113 3

Noise Distribution

Comparator Threshold

b0 b4b3b2b1

1 11 0 1

INp

INn

OK!

27

b0 b4b3b2b1

1 01 1 0

INp

INn

ERROR!

28

Comparator has noise and causes conversion error

V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. van der Plas, and J. Craninckx, “An 820uW 9b 40MS/s Noise Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” IEEE ISSCC 2008, Dig. of Tech. Papers, pp.238-239, Feb. 2008.


ENOB vs. noise

0 0.05 0.1 0.15 0.2 0.258

8.25

8.5

8.75

9

/LSBEN

OB

/LSB=0.24ENOB=8.09

V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. van der Plas, and J. Craninckx, “An 820uW 9b 40MS/s Noise Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” IEEE ISSCC 2008, Dig. of Tech. Papers, pp.238-239, Feb. 2008.

-1 -0.5 0 0.5 10

0.5

1

Vd/LSB

Bin

ary

Out

put

-1 -0.5 0 0.5 10

0.5

1

Vd/LSB

Bin

ary

Out

put

Ideal1=LSB/3

-1 -0.5 0 0.5 10

0.5

1

Vd/LSB

Bin

ary

Out

put

Ideal1

=LSB/3

2>1

radebitLSBradebitLSB

V

V

deg5.0:15.0deg1:25.0

Low noise comparator is required


Increase of resolution

S11 S12 S13 S14 S15 S16 S17

S2

S02C

4C

8C

16C

32C

64C

64C

Vin

Vref

Vref/2

Issue of SAR ADC: large capacitance ratio: 2N-1

Resistor ladder is sometimes used

CVQ Voltage ratio can be used


Increase of resolution

S21S22S23S24S25S26

S3

比較器

-

+

比較出力

Vin: 入力電圧

Vref: 参照電圧S1

S4 2C

4C

8C

2C

4C

8C

8C

Cs

Use of serial capacitance

Question: obtain Cs


Use of serial capacitance

2C

S11S12S13S14S15S16S17

S2

S0a

Vin

Vref

S0b4C

8C

2C

4C

8C

8C

7811 CCCCC s

s

7C

The serial capacitor reduces capacitor ratio,However causes linearity error, due to parasitic capacitance.


Pipeline ADC


Basic construction

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1

1stage

-1

-0.75

-0.5

-0.25

0

0.25

0.5

0.75

1

-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1

2stage

1st out 2nd out

-

-+

+

Op amp

CMPDAC

-

-+

+

Op amp

CMPDAC

-

-+

+

Op amp

Sample & Hold 1st stage 2nd stage

Cf

Cs

Cf

Cs

SamplingCompareSelect DAC voltageAmplifier (conventionally 2x)


Two modes

CMPDAC

-

-+

+

Op amp

Cf

Cs

Sample Amplify (Hold)

2V

,0,2V

V2V refrefinout

Vin

Vout

Vin

Vout

VDAC (+Vref, 0, -Vref)


1bit folding

-Vref

+Vref

-Vref

+Vref -Vref

+Vref

-Vref

+Vref

１st stage 2nd stage

0 1 0 1 0 1

Ｘ２Ｘ２Input

Out

put

Input

Out

put

Comp. out

VDAC=-Vref VDAC=+Vref

Comp. out


Non ideal signal due to offset voltage

-Vref

+Vref

-VrefＸ２

Offset by comp.

-Vref

+Vref

-Vref

+Vref

Ｘ２

+Vref

Offset by OpAmp.

Over rangeOver range

Over rangeOver range


Conversion characteristics

-Vref

+Vref

Ｘ２

+Vref -Vref+Vref

A/D conversion characteristics

Input

Out

put

Return to normal

Output value is clamped


1.5b redundant architecture

-Vref +Vref

+Vref

-Vref

Vsig

Vout

+Vref/4-Vref/4

00 01 10

A

B

A

B

Comp. offset

Folding signal within normal conversion area

OpAmp. offset

1.5bit redundant architecture can solve offset issues.


Analog value and digital value for each stage

-Vref

+Vref

-Vref

+Vref

１ビット目

0 1

Ｘ２

入力信号

出力

信号

比較器出力

-Vref +Vref

+Vref

-Vref

Vsig

Vout

+Vref/4-Vref/4

00 01 10

A

B

021

21,1]1[:

021

21,1]0[:

Anaref

Dig

ref

Anaref

Dig

ref

VV

MSBB

VV

MSBA

A

B

refAna

ref

Dig

ref

refAna

ref

Dig

ref

refAna

ref

Dig

ref

refAna

ref

Dig

ref

VVV

D

VVV

C

VVV

B

VVV

A

41

221

211]0,1[:

41

221

200]1,0[:

41

221

20,0]1,0[:

41

221

21,1]0,0[:

-1 +1-1 +10

C

D

Sum of analog value and digital value shows the input voltage.


Total pipeline configuration

LSB

stage1 stage2 stage3 stage4 stage5Vin

MSB 1.5bit 1.5bit 1.5bit 1.5bit 2bit

Q50Q51Q30Q31Q20Q21Q10Q11

D-FFD-FFD-FFD-FFD-FF

Q40Q41

D-FFD-FF

D-FF

D-FF

D-FF

D-FF

D-FF

D-FF

D-FF

D-FF

HAFAFAFA

Q0Q1Q2Q3Q4Q5

HAS1C1S2C2S3C3S4C4S5


Effect of gain error

-Vref +Vref

+Vref

-Vref

Vsig

Vout

-Vref

Conversion error

Solid line: ideal 2xDashed line: LT 2x

IO chara. Of each stage

ADC linearity


Cf=1pFCs=1pF

Ideal conversion


Larger than 2x


Less than 2x

basic adc design - 東京工業大学 · 2010. 4. 2. · 5 b 6 msb lsb v fs v 0 binary search v in...

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