based on slides from d. patterson and cs152

Modified by S. J. Fritz Spring 2009 (1)

Based on slides from D. Patterson and

www-inst.eecs.berkeley.edu/~cs152/

COM 249 – Computer Organization andAssembly Language

Chapter 4 The Processor


Introduction

• Chapter 1 explained CPU performance factors– Instruction count

• Determined by ISA and compiler

– CPI and Cycle time• Determined by CPU hardware

• Chapter 2 explained that the compiler and the instruction set architecture determine the instruction count for a program.

• But - the implementation of the processor determines both the clock cycle time and the number of clock cycles per instruction.

§4.1 Introduction


Introduction

• In this chapter we will construct the data path and the control unit for 2 different instruction set implementations

• We will examine two MIPS implementations– A simplified version– A more realistic pipelined version

• Simple subset, shows most aspects– Memory reference: lw, sw– Arithmetic/logical: add, sub, and, or, slt– Control transfer: beq, j

§4.1 Introduction


Instruction Classes

• In keeping with the principles of simplicity and making the common case fast, the actions are mostly the same for each of these classes of instructions:

• Memory-reference• Arithmetic-logical• Branches• All classes except jump use the ALU after

reading registers• After using the ALU, the actions differ


Memory Reference

• Memory-reference instructions use the ALU for an address calculation

• It will need to access memory either to read data (load) or write data ( store).

• Arithmetic-logical instructions use the ALU for operation execution

• It must write the data from the ALU back into the a register

• For a branch instruction, we may need to change the next instruction address based on the comparison; otherwise the PC is incremented by 4 to get the next instruction.


Instruction Execution

• Send the PC to the memory that contains the code and fetch the instruction – PC instruction memory, fetch instruction

• Read one or two registers– Register numbers register file, read registers

• Depending on instruction class– Use ALU to calculate

• Arithmetic result• Memory address for load/store• Branch target address

– Access data memory for load/store– PC target address or PC + 4


CPU Overview• High-level view focuses on the functional

units and their interconnection.• Omits two important aspects of instruction

execution:– It shows data coming form two separate

sources, where in actuality it requires a logic element to choose; this is a multiplexor or a data selector (See Appendix C)

– Several units must be controlled depending on the type of instruction ( e.g. data memory must read on a load and write on a store instruction)


CPU Overview

buses


CPU Overview

1. PC sends instruction address to instruction memory

2. Instruction is fetched

3. Registers for the instruction are specified by fields in the instruction

4. Register operands are fetched

5. Operands used to compute an address or an arithmetic result or a compare in the ALU

6. Result of ALU is written to a register or memory (depending on the type of instruction)


Multiplexors

• Can’t just join wires together– Use multiplexers


Control Unit

• A control unit, which has the instruction as an input, is used to determine how to set the control lines for the functional units and for two multiplexors.

• The third multiplexor, which determines whether the PC +4 or the branch destination address is written into the PC, is set based on the Zero output of the ALU, which is used to perform the comparison of a beq instruction

• This simple decoding can be used to set all control lines.


Control


Logic Design Basics

§4.2 Logic Design C

onventions

• Information encoded in binary– Low voltage = 0, High voltage = 1– One wire per bit– Multi-bit data encoded on multi-wire buses

• MIPS data path consists of 2 types of logic elements:– Combinational element

• Operate on data• Output is a function of input ( given the same input

always produces the same output)

– State (sequential) elements• Store information ( e.g. memory and registers)


Combinational Elements

• AND-gateY = A & BAB

Y

I0I1

YMux

S

• MultiplexerY = S ? I1 : I0

A

B

Y+

A

B

YALU

F

• AdderY = A + B

• Arithmetic/Logic UnitY = F(A, B)


Sequential (State) Elements• A state element has at least two inputs and one

output:– Inputs: the data value to be written and the clock, which

determines when the value will be written– Output: provides the value that was written in an earlier

clock cycle• Example: D-type flip-flop, which has value and clock inputs

and one output

• State elements can be read at any time.• Called sequential because their output depend on

both their inputs and the contents of their internal state

• (See Appendix C)


Signal Values

• Asserted – a signal that is logically high or true or 1

• Assert specifies that a signal should be driven logically high

• Deassert or deasserted represents a signal that is logically low or false or 0


Clocking Methodology

• Defines when a signal can be read and when it can be written, or when it is relatively stable with respect to the clock

• Designed to ensure predictability• Edge-triggered clocking – all state changes

occur on a clock edge.– Allow us to read the contents of a register, send the

value through some combinatorial logic and write the register in the same clock cycle

• There is no feedback within a single clock cycle.


Sequential Elements

• Register: stores data in a circuit– Uses a clock signal to determine when to

update the stored value– Edge-triggered: update when Clk changes

from 0 to 1

D

Clk

QClk

D

Q


Sequential Elements

• Register with write control– Only updates on clock edge when write

control input is 1– Used when stored value is required later

D

Clk

Q

Write

Write

D

Q

Clk


Clocking Methodology

• Combinational logic transforms data during clock cycles

• All signals propagate from state element 1to state element 2 in a single clock cycle– Between clock edges– Input from state elements, output to state element– Longest delay determines clock period


Building a Datapath

• Datapath– Elements that process data and addresses

in the CPU• Registers, ALUs, mux’s, memories, …

• We will build a MIPS datapath incrementally– Refining the overview design

§4.3 Building a D

atapath


Datapath Elements

• Memory unit – to store the instructions of a programand supply instructions when given an address

• Program counter (PC)- register that holds the address of the current instruction

• Adder- to increment the PC to the address of the next instruction– Combinatorial– Built from the ALU by wiring the control lines to

specify an add operation


Instruction Fetch

32-bit register

Increment by 4 for next instruction

1. Fetch instruction from memory

2. Increment the PC so that it point to the next instruction, 4 bytes later


R- Format Instructions

• R-type or arithmetic-logic instructions:– Read two registers– Perform an ALU operation on register contents– Write the result to a register

• Includes add, sub,AND, OR and slt• The 32 general registers make up a register file,

where any register can be read/written by specifying the number of the register.

• R- format instructions will read two words and write one into the registers for each instruction.


R-Format Instructions

• For each data word to be read:– Input to the register file to specify the number of

the register to be read– An output form the register file that carries the

value read from the registers

• To write to the registers, need two inputs:– To specify the register number to be written– To supply the data to be written to the register

• Register number inputs are 5 bits wide to specify one of the 32 registers (25 = 32)


R-Format Instructions• Read two register operands• Perform arithmetic/logical operation• Write register result


Zero Signal

• If the zero signal out of the ALU is asserted (1), the two input values are equal.

• It is used to test for equality

A

B

Zero

4ALU operation


Load/Store Instructions

• Load/Store Instructions computer a memory address by adding the base register to the offset field in the instruction.

• To load, the value read from memory is written to the register

• To store, the value must be read from the register file

• For these instructions, we will need the register file and the ALU as well as a unit to sign-extend the 16 bit offset field in the instruction to a 32-bit signed value and a data memory unit to read/write to it.


Load/Store Instructions

• Read register operands• Calculate address using 16-bit offset

– Use ALU, but sign-extend offset

• Load: Read memory and update register• Store: Write register value to memory


Branch Instructions

• The branch instruction has 3 operands:– two registers that are compared for equality,– and a 16 bit offset used to compute the branch target

address.

• Its form is beq $t1,$t2, offset• To compute the branch target address, add the

sign extend offset field of the instruction to the PC + 4 (and shift two bits so that it is a word offset).

• If the branch is not taken ( when the operands are not equal) the incremented PC should replace the current PC value ( just as for other instructions)


Branch Instructions

• Read register operands

• Compare operands– Use ALU, subtract and check Zero output

• Calculate target address– Sign-extend displacement– Shift left 2 places (word displacement)– Add to PC + 4

• Already calculated by instruction fetch


Branch Instructions

Justre-routes

wires

Sign-bit wire replicated


Composing the Elements

• First-cut data path does an instruction in one clock cycle– Each datapath element can only do one

function at a time– Hence, we need separate instruction and

data memories

• Use multiplexors where alternate data sources are used for different instructions


Creating a Single Datapath

• We combine the individual components into a single datapath and add the control signals.

• The simplest datapath attempts to execute all instructions in one clock cycle.

• To do this, no resource can be used more than once per instruction, so any element needed more than once must be duplicated.

• Therefore we need a separate memory for instructions and another for data.

• To share between different instruction classes, we allow multiple connections to the input of an element, using a multiplexor and a control signal to select among the multiple inputs.


Building a Datapath

•The operations of arithmetic-logical (R-Type) instructions and memory instructions datapath are quite similar.

•The differences are:

•The arithmetic-logical instructions use the ALU with inputs from 2 registers

•The memory instructions use the ALU to compute the address and the second input is the sign extend 16 bit offset field.

• The value stored in the destination register comes from the ALU for an R-type instruction or the memory ( for a load instruction).


R-Type/Load/Store Datapath


Simplest Full Datapath

• This simple datapath combines all the elements required by simple MIPS instructions and can execute these instructions (load, Store, ALU ops, and branch) in a single cycle).

• The control unit is added to take inputs and generate a write signal for each state element, the selector control for each MUX, and the ALU control.


Full Datapath

Fig. 4.11


ALU Control• ALU used for

– Load/Store: F = add (to compute address)– Branch: F = subtract– R-type: F depends on funct field

• The ALU (appendix c) defines 6 combinations of 4 inputs:

§4.4 A S

imple Im

plementation S

cheme

ALU control lines Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 set-on-less-than

1100 NOR


ALU Control

• Assume 2-bit ALUOp derived from opcode– Combinational logic derives ALU control– Don’t cares are xxxxxx

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010

sw 00 store word XXXXXX add 0010

beq 01 branch equal XXXXXX subtract 0110

R-type 10 add 100000 add 0010

subtract 100010 subtract 0110

AND 100100 AND 0000

OR 100101 OR 0001

set-on-less-than 101010 set-on-less-than 0111


The Main Control Unit

• Control signals derived from instruction0 rs rt rd shamt funct

31:26 5:025:21 20:16 15:11 10:6

35 or 43 rs rt address

31:26 25:21 20:16 15:0

4 rs rt address

31:26 25:21 20:16 15:0

R-type

Load/Store

Branch

opcode always read

read, except for load

write for R-type

and load

sign-extend and add


Datapath With Control

Fig. 4.17


Datapath With Control• The input to the control unit is the 6 bit opcode field

from the instruction.• The outputs of the control unit are

– 3 1 bit signals that control the MUXs (RegDst, ALU SRc,and MemToReg)

– 3 signals for controlling the reads and writes in the register file and data memory (RegWrite, MemRead, MemWrite)

– 1 bit signal to determine when to branch (Branch)– 2 bit Control signal for the ALU (ALUOp)

• An AND gate combines the branch control signal and the Zero output from the ALU


R-Type Instruction

Fig. 4.19


Components Involved In Executing An R-Type Instruction


Execution Stepsfor an R-Type Instruction

• Four steps:1. Fetch the instruction, add 4 to the PC value.2. Send the operand register contents to the

main ALU.3. Perform the main ALU operation.4. On the rise of the clock:

• ALU result is stored in register file, and• Incremented PC value (from Step 1) is stored in

the PC.• Change in the PC’s value initiates the next

instruction fetch.


Control Signalsfor an R-Type Instruction

• Control signals are generated:– By control circuits (to be added to data path

diagram) – From opcode/function bits of instructions.

• Signal values for correct execution of R-Type instructions:– RegDst = 1– RegWrite = Asserted– ALUSrc = 0– MemWrite = Deasserted– MemtoReg = 1– PCSrc = 0


Load Instruction

Fig. 4.20


Relevant Signal Propagation Involved In Executing A lw Instruction

write


Relevant Signal Propagation Involved In Executing A sw Instruction

write


Execution Stepsfor lw and sw Instructions

• Five steps:1. Fetch the instruction, add 4 to the PC value.

2. Send the:• Register 2 contents and Sign Extended address to the ALU.• Register 1 contents to Write Data of (data) memory.

3. Perform ALU add to compute the address of data.

4. Fetch data from memory for a lw instruction.

5. Store• Fetched data in the register file for an lw instruction, or• Register 1’s data in data memory for a sw instruction.• Incremented PC value (from Step 1) in the PC register.

Data path activity: lw and sw instructions


Components Involve In Executing A beq Instruction


Executing the Branch on Equal (beq) Instruction

• Four steps:1.Fetch the instruction; add 4 to the PC value.

2.Send the operand registers’ contents to the ALU.

3.Perform ALU subtract operation and add the offset to the incremented PC value.

4. If the ALU subtract result is 0, send the PC:• Incremented PC value + Offset (PCSrc = 1).• Otherwise, send the incremented PC value (PCSrc = 0).


Branch-on-Equal Instruction


Components Involved In Executing A j (Jump) Instruction


Implementing Jumps

• Jump uses word address• Update PC with concatenation of

– Top 4 bits of old PC– 26-bit jump address– 00

• Need an extra control signal decoded from opcode

2 address

31:26 25:0

Jump


Executing the Jump Instruction

• Three steps:1.Fetch the instruction. from the instruction

memory.

2.Generate the 32-bit jump (byte) address.

3.Store the 32-bit jump (byte) address in the PC register.


Datapath With Jumps Added

Fig. 4.24


Why Single Cycle is Not Used

• Single cycle works correctly, but is not efficient enough to be used today

• Clock cycle must have the same length for every instruction.

• Clock cycle is determined by the longest possible path in the instruction, usually a load instruction, which uses 5 functional units in series (instruction memory,register file, the ALU, the data memory, and the register file)


Steps for Different Instructions

Instruction Number of steps

R- format 4

Load / store (lw, sw) 5

Branch on equal ( beq) 4

Jump 3

Single cycle execution would have to be 5 stages long to accommodate the longest instruction


Performance Issues

• Longest delay determines clock period– Critical path: load instruction ( 5 steps)– Instruction memory register file ALU data

memory register file

• Not feasible to vary period for different instructions

• Violates design principle– Making the common case fast

• We will improve performance by pipelining


Review Datapath

• Five stages of datapath,executing an instruction, one step per stage

1. IF: Instruction fetch from memory

2. ID: Instruction decode & register read

3. EX: Execute operation or calculate address

4. MEM: Access memory operand

5. WB: Write result back to register

• ALL instructions must go through ALL five stages.


Review DatapathP

C

inst

ruct

ion

me

mor

y

+4

rtrs

rd

regi

ste

rs

ALU

Da

tam

em

ory

imm

1. InstructionFetch

2. Decode/ Register

Read

3. Execute 4. Memory5. Write

Back


Gotta Do Laundry

° Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and put away

A B C D

° Dryer takes 30 minutes

° “Folder” takes 30 minutes

° “Stasher” takes 30 minutes to put clothes into drawers

° Washer takes 30 minutes


Sequential Laundry

• Sequential laundry takes 8 hours for 4 loads

Task

Order

B

C

D

A

30Time

3030 3030 30 3030 3030 3030 3030 3030

6 PM 7 8 9 10 11 12 1 2 AM


Pipelined Laundry

• Pipelined laundry takes 3.5 hours for 4 loads!

Task

Order

B

C

D

A

12 2 AM6 PM 7 8 9 10 11 1

Time303030 3030 3030


General Definitions

• Latency: time to completely execute a certain task– for example, time to read a sector from disk is disk

access time or disk latency

• Throughput: amount of work that can be done over a period of time


Pipelining Lessons

• Pipelining doesn’t help latency of single task, it helps throughput of entire workload

• Multiple tasks operating simultaneously using different resources

• Potential speedup = Number pipe stages

• Time to “fill” pipeline and time to “drain” it reduces speedup:2.3X v. 4X in this example

6 PM 7 8 9

Time

B

C

D

A

303030 3030 3030Task

Order


Pipelining Lessons

• Suppose new Washer takes 20 minutes, new Stasher takes 20 minutes. How much faster is pipeline?

• Pipeline rate limited by slowest pipeline stage

• Unbalanced lengths of pipe stages also reduces speedup

6 PM 7 8 9

Time

B

C

D

A

303030 3030 3030Task

Order


Steps in Executing MIPS Revisited

1) IFetch: Fetch Instruction, Increment PC2) Decode Instruction, Read Registers3) Execute: Mem-ref: Calculate Address Arith-log: Perform Operation

4) Memory: Load: Read Data from Memory Store: Write Data to Memory

5) Write Back: Write Data to Register


Pipelined Execution Representation

• Every instruction must take same number of steps, also called pipeline “stages”, so some will go idle sometimes

IFtch Dcd Exec Mem WB






Time


Review: Datapath for MIPS

• Use datapath figure to represent pipelineIFtch Dcd Exec Mem WB

AL

U I$ Reg D$ Reg

PC

inst

ruct

ion

me

mor

y+4

rtrs

rd

regi

ste

rs

ALU

Da

tam

em

ory

imm

1. InstructionFetch

2. Decode/ Register Read

3. Execute 4. Memory5. Write

Back


Graphical Pipeline Representation

Instr.

Order

Load

Add

Store

Sub

Or

I$

Time (clock cycles)

I$

AL

U

Reg

Reg

I$

D$

AL

U

AL

U

Reg

D$

Reg

I$

D$

RegA

LU

Reg Reg

Reg

D$

Reg

D$

AL

U

(In Reg, right half highlight read, left half write)

Reg

I$


Example

• Suppose 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write; compute instr rate:

• Nonpipelined Execution:–lw : IF + Read Reg + ALU + Memory + Write Reg = 2 + 1 + 2 + 2 + 1 = 8 ns

–add: IF + Read Reg + ALU + Write Reg = 2 + 1 + 2 + 1 = 6 ns

• Pipelined Execution:–Max(IF,Read Reg,ALU,Memory,Write Reg) = 2 ns


Pipeline Hazard: Matching socks in later load

A depends on D; stall since folder tied up

Task

Order

B

C

D

A

E

F

bubble

12 2 AM6 PM 7 8 9 10 11 1

Time303030 3030 3030


Problems for Computers

• Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle– Structural hazards: HW cannot support this

combination of instructions (single person to fold and put clothes away)

– Control hazards: Pipelining of branches & other instructions stall the pipeline until the hazard; “bubbles” in the pipeline

– Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)


Structural Hazard #1: Single Memory

Read same memory twice in same clock cycle

I$

Load

Instr 1

Instr 2

Instr 3

Instr 4A

LU I$ Reg D$ Reg

AL

U I$ Reg D$ Reg

AL

U I$ Reg D$ RegA

LUReg D$ Reg

AL

U I$ Reg D$ Reg

Instr.

Order

Time (clock cycles)


Structural Hazard #1: Single Memory

• Solution:– infeasible and inefficient to create second

memory– (We’ll learn more about this)– so simulate this by having two Level 1

Caches (a temporary smaller [usually most recently used] copy of memory)

– have both an L1 Instruction Cache and an L1 Data Cache

– need more complex hardware to control when both caches miss


Structural Hazard #2: Registers

Can’t read and write to registers simultaneously

I$

sw

Instr 1

Instr 2

Instr 3

Instr 4A

LU I$ Reg D$ Reg

AL

U I$ Reg D$ Reg

AL

U I$ Reg D$ RegA

LUReg D$ Reg

AL

U I$ Reg D$ Reg

Instr.

Order

Time (clock cycles)


Structural Hazard #2: Registers

• Fact: Register access is VERY fast: takes less than half the time of ALU stage

• Solution: introduce convention– always Write to Registers during first half of

each clock cycle– always Read from Registers during second

half of each clock cycle– Result: can perform Read and Write during

same clock cycle


Peer Instruction – Discuss this for a minute

A. Thanks to pipelining, I have reduced the time it took me to wash my shirt.

B. Longer pipelines are always a win (since less work per stage & a faster clock).

C. We can rely on compilers to help us avoid data hazards by reordering instructions.

ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT


Peer Instruction Answer

A. Thanks to pipelining, I have reduced the time it took me to wash my shirt.

B. Longer pipelines are always a win (since less work per stage & a faster clock).

C. We can rely on compilers to help us avoid data hazards by reordering instrs.

ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT

F A L S EF A L S E

A. Throughput better, not execution time

B. “…longer pipelines do usually mean faster clock, but branches cause problems!

C. “they happen too often & delay too long.” Forwarding! (e.g, Mem ALU)

F A L S E


Things to Remember

• Optimal Pipeline– Each stage is executing part of an instruction

each clock cycle.– One instruction finishes during each clock cycle.– On average, execute far more quickly.

• What makes this work?– Similarities between instructions allow us to use

same stages for all instructions (generally).– Each stage takes about the same amount of

time as all others: little wasted time.


Pipelining Analogy• Pipelined laundry: overlapping execution

– Parallelism improves performance

§4.5 An O

verview of P

ipelining

• Four loads:– Non-pipelined 8 hrs– Pipelined: 3.5 hrs

• Speedup= 8/3.5 = 2.3

• Non-stop:• Speedup

= 2n/0.5n + 1.5 ≈ 4= number of stages


Pipeline Performance

• Assume time for stages is– 100ps for register read or write– 200ps for other stages

• Compare pipelined datapath with single-cycle datapath

Instr Instr fetch Register read

ALU op Memory access

Register write

Total time

lw 200ps 100 ps 200ps 200ps 100 ps 800ps

sw 200ps 100 ps 200ps 200ps 700ps

R-format 200ps 100 ps 200ps 100 ps 600ps

beq 200ps 100 ps 200ps 500ps


Pipeline PerformanceSingle-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)


Pipeline Speedup

• If all stages are balanced– i.e., all take the same time

– Time between instructionspipelined

= Time between instructionsnonpipelined

Number of stages

• If not balanced, speedup is less

• Speedup due to increased throughput– Latency (time for each instruction) does not

decrease


Pipelining and ISA Design

• MIPS ISA designed for pipelining– All instructions are 32-bits

• Easier to fetch and decode in one cycle• c.f. x86: 1- to 17-byte instructions

– Few and regular instruction formats• Can decode and read registers in one step

– Load/store addressing• Can calculate address in 3rd stage, access memory in 4th

stage

– Alignment of memory operands• Memory access takes only one cycle


Hazards

• Situations that prevent starting the next instruction in the next cycle:

• Structure hazards– A required resource is busy

• Data hazard– Need to wait for previous instruction to complete

its data read/write

• Control hazard– Deciding on control action depends on previous

instruction


Structure Hazards

• Conflict for use of a resource

• In MIPS pipeline with a single memory– Load/store requires data access– Instruction fetch would have to stall for that

cycle• Would cause a pipeline “bubble”

• Hence, pipelined datapaths require separate instruction/data memories– Or separate instruction/data caches


Data Hazards

• An instruction depends on completion of data access by a previous instruction– add $s0, $t0, $t1sub $t2, $s0, $t3

No-op


Forwarding (aka Bypassing)

• Use result when it is computed– Don’t wait for it to be stored in a register– Requires extra connections in the datapath


Load-Use Data Hazard

• Can’t always avoid stalls by forwarding– If value not computed when needed– Can’t forward backward in time!


Code Scheduling to Avoid Stalls

• Reorder code to avoid use of load result in the next instruction

• C code for A = B + E; C = B + F;lw $t1, 0($t0)lw $t2, 4($t0)add $t3, $t1, $t2sw $t3, 12($t0)lw $t4, 8($t0)add $t5, $t1, $t4sw $t5, 16($t0)

stall

stall

lw $t1, 0($t0)lw $t2, 4($t0)lw $t4, 8($t0)add $t3, $t1, $t2sw $t3, 12($t0)add $t5, $t1, $t4sw $t5, 16($t0)

11 cycles13 cycles


Control Hazards

• Branch determines flow of control– Fetching next instruction depends on

branch outcome– Pipeline can’t always fetch correct

instruction• Still working on ID stage of branch

• In MIPS pipeline– Need to compare registers and compute

target early in the pipeline– Add hardware to do it in ID stage


Stall on Branch

• Wait until branch outcome determined before fetching next instruction


Branch Prediction

• Longer pipelines can’t readily determine branch outcome early– Stall penalty becomes unacceptable

• Predict outcome of branch– Only stall if prediction is wrong

• In MIPS pipeline– Can predict branches not taken– Fetch instruction after branch, with no

delay


MIPS with Predict Not Taken

Prediction correct

Prediction incorrect


More-Realistic Branch Prediction

• Static branch prediction– Based on typical branch behavior– Example: loop and if-statement branches

• Predict backward branches taken• Predict forward branches not taken

• Dynamic branch prediction– Hardware measures actual branch behavior

• e.g., record recent history of each branch

– Assume future behavior will continue the trend• When wrong, stall while re-fetching, and update

history


Pipeline Summary

• Pipelining improves performance by increasing instruction throughput– Executes multiple instructions in parallel– Each instruction has the same latency

• Subject to hazards– Structure, data, control

• Instruction set design affects complexity of pipeline implementation

The BIG Picture


Review: Pipeline

• Optimal Pipeline– Each stage is executing part of an

instruction each clock cycle.– One inst. finishes during each clock cycle.– On average, execute far more quickly.

• What makes this work?– Similarities between instructions allow us to

use same stages for all instructions (generally).

– Each stage takes about the same amount of time as all others: little wasted time.


Review: Pipeline

• Pipelining is a BIG IDEA– widely used concept

• What makes it less than perfect?– Structural hazards: suppose we had only

one cache? Need more HW resources

– Control hazards: need to worry about branch instructions? Delayed branch

– Data hazards: an instruction depends on a previous instruction?


Control Hazard: Branching

Where do we do the compare for the branch?

I$

beq

Instr 1

Instr 2

Instr 3

Instr 4A

LU I$ Reg D$ Reg

AL

U I$ Reg D$ Reg

AL

U I$ Reg D$ RegA

LUReg D$ Reg

AL

U I$ Reg D$ Reg

Instr.

Order

Time (clock cycles)



• We put branch decision-making hardware in ALU stage– therefore two more instructions after the branch

will always be fetched, whether or not the branch is taken

• Desired functionality of a branch– if we do not take the branch, don’t waste any

time and continue executing normally– if we take the branch, don’t execute any

instructions after the branch, just go to the desired label



• Initial Solution: Stall until decision is made– insert “no-op” (bubble) instructions: those that

accomplish nothing, just take time– Drawback: branches take 3 clock cycles each

(assuming comparator is put in ALU stage)



• Optimization #1:– move asynchronous comparator up to

Stage 2– as soon as instruction is decoded (Opcode

identifies is as a branch), immediately make a decision and set the value of the PC (if necessary)

– Benefit: since branch is complete in Stage 2, only one unnecessary instruction is fetched, so only one no-op is needed

– Side Note: This means that branches are idle in Stages 3, 4 and 5.


• Insert a single no-op (bubble)


add

beq

lw

AL

U I$ Reg D$ Reg

AL

U I$ Reg D$ RegA

LUReg D$ Reg I$

Instr.

Order

Time (clock cycles)

bubble

• Impact: 2 clock cycles per branch instruction slow



• Optimization #2: Redefine branches– Old definition: if we take the branch, none of the

instructions after the branch get executed by accident

– New definition: whether or not we take the branch, the single instruction immediately following the branch gets executed (called the branch-delay slot)

• The term “Delayed Branch” meanswe always execute instruction after branch



• Notes on Branch-Delay Slot– Worst-Case Scenario: can always put a no-op

in the branch-delay slot– Better Case: can find an instruction preceding

the branch which can be placed in the branch-delay slot without affecting flow of the program

• re-ordering instructions is a common method of speeding up programs

• compiler must be very smart in order to find instructions to do this

• usually can find such an instruction at least 50% of the time

• Jumps also have a delay slot…


Example: Nondelayed vs. Delayed Branch

add $1 ,$2,$3

sub $4, $5,$6

beq $1, $4, Exit

or $8, $9 ,$10

xor $10, $1,$11

Nondelayed Branch

add $1 ,$2,$3

sub $4, $5,$6

beq $1, $4, Exit

or $8, $9 ,$10

xor $10, $1,$11

Delayed Branch

Exit: Exit:


Data Hazards

add $t0, $t1, $t2

sub $t4, $t0 ,$t3

and $t5, $t0 ,$t6

or $t7, $t0 ,$t8

xor $t9, $t0 ,$t10

• Consider the following sequence of instructions


Dependencies backwards in time are hazards

Data Hazards

sub $t4,$t0,$t3

AL

UI$ Reg D$ Reg

and $t5,$t0,$t6

AL

UI$ Reg D$ Reg

or $t7,$t0,$t8 I$

AL

UReg D$ Reg

xor $t9,$t0,$t10

AL

UI$ Reg D$ Reg

add $t0,$t1,$t2IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg

Instr.

Order

Time (clock cycles)


• Forward result from one stage to another

Data Hazard Solution: Forwarding

sub $t4,$t0,$t3

AL

UI$ Reg D$ Reg

and $t5,$t0,$t6A

LUI$ Reg D$ Reg

or $t7,$t0,$t8 I$

AL

UReg D$ Reg

xor $t9,$t0,$t10

AL

UI$ Reg D$ Reg

add $t0,$t1,$t2IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg

“or” hazard solved by register hardware


• Dependencies backwards in time are hazards

Data Hazard: Loads

sub $t3,$t0,$t2A

LUI$ Reg D$ Reg

lw $t0,0($t1)IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg

• Can’t solve with forwarding• Must stall instruction dependent on load, then forward (more hardware)


• Hardware must stall pipeline• Called “interlock”

Data Hazard: Loads

sub $t3,$t0,$t2

AL

UI$ Reg D$ Regbubble

and $t5,$t0,$t4

AL

UI$ Reg D$ Regbubble

or $t7,$t0,$t6 I$

AL

UReg D$bubble

lw $t0, 0($t1)IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg


Data Hazard: Loads

• Instruction slot after a load is called “load delay slot”

• If that instruction uses the result of the load, then the hardware interlock will stall it for one cycle.

• If the compiler puts an unrelated instruction in that slot, then no stall

• Letting the hardware stall the instruction in the delay slot is equivalent to putting a no-op in the slot (except the latter uses more code space)


Data Hazard: Loads

sub $t3,$t0,$t2

and $t5,$t0,$t4

or $t7,$t0,$t6 I$

AL

UReg D$

lw $t0, 0($t1)

AL

UI$ Reg D$ Reg

bubble

bubble

bubble

bubble

bubble

AL

UI$ Reg D$ Reg

AL

UI$ Reg D$ Reg

nop

•Stall is equivalent to no-op


Historical Trivia

• First MIPS design did not interlock and stall on load-use data hazard

• Real reason for name behind MIPS: Microprocessor without Interlocked Pipeline Stages– Word Play on acronym for

Millions of Instructions Per Second, also called MIPS


Review Pipeline Hazard: Stall is dependency

A depends on D; stall since folder tied up

Task

Order

12 2 AM6 PM 7 8 9 10 11 1

Time

B

C

D

A

E

F

bubble

303030 3030 3030


Out-of-Order Laundry: Don’t Wait

A depends on D; rest continue; need more resources to allow out-of-order

Task

Order

12 2 AM6 PM 7 8 9 10 11 1

Time

B

C

D

A

303030 3030 3030

E

F

bubble


Superscalar Laundry: Parallel per stage

More resources, HW to match mix of parallel tasks?

Task

Order

12 2 AM6 PM 7 8 9 10 11 1

Time

B

C

D

A

E

F

(light clothing) (dark clothing) (very dirty clothing)

(light clothing) (dark clothing) (very dirty clothing)

303030 3030


Superscalar Laundry: Mismatch Mix

Task mix underutilizes extra resources

Task

Order

12 2 AM6 PM 7 8 9 10 11 1

Time303030 3030 3030

(light clothing)

(light clothing) (dark clothing)

(light clothing)

A

B

D

C


Peer Instruction

Assume 1 instr/clock, delayed branch, 5 stage pipeline, forwarding, interlock on unresolved load hazards (after 103 loops, so pipeline full)Loop: lw $t0, 0($s1)

addu $t0, $t0, $s2sw $t0, 0($s1)addiu $s1, $s1, -4bne $s1, $zero, Loopnop

•How many pipeline stages (clock cycles) per loop iteration to execute this code?

12345678910


Peer Instruction Answer• Assume 1 instr/clock, delayed branch, 5 stage

pipeline, forwarding, interlock on unresolved load hazards. 103 iterations, so pipeline full.

Loop:

lw $t0, 0($s1)addu $t0, $t0, $s2sw $t0, 0($s1)addiu $s1, $s1, -4bne $s1, $zero, Loopnop

• How many pipeline stages (clock cycles) per loop iteration to execute this code?

1.2. (data hazard so stall)

3.4.5.6.

(delayed branch so exec. nop)7.

1 2 3 4 5 6 7 8 9 10


“And in Conclusion..”

• Pipeline challenge is hazards–Forwarding helps w/many data hazards–Delayed branch helps with control hazard in 5 stage pipeline

• More aggressive performance: –Superscalar–Out-of-order execution


MIPS Pipelined Datapath

§4.6 Pipelined D

atapath and Control

WB

MEM

Right-to-left flow leads to hazards


Pipeline registers

• Need registers between stages– To hold information produced in previous cycle


Pipeline Operation

• Cycle-by-cycle flow of instructions through the pipelined datapath– “Single-clock-cycle” pipeline diagram

• Shows pipeline usage in a single cycle• Highlight resources used

– c.f. “multi-clock-cycle” diagram• Graph of operation over time

• We’ll look at “single-clock-cycle” diagrams for load & store


IF for Load, Store, …


ID for Load, Store, …


EX for Load


MEM for Load


WB for Load

Wrongregisternumber


Corrected Datapath for Load


EX for Store


MEM for Store


WB for Store


Multi-Cycle Pipeline Diagram

• Form showing resource usage


Multi-Cycle Pipeline Diagram

• Traditional form


Single-Cycle Pipeline Diagram

• State of pipeline in a given cycle


Pipelined Control (Simplified)


Pipelined Control

• Control signals derived from instruction– As in single-cycle implementation


Pipelined Control


Data Hazards in ALU Instructions

• Consider this sequence:sub $2, $1,$3and $12,$2,$5or $13,$6,$2add $14,$2,$2sw $15,100($2)

• We can resolve hazards with forwarding– How do we detect when to forward?

§4.7 Data H

azards: Forw

arding vs. Stalling


Dependencies & Forwarding


Detecting the Need to Forward

• Pass register numbers along pipeline– e.g., ID/EX.RegisterRs = register number for Rs

sitting in ID/EX pipeline register

• ALU operand register numbers in EX stage are given by– ID/EX.RegisterRs, ID/EX.RegisterRt

• Data hazards when1a. EX/MEM.RegisterRd = ID/EX.RegisterRs1b. EX/MEM.RegisterRd = ID/EX.RegisterRt2a. MEM/WB.RegisterRd = ID/EX.RegisterRs2b. MEM/WB.RegisterRd = ID/EX.RegisterRt

Fwd fromEX/MEMpipeline reg

Fwd fromMEM/WBpipeline reg


Detecting the Need to Forward

• But only if forwarding instruction will write to a register!– EX/MEM.RegWrite, MEM/WB.RegWrite

• And only if Rd for that instruction is not $zero– EX/MEM.RegisterRd ≠ 0,

MEM/WB.RegisterRd ≠ 0


Forwarding Paths


Forwarding Conditions

• EX hazard– if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10

– if (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠ 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10

• MEM hazard– if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01

– if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01


Double Data Hazard

• Consider the sequence:add $1,$1,$2add $1,$1,$3add $1,$1,$4

• Both hazards occur– Want to use the most recent

• Revise MEM hazard condition– Only fwd if EX hazard condition isn’t true


Revised Forwarding Condition

• MEM hazard– if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠

0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRs))

and (MEM/WB.RegisterRd = ID/EX.RegisterRs))

ForwardA = 01

– if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0)

and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd ≠

0)

and (EX/MEM.RegisterRd = ID/EX.RegisterRt))

and (MEM/WB.RegisterRd = ID/EX.RegisterRt))

ForwardB = 01


Datapath with Forwarding


Load-Use Data Hazard

Need to stall for one cycle


Load-Use Hazard Detection

• Check when using instruction is decoded in ID stage

• ALU operand register numbers in ID stage are given by– IF/ID.RegisterRs, IF/ID.RegisterRt

• Load-use hazard when– ID/EX.MemRead and

((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))

• If detected, stall and insert bubble


How to Stall the Pipeline

• Force control values in ID/EX registerto 0– EX, MEM and WB do nop (no-operation)

• Prevent update of PC and IF/ID register– Using instruction is decoded again– Following instruction is fetched again– 1-cycle stall allows MEM to read data for lw

• Can subsequently forward to EX stage


Stall/Bubble in the Pipeline

Stall inserted here


Stall/Bubble in the Pipeline

Or, more accurately…


Datapath with Hazard Detection


Stalls and Performance

• Stalls reduce performance– But are required to get correct results

• Compiler can arrange code to avoid hazards and stalls– Requires knowledge of the pipeline

structure

The BIG Picture


Branch Hazards

• If branch outcome determined in MEM

§4.8 Control H

azards

PC

Flush theseinstructions(Set controlvalues to 0)


Reducing Branch Delay

• Move hardware to determine outcome to ID stage– Target address adder– Register comparator

• Example: branch taken36: sub $10, $4, $840: beq $1, $3, 744: and $12, $2, $548: or $13, $2, $652: add $14, $4, $256: slt $15, $6, $7 ...72: lw $4, 50($7)


Example: Branch Taken


Data Hazards for Branches

• If a comparison register is a destination of 2nd or 3rd preceding ALU instruction

…

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

IF ID EX MEM WB

add $4, $5, $6

add $1, $2, $3

beq $1, $4, target

• Can resolve using forwarding



• If a comparison register is a destination of preceding ALU instruction or 2nd preceding load instruction– Need 1 stall cycle

beq stalled

IF ID EX MEM WB

IF ID EX MEM WB

IF ID

ID EX MEM WB

add $4, $5, $6

lw $1, addr

beq $1, $4, target



• If a comparison register is a destination of immediately preceding load instruction– Need 2 stall cycles

beq stalled

IF ID EX MEM WB

IF ID

ID

ID EX MEM WB

beq stalled

lw $1, addr

beq $1, $0, target


Dynamic Branch Prediction

• In deeper and superscalar pipelines, branch penalty is more significant

• Use dynamic prediction– Branch prediction buffer (aka branch history table)– Indexed by recent branch instruction addresses– Stores outcome (taken/not taken)– To execute a branch

• Check table, expect the same outcome• Start fetching from fall-through or target• If wrong, flush pipeline and flip prediction


1-Bit Predictor: Shortcoming

• Inner loop branches mispredicted twice!outer: … …inner: … … beq …, …, inner … beq …, …, outer

– Mispredict as taken on last iteration of inner loop

– Then mispredict as not taken on first iteration of inner loop next time around


2-Bit Predictor

• Only change prediction on two successive mispredictions


Calculating the Branch Target

• Even with predictor, still need to calculate the target address– 1-cycle penalty for a taken branch

• Branch target buffer– Cache of target addresses– Indexed by PC when instruction fetched

• If hit and instruction is branch predicted taken, can fetch target immediately


Exceptions and Interrupts

• “Unexpected” events requiring changein flow of control– Different ISAs use the terms differently

• Exception– Arises within the CPU

• e.g., undefined opcode, overflow, syscall, …

• Interrupt– From an external I/O controller

• Dealing with them without sacrificing performance is hard

§4.9 Exceptions


Handling Exceptions

• In MIPS, exceptions managed by a System Control Coprocessor (CP0)

• Save PC of offending (or interrupted) instruction– In MIPS: Exception Program Counter (EPC)

• Save indication of the problem– In MIPS: Cause register– We’ll assume 1-bit

• 0 for undefined opcode, 1 for overflow

• Jump to handler at 8000 00180


An Alternate Mechanism

• Vectored Interrupts– Handler address determined by the cause

• Example:– Undefined opcode: C000 0000– Overflow: C000 0020– …: C000 0040

• Instructions either– Deal with the interrupt, or– Jump to real handler


Handler Actions

• Read cause, and transfer to relevant handler

• Determine action required• If restartable

– Take corrective action– use EPC to return to program

• Otherwise– Terminate program– Report error using EPC, cause, …


Exceptions in a Pipeline

• Another form of control hazard• Consider overflow on add in EX stage

add $1, $2, $1– Prevent $1 from being clobbered– Complete previous instructions– Flush add and subsequent instructions– Set Cause and EPC register values– Transfer control to handler

• Similar to mispredicted branch– Use much of the same hardware


Pipeline with Exceptions


Exception Properties

• Restartable exceptions– Pipeline can flush the instruction– Handler executes, then returns to the

instruction• Refetched and executed from scratch

• PC saved in EPC register– Identifies causing instruction– Actually PC + 4 is saved

• Handler must adjust


Exception Example

• Exception on add in40 sub $11, $2, $444 and $12, $2, $548 or $13, $2, $64C add $1, $2, $150 slt $15, $6, $754 lw $16, 50($7)…

• Handler80000180 sw $25, 1000($0)80000184 sw $26, 1004($0)…


Exception Example


Multiple Exceptions

• Pipelining overlaps multiple instructions– Could have multiple exceptions at once

• Simple approach: deal with exception from earliest instruction– Flush subsequent instructions– “Precise” exceptions

• In complex pipelines– Multiple instructions issued per cycle– Out-of-order completion– Maintaining precise exceptions is difficult!


Imprecise Exceptions

• Just stop pipeline and save state– Including exception cause(s)

• Let the handler work out– Which instruction(s) had exceptions– Which to complete or flush

• May require “manual” completion

• Simplifies hardware, but more complex handler software

• Not feasible for complex multiple-issueout-of-order pipelines


Instruction-Level Parallelism (ILP)

• Pipelining: executing multiple instructions in parallel

• To increase ILP– Deeper pipeline

• Less work per stage shorter clock cycle

– Multiple issue• Replicate pipeline stages multiple pipelines• Start multiple instructions per clock cycle• CPI < 1, so use Instructions Per Cycle (IPC)• E.g., 4GHz 4-way multiple-issue

– 16 BIPS, peak CPI = 0.25, peak IPC = 4

• But dependencies reduce this in practice

§4.10 Parallelism

and Advanced Instruction Level P

arallelism


Multiple Issue

• Static multiple issue– Compiler groups instructions to be issued together– Packages them into “issue slots”– Compiler detects and avoids hazards

• Dynamic multiple issue– CPU examines instruction stream and chooses

instructions to issue each cycle– Compiler can help by reordering instructions– CPU resolves hazards using advanced techniques

at runtime


Speculation

• “Guess” what to do with an instruction– Start operation as soon as possible– Check whether guess was right

• If so, complete the operation• If not, roll-back and do the right thing

• Common to static and dynamic multiple issue• Examples

– Speculate on branch outcome• Roll back if path taken is different

– Speculate on load• Roll back if location is updated


Compiler/Hardware Speculation

• Compiler can reorder instructions– e.g., move load before branch– Can include “fix-up” instructions to recover

from incorrect guess

• Hardware can look ahead for instructions to execute– Buffer results until it determines they are

actually needed– Flush buffers on incorrect speculation


Speculation and Exceptions

• What if exception occurs on a speculatively executed instruction?– e.g., speculative load before null-pointer

check

• Static speculation– Can add ISA support for deferring

exceptions

• Dynamic speculation– Can buffer exceptions until instruction

completion (which may not occur)


Static Multiple Issue

• Compiler groups instructions into “issue packets”– Group of instructions that can be issued on

a single cycle– Determined by pipeline resources required

• Think of an issue packet as a very long instruction– Specifies multiple concurrent operations Very Long Instruction Word (VLIW)


Scheduling Static Multiple Issue

• Compiler must remove some/all hazards– Reorder instructions into issue packets– No dependencies with a packet– Possibly some dependencies between

packets• Varies between ISAs; compiler must know!

– Pad with nop if necessary


MIPS with Static Dual Issue

• Two-issue packets– One ALU/branch instruction– One load/store instruction– 64-bit aligned

• ALU/branch, then load/store• Pad an unused instruction with nop

Address Instruction type Pipeline Stages

n ALU/branch IF ID EX MEM WB

n + 4 Load/store IF ID EX MEM WB

n + 8 ALU/branch IF ID EX MEM WB


n + 16 ALU/branch IF ID EX MEM WB



MIPS with Static Dual Issue


Hazards in the Dual-Issue MIPS

• More instructions executing in parallel• EX data hazard

– Forwarding avoided stalls with single-issue– Now can’t use ALU result in load/store in same

packet• add $t0, $s0, $s1load $s2, 0($t0)

• Split into two packets, effectively a stall

• Load-use hazard– Still one cycle use latency, but now two

instructions

• More aggressive scheduling required


Scheduling Example

• Schedule this for dual-issue MIPSLoop: lw $t0, 0($s1) # $t0=array element addu $t0, $t0, $s2 # add scalar in $s2 sw $t0, 0($s1) # store result addi $s1, $s1,–4 # decrement pointer bne $s1, $zero, Loop # branch $s1!=0

ALU/branch Load/store cycle

Loop: nop lw $t0, 0($s1) 1

addi $s1, $s1,–4 nop 2

addu $t0, $t0, $s2 nop 3

bne $s1, $zero, Loop sw $t0, 4($s1) 4

– IPC = 5/4 = 1.25 (c.f. peak IPC = 2)


Loop Unrolling

• Replicate loop body to expose more parallelism– Reduces loop-control overhead

• Use different registers per replication– Called “register renaming”– Avoid loop-carried “anti-dependencies”

• Store followed by a load of the same register• Aka “name dependence”

– Reuse of a register name


Loop Unrolling Example

• IPC = 14/8 = 1.75– Closer to 2, but at cost of registers and code size

ALU/branch Load/store cycle

Loop: addi $s1, $s1,–16 lw $t0, 0($s1) 1

nop lw $t1, 12($s1) 2

addu $t0, $t0, $s2 lw $t2, 8($s1) 3

addu $t1, $t1, $s2 lw $t3, 4($s1) 4

addu $t2, $t2, $s2 sw $t0, 16($s1) 5

addu $t3, $t4, $s2 sw $t1, 12($s1) 6

nop sw $t2, 8($s1) 7

bne $s1, $zero, Loop sw $t3, 4($s1) 8


Dynamic Multiple Issue

• “Superscalar” processors

• CPU decides whether to issue 0, 1, 2, … each cycle– Avoiding structural and data hazards

• Avoids the need for compiler scheduling– Though it may still help– Code semantics ensured by the CPU


Dynamic Pipeline Scheduling

• Allow the CPU to execute instructions out of order to avoid stalls– But commit result to registers in order

• Examplelw $t0, 20($s2)addu $t1, $t0, $t2sub $s4, $s4, $t3slti $t5, $s4, 20

– Can start sub while addu is waiting for lw


Dynamically Scheduled CPU

Results also sent to any waiting

reservation stations

Reorders buffer for register writes

Can supply operands for

issued instructions

Preserves dependencies

Hold pending operands


Register Renaming

• Reservation stations and reorder buffer effectively provide register renaming

• On instruction issue to reservation station– If operand is available in register file or reorder

buffer• Copied to reservation station• No longer required in the register; can be overwritten

– If operand is not yet available• It will be provided to the reservation station by a function

unit• Register update may not be required


Speculation

• Predict branch and continue issuing– Don’t commit until branch outcome

determined

• Load speculation– Avoid load and cache miss delay

• Predict the effective address• Predict loaded value• Load before completing outstanding stores• Bypass stored values to load unit

– Don’t commit load until speculation cleared


Why Do Dynamic Scheduling?

• Why not just let the compiler schedule code?

• Not all stalls are predicable– e.g., cache misses

• Can’t always schedule around branches– Branch outcome is dynamically determined

• Different implementations of an ISA have different latencies and hazards


Does Multiple Issue Work?

• Yes, but not as much as we’d like• Programs have real dependencies that limit ILP• Some dependencies are hard to eliminate

– e.g., pointer aliasing

• Some parallelism is hard to expose– Limited window size during instruction issue

• Memory delays and limited bandwidth– Hard to keep pipelines full

• Speculation can help if done well

The BIG Picture


Power Efficiency

• Complexity of dynamic scheduling and speculations requires power

• Multiple simpler cores may be better

Microprocessor Year Clock Rate Pipeline Stages

Issue width

Out-of-order/

Speculation

Cores Power

i486 1989 25MHz 5 1 No 1 5W

Pentium 1993 66MHz 5 2 No 1 10W

Pentium Pro 1997 200MHz 10 3 Yes 1 29W

P4 Willamette 2001 2000MHz 22 3 Yes 1 75W

P4 Prescott 2004 3600MHz 31 3 Yes 1 103W

Core 2006 2930MHz 14 4 Yes 2 75W

UltraSparc III 2003 1950MHz 14 4 No 1 90W

UltraSparc T1 2005 1200MHz 6 1 No 8 70W


The Opteron X4 Microarchitecture

§4.11 Real S

tuff: The A

MD

Opteron X

4 (Barcelona) P

ipeline

72 physical registers


The Opteron X4 Pipeline Flow

• For integer operations

– FP is 5 stages longer– Up to 106 RISC-ops in progress

• Bottlenecks– Complex instructions with long dependencies– Branch mispredictions– Memory access delays


Fallacies

• Pipelining is easy (!)– The basic idea is easy– The devil is in the details

• e.g., detecting data hazards

• Pipelining is independent of technology– So why haven’t we always done pipelining?– More transistors make more advanced

techniques feasible– Pipeline-related ISA design needs to take

account of technology trends• e.g., predicated instructions

§4.13 Fallacies and P

itfalls


Pitfalls

• Poor ISA design can make pipelining harder– e.g., complex instruction sets (VAX, IA-32)

• Significant overhead to make pipelining work• IA-32 micro-op approach

– e.g., complex addressing modes• Register update side effects, memory indirection

– e.g., delayed branches• Advanced pipelines have long delay slots


Concluding Remarks

• ISA influences design of datapath and control• Datapath and control influence design of ISA• Pipelining improves instruction throughput

using parallelism– More instructions completed per second– Latency for each instruction not reduced

• Hazards: structural, data, control• Multiple issue and dynamic scheduling (ILP)

– Dependencies limit achievable parallelism– Complexity leads to the power wall

§4.14 Concluding R

emarks

based on slides from d. patterson and cs152

Documents

fritz spring

instruction address

instruction classesin

instruction executionsend

different instruction

type of instruction

branch instruction

instruction classuse