TRNG I HC BCH KHOA H NI

VIN CNG NGH THNG TIN V TRUYN THNG

BO CO

GRADUATION RESEARCH 1

Gio vin hng dn:

TS. Nguyn Kim Khnh

Sinh vin thc hin :

Nguyn Trng Giang

MSSV:

20100228

Lp:

Vit Nht IS2 K55

H NI, 5/2014

Mc lc

1. Tm hiu v DE2i-150 Development Kit .............................................................. 1

1.1. Gii thiu chung v DE2i-150 ....................................................................................................... 1

1.2. Cu to ca DE2i-150 ................................................................................................................... 1

1.2.1. S khi ............................................................................................................................. 1

1.2.3. B vi x l............................................................................................................................. 2

1.2.3. B FPGA ................................................................................................................................. 3

1.3.Nhng im u vit ca DE2i-150 ................................................................................................ 4

2. Tm hiu phn mm Quartus II, ModelSim v ngn ng lp trnh VHDL ......... 5

2.1. Quartus II...................................................................................................................................... 5

2.1.1. Gii thiu v Quartus II ......................................................................................................... 5

2.1.2. To project ............................................................................................................................ 6

2.1.3. Bin dch v np .................................................................................................................... 9

2.2. ModelSim Altera ........................................................................................................................ 11

2.2.1. Gii thiu v ModelSim Altera ........................................................................................... 11

2.2.2. To mt project vi ModelSim Altera ................................................................................ 11

2.2.3. Bin dch v chy m phng. .............................................................................................. 14

2.3. S dng kt hp Quartus II v ModelSim ................................................................................. 16

2.4. VHDL ........................................................................................................................................... 17

2.4.1. Gii thiu v VHDL .............................................................................................................. 17

2.4.2. Cu trc chng trnh vit bng VHDL ............................................................................... 17

2.3.3. Kiu d liu: ........................................................................................................................ 19

2.3.4. SIGNAL v VARIABLE ........................................................................................................... 20

2.3.4. Ton t ................................................................................................................................ 20

2.4.5. GENERIC .............................................................................................................................. 21

2.4.6. M song song ...................................................................................................................... 22

2.4.7. M tun t .......................................................................................................................... 22

3.Tm hiu v FPGA ................................................................................................ 24

3.1. Khi nim ................................................................................................................................... 24

3.2. So snh FPGA vi cc loi vi mch khc ..................................................................................... 24

3.3. Cu to ca FPGA ....................................................................................................................... 24

3.3.1. Logic Blocks ....................................................................................................................... 25

3.3.2. Programmable Interconnects ............................................................................................... 26

3.3.3. I/O Blocks ........................................................................................................................... 26

3.3.4. Cc khi thit k sn ........................................................................................................... 27

3.4. ng dng ca FPGA ................................................................................................................... 27

4. Hng nghin cu ............................................................................................. 28

4.1. Hng nghin cu: .................................................................................................................... 28

4.2. L do chn ti: ........................................................................................................................ 28

4.2. Mc tiu nghin cu .................................................................................................................. 28

4.4. Cc vn s nghin cu........................................................................................................... 28

Danh mc ti liu tham kho ..................................................................................... 29

Danh mc hnh v Hnh 1.1: S khi ca kit DE2i-150 ....................................................................... 1 Hnh 2.1: Giao din ca Quartus II 12.0 ..................................................................... 5 Hnh 3.1: S khi FPGA ...................................................................................... 25 Hnh 3.2. Mt s v d ca logic cell ......................................................................... 25 Hnh 3.3. S khi chuyn mch lp trnh c ................................................... 26 Hnh 3.4. Cu trc PIP ............................................................................................. 26 Hnh 3.5. Mt v d m hnh I/O cell ......................................................................... 27

1

1. Tm hiu v DE2i-150 Development Kit

1.1. Gii thiu chung v DE2i-150 DE2i-150 l mt nn tng t ph, vi s kt hp ca b vi x l nhng Intel N2600 v b Altera Cyclone IV GX FPGA ca hng Altera. Chnh nh s kt hp ny, DE2i-150 tr thnh mt h thng my tnh y tnh nng, v c hiu nng x l rt cao. c bit, b Altera Cyclone IV GX FPGA nm trn board DE2i-150 c th tng tc kh nng p ng ca h thng m vn gi nguyn chi ph gii php v hiu qu nng lng.

DE2i-150 c n 150.000 phn t logic, vi s mn do, linh hot ca kh nng ti cu trc phn cng, n c th p ng cho bt c nhim v no.

B vi x l ca Intel v b thit b FPGA c lin kt vi nhau thng qua 2 lung PCIe tc cao, m bo cho vic truyn d liu gia chng t tc cao.

Chnh nh nhng iu ny, DE2i-150 s l mt cng c tuyt vi x l cc tc v c bit, cng nh thit k phn cng.

1.2. Cu to ca DE2i-150

1.2.1. S khi

Hnh 1.1: S khi ca kit DE2i-150

2

Qua s trn, ta c th nhn thy, kit DE2i-150 gm 2 khi: khi bn tri l Intel Atom Processor, khi bn phi l FPGA Altera Cyclone GX. Hai khi lin kt vi nhau bi 2 ng PCIe.

1.2.3. B vi x l

Cc thng s k thut:

CPU : Intel Atom Dual Core Processor N2600( 1M Cache, 1.6GHz )

Intel Hyper-Threading Technology

Intel SpeedStep Technology

Instruction Set : 64-bit

Instruction Set Extensions : SSE2, SSE3, SSSE3

Integrated Graphics

Graphics Base Frequency : 400MHz

Chipset : Intel NM10 Express Chipset

DMI x2 to CPU

Intel High Definition Audio

Serial ATA (SATA) 3 Gb/s

Universal Serial Bus(USB) Hi-Speed USB 2.0

PCI Express Gen 1

Memory

DDR3 SO-DIMM SDRAM

Display

VGA

HDMI 1.3a

Intel Centrino Wireless-N 135

802.11b/g/n

Bluetooth 4.0

Wi-Fi Direct

Audio Codec

Realtek ALC272VA3-GR

BIOS

DIP package Bios Flash : GD25Q16

Programming Interface for Bios : Dedi-Prog Interface

Debug Interface

XDP header

Clock System

CK505 : 9VRS4339B

32768 Hz RTC crystal

27MHz VGA clock source

Ethernet

3

Intel 82583V GbE Controller

10/100/1000 Mb/s RJ45

3 status indicting LEDs

Others

Power header for hard-disk

Current limit for USB

Buzzer

Mini PCIE header (Default for Intel Centrino Wireless-N 135 WiFi

module)

mSATA header

RTC battery : CR2032

1.2.3. B FPGA

Cc thng tin chi tit ca b FPGA:

Featured Devices

Cyclone IV EP4CGX150DF31 device

149,760 Les

720 M9K memory blocks

6,480 Kbits embedded memory

8 PLLs

FPGA configuration

JTAG and AS mode configuration

EPCS64 serial configuration device

On-board USB Blaster circuitry

Memory devices

128MB (32Mx32bit) SDRAM

4MB (1Mx32) SSRAM

64MB (4Mx16) Flash with 16-bit mode

SD Card socket

Provides SPI and 4-bit SD mode for SD Card access

Connectors

Ethernet 10/100/1000 Mbps ports

High Speed Mezzanine Card (HSMC)

40-pin expansion port

VGA-out connector

VGA DAC (high speed triple DACs)

DB9 serial connector for RS-232 port with flow control

Clock

Three 50MHz oscillator clock inputs

SMA connectors (external clock input/output)

4

Display

16x2 LCD module

Switches and indicators

18 slide switches and 4 push-buttons switches

18 red and 9 green LEDs

Eight 7-segment displays

Other features

Infrared remote-control receiver module

TV decoder (NTSC/PAL/SECAM) and TV-in connector

1.3.Nhng im u vit ca DE2i-150 S kt hp gia b vi x l Intel Atom v b FPGA ca Altera gip cho kit tr

thnh mt h thng hon chnh, mnh m v y cc chc nng.

S lng thnh phn logic ln (150.000 phn t logic) vi kh nng ti cu trc linh hot, mm do.

c nh sn xut cung cp cc phn mm, mi trng ph hp trn c windown v linux

C y cc h thng vo ra v kt ni mng

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2. Tm hiu phn mm Quartus II, ModelSim v ngn ng lp trnh VHDL

2.1. Quartus II

2.1.1. Gii thiu v Quartus II

Quartus II l mt sn phm phn mm ca hng Altera . N cung cp mi trng thit k hon thin, a nn tng, d dng p ng cc nhu cu thit k c th. N l mt mi trng ton din cho vic thit k SOPC(system-on-a-programmable-chip). Quartus II bao gm cc gii php cho c qu trnh thit k FPGA v CPLD.

Quartus II cung cp cc kh nng thit k sau: Cng c son tho: VHDL, AHDL v Verilog HDL. L cng c mnh m trong tng hp logic Phn tch thi gian (timming analysis) T ng nh v li Place & Route C giao din ha v giao din dng lnh tin dng T ng nhn din cc linh kin khi kt ni Phn tch logic nhng vi cng c phn tch SignalTap II

.

Hnh 2.1: Giao din ca Quartus II 12.0

6

2.1.2.To project

T giao din chnh ca Quartus II, chn File > New Project Winzard

Chn Next tip tc, sau in vo ni lu tr project, nhp tn project

7

Chn next chn file cn include vo project nu c. Nu khng c th n next ngay

Sau khi add file thnh cng, n next tip tc thit lp linh kin (Family & Device Settings), chn FPGA m ta dng.

8

n next tip tc thit lp b cng c EDA, thng th Quartus II s mc nh cng c m phng l ModelSim-Altera, v ngn ng VHDL. Bn c th chn ngn ng v b phng ty , ngoi ra cn cung cp b Timming, Symbol

n next tip tc, mt mn hnh s hin ra ghi li nhng thng s ta thit lp cho project.

n Finish hon thnh, hoc back chnh sa cc thng s.

9

Sau khi project c to, chn file > New file to mt file mi v bt u lp trnh. n file > Save lu file.

2.1.3.Bin dch v np

Sau khi code xong mt file, ch nh chn pin cho u ra v u vo. Chn Processing > Start > Start Analysis & Elaboration. Sau chn Assignments > Pins Planner, chn cc chn cho u vo v u ra ty vo tng thit b

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bin dch file ta chn Processing > Start Compilation. Nu file c li s hin thng bo di nh hnh di.

C th n trc tip vo li hin th a code b li. Qu trnh bin dch hon thnh khi khng c li, v ta bt u np chng trnh chy vo phn cng. Trc tin c th np chng trnh chy vo phn cng, ta phi kt ni phn cng vi my tnh. Sau chn Tools > Programmer, ca s Programmer xut hin.

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Click vo Hardware Setup, trong mc currently selected hardware chn USB-Blaster [USB-0]

Sau click vo Close.

Nu trong Programmer cha c file cn np th chn Add file chn file. Chn file cn np v n Start bt u np vo phn cng.

2.2. ModelSim Altera

2.2.1. Gii thiu v ModelSim Altera

ModelSim Altera cng l mt sn phm phn mm do hng Altera cung cp, l mt cng c va c kh nng lp trnh phn cng, va c kh nng chy m phng.

2.2.2. To mt project vi ModelSim Altera

T giao din chnh, chn File>New project, in tn project v chn ng d lu project.

12

Ca s Add items to the Project hin ra, yu cu thm i tng vo cho Project. Chn Create New File.

13

Trong ca s Create Project File, nhp tn ca file, chn kiu file.

Sau khi to xong file, ca s editor hin ra, cho php ta lp trnh.

14

2.2.3. Bin dch v chy m phng.

Sau khi to xong file, bin dch, chn Compile>Compile All

Nu khng c li g xy ra trong qu trnh bin dch, ta c th bt u chy m phng bng cch chon Simulate > Start Simulate.

15

Ca s Start Simulation hin ra, chn vo tab Design > work > ten_file v n OK:

chn dng m phng wave, chn Add>To Wave>All items in region:

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Trong tab Wave, chut phi vo cc bin u vo,chn force thit lp gi tr, tip tc chn Simulate > Run 100

2.3. S dng kt hp Quartus II v ModelSim

Chng ta c th s dng kt hp Quartus II v ModelSim thit k mch v chy m phng.Trong Quartus II ng vai tr l cng c lp trnh, v v s thit k mch,ModelSim ng vai tr l cng c chy m phng kim tra tnh ng n ca mch c thit k bng Quartus II.

s dng kt hp Quartus II v ModelSim, ta cn chn ModelSim l cng c m phng trong bc to project trong Quartus II(Xem mc 2.1.2.To project) hoc chut phi vo thit b trong Entity > Settings > Simulation, trong mc Tool name > ModelSim-Altera.

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2.4. VHDL

2.4.1. Gii thiu v VHDL

VHDL(Very high speed integrated circuit Hardware Description Language) l mt trong cc ngn ng m t phn cng c s dng rng ri hin nay. VHDL l ngn ng m t phn cng cho cc vi mch tch hp c tc cao nh FPGA, CPLD VHDL cng c s dng nh mt ngn ng lp trnh song song.

VHDL l ngn ng m phng phn cng c pht trin dng cho chng trnh VHSIC (Very High Speed Intergrated Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m phng phn cng tiu chun v thng nht cho php pht trin th nghim cc h thng s nhanh hn, cng nh cho php d dng a cc h thng vo ng dng trong thc t

2.4.2. Cu trc chng trnh vit bng VHDL

Mt on Code VHDL chun cn c ti thiu 3 mc sau: LIBRARY(th vin): cha mt danh sch ca tt c cc th vin c s dng

trong thit k. V d: ieee, std, work, VD:

LIBRARY library_name;

USE library_name.package_name.package_parts;

ENTITYI(thc th): M t cc chn vo ra (I/O pins) ca mch. C php nh sau:

ENTITY entity_name IS

PORT (

port_name : signal_mode signal_type;

port_name : signal_mode signal_type;

...);

END entity_name;

Signal_mode: c th l IN, OUT, INOUT, hoc BUFFER Signal_type: kiu d liu, c th l BIT, STD_LOGIC, INTERGER Port_name: tn ca cng, c th l bt c g, ngoi tr cc t kha ca VHDL

Vd: ENTITY nand_gate IS

PORT (a, b : IN BIT;

x : OUT BIT);

END nand_gate;

ARCHITECTURE(kin trc): cha m VHDL, m t mch s hat ng nh th no. C php nh sau:

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ARCHITECTURE architecture_name OF entity_name IS

[declarations]

BEGIN

(code)

END architecture_name;

[declarations]: phn m t, ni cc tn hiu v cc hng c khai bo

Vd: ARCHITECTURE tg OF nand_gate IS

BEGIN

x

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Tn_componemt port [ danh sch ]; End component;

M hnh kt hp: l s kt hp ca hai m hnh trn

2.3.3. Kiu d liu:

Cc kiu d liu tin nh ngha: BIT v BIT_VECTOR: 2 mc logic 0 v 1

STD_LOGIC v STD_LOGIC_VECTOR H logic 8 gi tr sau y c gii tiu trong chun IEEE 1164:

- X khng xc nh ( bt buc) - 0 mc thp ( bt buc) - 1 mc cao ( bt buc) - Z tr khng cao - W khng xc nh (yu) - L mc thp ( yu) - H mc cao ( yu) - - khng quan tm

STD_ULOGIC v STD_ULOGIC_VECTOR: l m rng ca STD_LOGIC v STD_LOGIC_VECTOR, thm mt gi tr logic l U

Cc kiu d liu ngi dng nh ngha: Vd:

TYPE integer IS RANGE -2147483647 TO +2147483647; -- nh ngha kiu interger

TYPE my_logic IS ('0', '1', 'Z'); -- Mt tp con ca std_logic m ngi dng nh ngha

Cc kiu con: l kiu d liu i km theo iu kin dng buc Vd:

SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH; -- natural l mt kiu con (tp con) ca INTEGER, vi gi tr t 0->INTERGERHIGH

Mng: l mt tp hp cc gi tr cng kiu. Mng c th l mng 1 chiu (1D), hai chiu (2D), hoc l mng 1 chiu ca 1 chiu(1Dx1D) v c th l cc mng c chiu cao hn. ch nh mt kiu mng mi:

TYPE type_name IS ARRAY (specification) OF data_type; to s dng kiu mng mi:

SIGNAL signal_name: type_name [:= initial_value];

Mng cng Kiu bn ghi: tng t nh mng, nhng cha nhng kiu gi tr khc nhau

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Vd: TYPE birthday IS RECORD

day: INTEGER RANGE 1 TO 31;

month: month_name;

END RECORD; Kiu d liu c du v khng du: c nh ngha trong gi std_logic_arith

ca th vin ieee, dng biu din s c du v khng du.

Vd: SIGNAL x: SIGNED (7 DOWNTO 0);

SIGNAL y: UNSIGNED (0 TO 3);

Chuyn i d liu: VHDL khng cho php cc php ton trc tip ( s hc, logic, ) tc ng ln cc d liu khc kiu nhau. Nhiu hm chuyn i d liu c th c tm trong gi std_logic_arith ca th vin ieee:

conv_integer(p):chuyn i mt tham s p ca kiu INTEGER, UNSIGNED, SIGNED, hoc STD_ULOGIC thnh mt gi tr INTEGER. Lu rng STD_LOGIC_VECTOR khng c k n.

conv_unsigned(p, b): chuyn i mt tham s p ca kiu INTEGER, UNSIGNED, SIGNED, hoc STD_ULOGIC thnh mt gi tr UNSIGNED vi kch c l b bit.

conv_signed(p, b): chuyn i mt tham s p ca kiu INTEGER, UNSIGNED, SIGNED, hoc STD_ULOGIC thnh mt gi tr SIGNED vi kch c l b bits.

conv_std_logic_vector(p, b): chuyn i mt tham s p thuc kiu d liu INTEGER, UNSIGNED, SIGNED, hoc STD_LOGIC thnh mt gi tr STD_LOGIC_VECTOR vi kch thc b bits.

2.3.4. SIGNAL v VARIABLE

VHDL c hai cch nh ngha cc gi tr khng tnh: bng SIGNAL hoc bng VARIABLE.

SIGNAL c th c khai bo trong PACKAGE, ENTITY hoc ARCHITECTURE (trong phn khai bo ca n).

VARIABLE c th c m t bn trong mt phn ca m tun t.

Gi tr ca VARIABLE c th khng bao gi nh ngha ngoi PROCESS mt cch trc tip, nu cn, th n phi c gn thnh SIGNAL.

Php ton gn cho SIGNAL l

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Vd: SIGNAL x : STD_LOGIC;

VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);

x So snh ln hn. = So snh ln hn hoc bng.

Ton t dch C php s dng ton t dch l:

Trong : c kiu l BIT_VECTOR c kiu l INTEGER. C hai ton t dch:

- Sll Ton t dch tri. in 0 vo pha phi. - Rll Ton t dch phi. in 0 vo pha tri.

2.4.5. GENERIC

GENERIC l mt cch to cc tham s dng chung (ging nh cc bin static trong cc ngn ng lp trnh). Tham s ny c th gi c t bt c ni no, trong mt

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ENTITY hay ARCHITECTURE. Mc ch l cho cc on code mm do v d s dng li hn. Mt on GENERIC mun s dng c cn phi c m t trong ENTITY. Cc tham s phi c ch r. Cu trc nh sau:

GENERIC (parameter_name : parameter_type := parameter_value);

Vd: GENERIC (n : INTEGER := 8);=> Bin n c th gi t bt c u v gi tr ca n lun l 8.

2.4.6. M song song

M ngun VHDL ch yu l m song song, ngoi tr cc on m trong PROCESS, FUNTION, PROCEDURE. M song song cn c gi l m lung d liu. Cc cch to m song song:

S dng cc ton t Mnh WHEN

Vd:

------ With WHEN/ELSE -------------------------

outp

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ELSE assignments;

END IF; WAIT:

C php:

WAIT UNTIL signal_condition;

WAIT ON signal1 [, signal2, ... ];

WAIT FOR time; CASE

C php:

CASE identifier IS

WHEN value => assignments;

WHEN value => assignments;

...

END CASE; LOOP

C php:

FOR/LOOP: vng lp c lp li mt s ln c nh.

[label:] FOR identifier IN range LOOP

(sequential statements)

END LOOP [label];

WHILE/LOOP: vng lp c lp cho n khi iu kin khng tho mn.

[label:] WHILE condition LOOP

(sequential statements)

END LOOP [label];

EXIT: s dng kt thc vng lp.

[label:] EXIT [label] [WHEN condition]; NEXT: s dng b qua cc bc vng lp.

[label:] NEXT [loop_label] [WHEN condition];

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3.Tm hiu v FPGA 3.1.Khi nim Field-programmable gate array (FPGA) l mt mch tch hp, c th cu trc li mng phn t logic bi ngi s dng hoc lp trnh vin, bng cch s dng ngn ng lp trnh m t phn cng HDL nh VHDL, Verilog, AHDL

Hin nay FPGA tch hp c mt s lng ln cc cng logic v cc khi RAM x l cc tnh ton phc tp. ng thi n cng c trang b cc cng I/O tc cao, m bo v mt thi gian cho vic truyn v nhn d liu. FPGA c th thc hin c bt c nhim v no m mt ASIC c th thc hin, cng vi kh nng ti cu trc linh hot, FPGA c u th trong nhiu ng dng.

3.2.So snh FPGA vi cc loi vi mch khc

FPGA cng c xem nh mt loi vi mch bn dn chuyn dng ASIC, nhng nu so snh FPGA vi nhng ASIC c ch hon ton hay ASIC thit k trn th vin logic th FPGA khng t c mc ti u nh nhng loi ny, v hn ch trong kh nng thc hin cc tc v c bit phc tp, tuy nhin FPGA li u vit hn ch c th ti cu trc li khi ang s dng, cng on thit k n gin hn, do vy chi ph gim, rt ngn thi gian a sn phm vo s dng.

Cn nu so snh vi cc dng vi mch bn dn lp trnh c dng cu trc mng phn t logic nh PLA, PAL, CPLD th FPGA u vit hn c im: tc v ti lp trnh ca FPGA c thc hin n gin hn; kh nng lp trnh linh ng hn; v khc bit quan trng nht l kin trc ca FPGA cho php n c kh nng cha khi lng ln cng logic.

3.3.Cu to ca FPGA FPGA c cu to t 3 thnh phn chnh:

Cc khi logic c bn (Logic Blocks, ngoi ra cn c tn gi khc nh: CLB, Logic Array Block, LABty vo nh sn xut).

H thng mch lin kt lp trnh c (Programmable Interconnects hay routing channels).

Cc khi vo ra (I/0 Block).

Ngoi ra FPGA cn c trang b cc phn t thit k sn nh: DSP slice, RAM, ROM, nhn vi x l

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Hnh 3.1: S khi FPGA

3.3.1.Logic Blocks

Mi khi logic thng thng c to nn t mt vi phn t logic cell. Mi logic cell in hnh bao gm:

Mt b LUT(look up table) Mt b cng y FA Mt b D flip-flop DFF.

Hnh 3.2. Mt s v d ca logic cell

Trong hnh trn, khi LUT c chia lm 2 khi 3-LUT(LUT vi 3 u vo). Nhng thng thng 2 khi 3-LUT c kt hp li thnh 1 khi 4-LUT(LUT vi 4 u vo) thng qua b MUX. Hin nay khi LUT cn c b sung thm 2 u vo kt ni t cc khi logic trc v sau n, nng tng s u vo ca LUT ln 6 chn. Cu trc ny nhm tng tc cc b s hc logic.

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3.3.2.Programmable Interconnects

Hnh 3.3. S khi chuyn mch lp trnh c

Vai tr ca khi l:

Kt ni hoc ngt kt ni gia cc khi logic vi nhau

Kt ni hoc ngt kt ni gia cc khi logic vi cc khi I/O bng ngn ng lp trnh.

Mng lin kt trong FPGA c cu thnh t cc ng kt ni theo hai phng ngang v ng, ty theo tng loi FPGA m cc ng kt ni c chia thnh cc nhm khc nhau, v d trong XC4000 ca Xilinx c 3 loi kt ni: ngn, di v rt di.

Cc ng kt ni c ni vi nhau thng qua cc khi chuyn mch lp trnh c (programmable switch), trong mt khi chuyn mch cha mt s lng nt chuyn lp trnh c, m bo cho cc dng lin kt phc tp khc nhau.

Cc im kt ni nh vy c gi l programmable interconnect point(PIPs).

Hnh 3.4. Cu trc PIP

Mt s kiu PIPs hay c dng:

Cross-point: kt ni ln lt cc ng kt ni theo chiu dc hoc ngang

Break-point: kt ni hoc c lp 2 ng kt ni

Decoded MUX: nhm 2^n cross-points thnh mt u ra vi n config bit

Non-decoded MUX: nhiu ng kt ni s dng chung 1 config bit

Compound cross-point: gm 6 Break-point

3.3.3.I/O Blocks

Cc khi I/O c dng kt ni FPGA vi cc thit b phn cng khc, m bo truyn v nhn d liu gia mi trng bn trong v mi trng bn ngoi FPGA.

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Hnh 3.5. Mt v d m hnh I/O cell

I/O Blocks gm nhiu I/O cell. Mi I/O cell c th cu hnh li thnh mt cng vo, mt cng ra, hoc l mt cng hai chiu. D flip-flop thng c s dng trong I/O cell cung cp vic cho ng k u vo v u ra.

3.3.4.Cc khi thit k sn

Ngoi cc khi logic ty theo cc loi FPGA khc nhau m c cc phn t tch hp thm khc nhau, v d thit k nhng ng dng SoC, trong dng Virtex 4.5 ca Xilinx c cha nhn x l PowerPC, hay trong Atmel FPSLIC tch hp nhn AVR, hay cho nhng ng dng x l tiens hiu s DSP trong FPGA c tch hp cc DSP Slide l b nhn cng tc cao, thc hin hm a*b+c

3.4.ng dng ca FPGA ng dng ca FPGA bao gm:

X l tn hiu s DSP

Tin thit k mu ASIC(ASIC prototyping)

Cc h thng iu khin trc quan, phn tch nhn dng nh, nhn dng ting ni

Mt m hc

M phng phn cng my tnh Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt c nhng bi ton phc tp m trc kia ch thc hin c nh phn mm my tnh, ngoi ra nh s lng cng logic ln m FPGA c ng dng cho nhng bi ton i hi khi lng tnh ton ln v dng trong cc h thng lm vic thi gian thc.

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4. Hng nghin cu 4.1. Hng nghin cu:

ti:

Nghin cu kit pht trin DE2i-150 FPGA v ng dng xy dng thit b nh v GPS.

4.2. L do chn ti: Cc thit b hin nay hu nh u c nhp nguyn khi t nc vi gi

thnh cao, kh nng m rng km, v cng c nhng nhng tnh nng khng s dng n.

Kit pht trin DE2i-150 vi nhng tnh nng u vit, rt ph hp thit k thit b nh v GPS cn n kh nng tnh ton nhanh v chnh xc cao.

4.2. Mc tiu nghin cu Nghin cu v hiu c cng ngh nh v GPS Thit k c thit b nh v GPS cht lng cao, mang tnh cnh tranh cao

vi gi thnh r, kh nng m rng cao h tr cho cng tc gim st, qun l giao thng

ng dng thnh cng kit DE2i-150 vi cng ngh FPGA Tp trung vo xy dng Modul GPS trong b thu GPS

4.4. Cc vn s nghin cu Cng ngh FPGA Cng ngh thu v x l tn hiu s Nguyn l nh v GPS Cch thc xy dng b x l

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Danh mc ti liu tham kho

[1]. FPGA wikipedia

http://en.wikipedia.org/wiki/Field-programmable_gate_array

[2]. Stephen Brown and Jonathan Rose,Department of Electrical and Computer

Engineering University of Toronto : Architecture of FPGAs and CPLDs: A T utorial

[3]. Bill Jason P. Tomas, Dept. of Electrical and Computer Engineering University of

Nevada Las Vegas: Introduction to Field Programmable Gate Arrays (FPGAs)

[4]. DE2i-150 Development Kit Getting Started Guide

[5]. DE2i-150 Development Kit FPGA System User Manual

[6]. VHDL-hanbook