BaBar Silicon Vertex Tracker Status and

Prospects

Adam CunhaUC Santa Barbara

for the BaBar SVT Group 7 November 2005

Vertex2005, Nikko, Japan

adamcun@slac.stanford.edu

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Outline

Overview of BaBar Overview of Silicon Vertex Tracker

(SVT) Recent SVT issues and solutions

Pedestal shift Leakage current increase in outer layers Impact of possible chip loss

SVT performance projections Conclusion

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Reconstruct CP state

Determine time between decays from vertices

Boosted Υ(4S)

l-

K-

J/ψ

KS

µ+

µ-

e- e+

B0

B0

Δz=(βγc)Δt

π+

π-

slow pion

The BaBar ExperimentScientific Objective Study CP violation in B meson decays. Over-constrain CKM quark mixing matrix.

SVT Performance Requirements Δz resolution < 130 µm (average Δz for B0 decays = 280µm). Single vertex resolution < 80 µm. Stand-alone tracking for pT < 100 MeV/c with 80-90%

efficiency.

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Cherenkov Detector (DIRC)

144 quartz barsK, separation

Electromagnetic Calorimeter6580 CsI crystals

e+ ID, and reco

Drift Chamber40 layers

Tracking + dE/dx

Instrumented Flux Return19 layers of RPCs (LSTs) and KL ID

Silicon Vertex Tracker

5 layers of double sided silicon strips

e+ [3.1 GeV]

e- [9 GeV]

The BaBar DetectorSLAC: PEPII

Collider

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5 Layers of double-sided, AC-coupled silicon 0.94 m2 of Si Φ and z strips Inner 3: Precision Vertexing Outer 2: Pattern recognition, Low Pt tracking

Custom rad-hard readout IC (the AToM chip). Low-mass design (Kevlar/carbon fiber mechanical

support)

Be Beam Pipe

Magnet

The BaBar SVT

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z-side

φ-side

Si wafersupilex fanout

Layer 1 Layer 2 Layer 3 Layer 4 Layer 5 Total

min radius 3.2 cm 4.0 cm 5.4 cm 12.4 cm 14.0 cm

modules 6 6 6 16 18 52

Si wafers 6x4=24 6x4=24 6x6=36 16x7=112

18x8=144

340

readout pitch (φ)

50 µm 55 µm 55 µm 100 µm 100 µm

readout pitch (Z)

100 µm 100 µm 100 µm 210 µm 210 µm

readout chips

144 192 240 256 288 1120

channels 18432 24576 30720 32768 36864 ~140k

SVT Modules

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HDI Readout Board

AToM Chip A Time over Threshold

Machine Time Over Threshold

Readout 128 Channels per chip Simultaneous

Acquisition Digitization Read-out

Internal charge injection for calibration

AToMChips

UpilexFanout

MountingButtons

BergConnector

5.7

mm

8.3 mm

HDI Board

AToM Chip

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CAL DAC

Shaper

ThreshDAC

CompPREAMP

TOT CounterTime Stamp

Event TimeEvent Number

Revolving Buffer

193 Bins

Si

Buffer

Buffer

Chan # Sp

ars

ifica

tion

Re

ad

ou

t Bu

ffer

CINJ

CAC

SerialData Out

15 MHz

Digitization pipeline of single channel

Inside the AToM Chip

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Specifications• Reverse-biased (50V) Si PIN diodes. • Active area 1cm x 1cm x 300µm• 2 rings (FWD/BWD) of 6 diodes • Near Layer-1 SVT electronics

Cross-section view of SVT

Details• DC coupled readout monitors total

(leakage + radiation) current• Large leakage current subtraction

with temperature corrections (thermistors)

• Trigger beam dump when acute/chronic dose rate exceeds maximum

• + 2 CVD Diamonds (new)

Purpose• Monitor accumulated dose• Protect against too high dose rates:

• Acute damage threshold: 1 krad/ms• Chronic (10min) threshold: 50 mrad/s

Radiation Monitoring (SVTRAD)

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SVT Performance and Bugeted Radiation

Damage

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SVT Performance Average hit efficiency 97% Slow pion efficiency 70% for PT>50 MeV Average zed hit resolution 10 - 40 μm

(Track-angle dependent) No radiation-induced change in

performance observed so far.

Phi side

z side

Z R

eso

luti

on

(μ

m)

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Effi

cien

cyE

ffici

en

cy

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Expected Damage to Electronics

Gain

decrease ~ 4%/Mrad

Noise increase ~ 16%/Mrad

G.C., A.Perazzo

No digital failure observed up to 5 MRads

Radiation tests were performed on the AToM chip in 2001

using 60Co sources at SLAC and using 60Co sources at LBL.

(Also tests at Elettra, mentioned later)

In the real system, the gain decreases by ~5%/Mrad, noise increases by 15-20%/Mrad

Exactly the same numbers we found with the 60Co

1 Mrad 4 Mrad Dose (Mrad)

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S/N Limit of 10 Radiation budget: 5 Mrad

Shot noise

0 2.5 5 7.5 10

0

1000

2000

3000

4000

5000

Total Noise

Noi

se (

EN

C) Total S/N

0

5

10

15

20

25

Sig

na

l/No

ise

SVT layer-1 Signal/Noise

ATOM noise

Dose (Mrad)

Limit: S/N=10

Signal to Noise Projections

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Unexpected Phenomenon

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HDI Card in horizontal plane

Th

resh

old

off

set

(cou

nts

)

Channel

Unexpected Phenomenon:Pedestal Shift

Noise pedestal (Threshold offset) started to increase Behavior associated with AToM chip location, not with

strip location Why problem? One pedestal setting per AToM chip

Chip 4

20 threshold DACs = 1fC

Ped

est

al

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Pedestal Shift (cont.) Sets in at an integrated radiation dose of 1 Mrad Correlated with most irradiated channel (note highly

non-uniform: peaked sharply in the horizontal plane). Effect reproduced at Elettra (test beam at Trieste,

Italy)

Effect reproduced @ Elettra

Channel

Del

ta T

hre

shol

d (

cou

nts

)

narrow e- beam AToM Chip

Pedestal recovers

Th

resh

old

off

set

(cou

nts

)

Integrated Radiation

1 Mrad

2 Mrad

Groups of 8 channels

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Pedestal Shift (cont.) Cause: Uneven radiation above 1 Mrad leads to

asymmetry in AToM chip electronics Solution: Adjust threshold by chip is successful

Layer 2 Module 4

10% inefficiency

level

Make threshold adjustment…

Layer 2 Module 4

…recover efficiency.

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Unexpected Phenomenon 2

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Unexpected Phenomenon:Leakage Current Increase

Since May 2004 an anomalous increase in the bias current for some modules has been observed

Only Layer-4 modules: not a simple radiation damage effect

No geometrical correlation

Consequences: increasing occupancies

300uA

10uA

Apr May Jun

I Lea

k (

A)

Days in 2004

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Leakage Current Increase

No beams

Decrease in leakage current

Beams play a role in leakage current

increase

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Leakage Current Increase

If we vary the reference potential of the metal strips (see next slide) it leads to a decrease in the leakage current

“Phenomenon is reference-voltage dependent”

Leaka

ge

Cu

rren

t

More humidity helps to stop the effect

“Humidity plays a role”

Leaka

ge C

urr

en

t

0 1 2Time (hrs)

Jan 24 Jan 25 Time

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I Lea

k (A

)

Time (hrs)

Leakage Current Increase

-20V

-20V

+20V

+20V

E

Nside

Pside

Nside

Pside

VL5-L4

=+40V

Hypothesis: Accumulation of static charge on the silicon surface. The charge is beam-induced drifts because of the field between the facing sides of different layers.

By varying the potential drop across the air between the layers we can control the effect

1800 0000 0600 1200

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Leakage Current Increase

M etal

p+ im plant

S ilicon D ioxide

n- substrate

Passivation+++++++++++++++++++++++++++++++++

Static charge on passivated surface

Charge accumulation causes an increase in the electric field at junction edge, inducing a soft junction breakdown.

Charge accumulation due to trickle injection SVT bias always on.

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Leakage Current IncreaseUsing humid air and a new

reference voltage setting, the situation now is under

control

180 μA

100 μA

1 June 05 - 1 July 05

Increased Humidity

Leaka

ge C

urr

ent

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SVT Status & Future Prospects

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short

Both noisy

2 chips masked short

Current SVT Status

Faulty AToM Chips

Forward Backward

95% of detector is fully functional: 6 out of 208 readout sections not working 300 p-stop shorts/pinholes (mainly from before 2001) 2% unbonded or otherwise dead channels Redundancy proven to be sufficient

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Radiation Dose History & Future

Dose Projections: Midplane modules will reach 5

Mrad budget in 2008 Top & Bottom modules will reach

1 Mrad in 2006 – pedestal shift

Pedestal Shift

Bottom Modules

Radiation Budget

Midplane Modules

`00 `02 `04 `06 `08

Date

`00 `02 `04 `06 `08

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Impact of Losing Chips on Physics

35.3% 34.5%

B J/s

56%51%

However, no loss of Δz precision!

Scenarios with up to all mid-plane L1-2 modules OFF:(UNREALISTIC)

Set E = 2 midplane chips OFF in L1& 2 (1/9 of L1/2 readout)

Soft

Eff

icie

ncy

(%)

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SVT has been successfully operated in BaBar since 1999

Effects of radiation damage Pedestal shift effect solved using bimonthly threshold

optimization Electronics noise/gain degradation limits detector lifetime

Rapid leakage current increase was alarming, but has been mostly reversed

Adjustable reference voltages implemented Increased humidity levels also help charge dissipation

Physics performance only slightly reduced in any realistic damage scenario.

Conclusions

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The End

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Extra Slides

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HDI MatchingCard

KaptonTail

FrontCables

Si Wafers

HDILink

DAQLink

PowerSupplies

MUXPower

BackCables

Fiber Opticto DAQ

Inside detector

Schematic of Signal Readout

HDI: High Density Interconnect. Mounting fixture and cooling for readout ICs. Kapton Tail: Flexible multi-layer circuit. Power, clock, commands, and data. Matching Card: Connects dissimilar cables. Impedance matching (passive). HDI Link: Reference signals to HDI digital common. DAQ Link: Multiplex control, demultiplex data. Electrical -- optical conversion.

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Pedestal Shift Onset

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Trickle Injection

Fill & Coast; Ramp down SVT during each injection

Trickle Injection! (began March 2004)SVT biased all the time

Lumi

LER

HER

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Occupancy Projections

Note: Electronics noise (e.g. AToM pedestal level) NOT included

Predicted from background studies at

various beam currents & luminosities.