averilogtutorial

8/7/2019 AVerilogTutorial

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Verilog & ModelSim XE Tutorial

Yeh-Juin Lin ()

[email protected]

4/23 2007


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Verilog Tutorial


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IC Design FlowRTL Model

Logic Synthesis

Gate Level Netlist

Physical Design CellLibrary


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Full Adder for Example


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Gate Level Verilog Description

// assign sum = a ^ b ^ ci;

// assign net1 = a & b;

// assign net2 = b & ci;

// assign net3 = ci & a;

// assign cout = net1 | net2 | net3;


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Behavior Level Verilog Description


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Integer & Real Numbers


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Major Data Type Nets

Registers

Parameters


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Nets Netdata type represent physical connections

between structural entities.

A netmust be driven by a driver, such as a gateor a continuous assignment.

Verilog automatically propagates new valuesonto a net when the drivers change value.


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Registers Registers represent abstract storage elements.

A register holds its value until a new value isassigned to it.

Registers are used extensively in behaviormodeling.


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Common Mistake in Choosing Data Type An input port can be driven by a net or a register,

but it can only drive a net.


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Common Mistake in Choosing Data Type An output port can be driven by a net or a

register, but it can only drive a net.


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Parameters Parameters are not variables, they are constants.

Typically parameters are used to specify delaysand width of variables.


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Structure Modeling In structural modeling, you connect components

with each other to create a more complex

component.


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Structure Modeling

module HA(a,b,sum,co);

input a, b;

output sum, co;

assign sum = a ^ b;

assign co = a & b;

endmodule

module FA(A,B,CarryIn,Sum,CarryOut);

input A, B, CarryIn;

output Cum, CarryOut;

wire sum0, sum1, co0

HA ha0(A,B,sum0,co0);

HA ha1(co0,CarryIn,sum1,CarryOut);

assign Sum = sum0 ^ sum1;endmoduleHA.v FA.v


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Delay Specification Delay specification defines the propagation

delay of that primitive gate.


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Continuous Assignments Any changes in the RHS of the continuous

assignment are evaluated and the LHS is

updates.

RHS can be

Expression

assign and_out = i1 & i2; Value

assign net_1 = 1;

Other net

assign net_a = net_b;

Example


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Operations


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Shift Operator


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Equality & Identity Operator


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Conditional Operator


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Concatenation & Replication Operator


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Procedural Assignments Procedural assignments drives values onto

register.


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Procedural Assignments A continuous assignment statement cannont be

inside procedural blocks.

A procedural assignment statement must beinside procedural blocks.


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Behavior Modeling At system level, systems functional view is more

important than implementation.

You do not have any idea about how to implementyour netlist.

The data flow of this system is analyzed,

You may need to explore different design options.

Behavior modeling enables you to describe thesystem at a high-level of abstraction.

All you need to do is to describe the behavior ofyour design.


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Behavior Modeling


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Behavior Modeling In behavior modeling, you must describe your circuits Action

How do you model your circuits behaviors? Timing control

At what time do what thing.

At what condition do what thing.

Verilog supports the following constructs to modelcircuits behavior

Procedural block

Procedural assignment

Timing control

Control statement


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Procedural Blocks

In Verilog, procedural blocks are the basic of behaviormodeling.

You can describe one behavior in one procedural block Procedural blocks are of two types

Initial procedural block Which execute only once

Always procedural block Which execute in a loop


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Procedural Blocks (Cont.)

All procedural blocks are activated at simulation time 0 With enabling condition, the block will not ne execute until the enabling

condition evaluates to TRUE

Without enabling condition, the block will be executed immediately.


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Procedural Blocks (Cont.)


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Procedural Assignment

Procedural assignments drive values or expressionsonto registers.


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Non-blocking Procedural Assignment

Blocking procedural assignment

Non-blocking procedural assignment

always@(posedge clock) begin

x = a;y = x;z = y;

end

always@(posedge clock) beginx


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Conditional Statements

If and If-Else Statement

Example


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Conditional Statements

Case Statement


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ModelSim XE Tutorial


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Install ModelSim XE Download the file

http://www.xilinx.com/ise/mxe3/mxe_3_6.2c.zipand save it on your machine.

Unzip the file.

Click on the setup.exeprogram.

Select MXE III Starter (Free)

Select Full Verilog

Setup license


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Create a Project File New Project

Add Existing File Browse


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Compile All Files

Compile All


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Compile All Files

No errors


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Simulation

1. Select your TestBench file2. Click the right button of mouse3. Simulate


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Simulation

Add signals to wave to see the waveform


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Run

1. Click Run All

2. Check the waveform to debug3. Simulation result output

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