automatic generation of hierarchical placement rules · pdf fileautomatic generation of...

Technische Universität MünchenInstitute forElectronic Design Automation

Automatic Generation ofHierarchical Placement Rules for

Analog Integrated Circuits

M. Eick, M. Strasser, H. Graeb, U. Schlichtmann

Institute for Electronic Design AutomationProf. Dr.-Ing. Ulf Schlichtmann

Technische Universität München


Overview

• Motivation: analog placement constraints• Generation of hierarchical placement rules• Experimental results

– Comparison with industrial tool– Fully differential amplifier

• Conclusion

2


Constraints in Design Flow

3

specification

structure

sizing

placement

routing

analog block

sizing constraints

placement constraints

routing constraints

process variations,parasitic devices etc.

layout

manual

mostlyautomated

mostly manual


Placement Constraints – Device Matching

4

• Device matching: equal electrical properties

• Sources of mismatch, e.g.,− Distance effects

(temperature, oxide thickness, ...)− Orientation effects

(μ0, skewed doping, ...)• Countermeasures− Same variant and orientation− Parallel connections instead of larger

transistors− Spatial proximity

• Common centroid

same variant

common centroid

[Hastings: The Art of Analog Layout’01]


Placement Constraints - Symmetry

5

differential circuits: symmetrical behavior

device matching“symmetrical” routing requires

“symmetrical” placement

In Ip

Op On

[Cohn et al.: Analog Device-Level Layout Automation’94]


State of the Art

• Sensitivity analysis– Parasitic devices → matching, symmetry

[Malavasi et al. TCAD’96]– Net sensitivities → matching [Chen et al. IEE Proc. G’92]

• Graph isomorphism→ symmetry[Kole et al. ISCAS’94] [Hao et al. ICCCS’04]

• Building blocks→ matching (sizing) [Massier et al. TCAD’08]• Retargeting using hierarchical symmetry

[Bhattacharya et al. ASP-DAC’04]• Circuit hierarchy not considered

– Possibly missing constraints– Infeasible for hierarchical placement

6


Hierarchical Placement

7

Group 5

Group 4

Group 3Group 2Group 1

• Plantage [Strasser et al., ICCAD’08]

• Placement generation controlled by inherent hierarchy

• Placement constraints within and among groups− Matching− Symmetry− Proximity

• Similar approach: [Lin et al., DAC’08]

hierarchy tree


Overview



• Conclusion

8


Flow Chart of New Approach

9

netlist building blocks symmetry


Automatic Structure Analysis

• Structure recognition− Comparison with building

blocks from library− Resolution of ambiguities− [Massier et al. TCAD’08]

• Symmetry analysis− Propagation of symmetry-

pairs starting from differential pair

− similar to [Arsintescu et al. ICCD’96]

simple current mirror

differential pair

simple current mirror

10


Flow Chart of New Approach

11


constraint graph

constraint graph(netlist)

constraint graph(building blocks)

constraint graph(symmetry)


Constraint Graph (Symmetry)

12


c

• Symmetry pair→matching constraint (symmetry)

devicecoordinates

axis coordinate

• Symmetry pairs (d,d‘) of same axis → symmetry constraint


Constraint Graph (Symmetry)

13


• Symmetry pair→ matching constraint (symmetry)

• Symmetry pairs (d,d‘) of same axis → symmetry constraint

• Elimination of → complete graph

devicecoordinates

axis coordinate


Constraint Graph

14

constraint graph (building blocks)

constraint graph (netlist) constraint graph (symmetry)

constraint graph

proximity constraint

matching constraint

matching constraint

symmetry constraint


Flow Chart

15


constraint graph

hierarchical placement rules

constraint graph(netlist)

constraint graph(building blocks)



Conflict Avoidance

• Priority order TI:1. Matching constraints

(symmetry)2. Matching constraints

(building blocks)3. Proximity constraints

(building blocks)4. Symmetry constraints5. Proximity constraints

(netlist) • Criteria, e.g., differential principle

16


Hierarchy Generation

17

MGS3MGS1 MGS2

SG1

MGB1

PGN1

MGS1

MGS3

MGS2MGB1

SG1

• Controlled by priority order TI:1. Matching constraints

(symmetry)2. Matching constraints

(building blocks)3. Proximity constraints

(building blocks)4. Symmetry constraints5. Proximity constraints

(netlist) • MGS/B: Matching group

(symmetry / building blocks)• SG: Symmetry group• PGN: Proximity group (netlist)

PGN1


Overview



• Conclusion

18


Hierarchy Generation

19

Circuit Number oftransistors

Groups Runtime[s]Number Size

Miller1 9 5 2 – 4 (Ø 2,6) 0,14Example 10 8 2 – 4 (Ø 2,5) 0,17Fully Differential OTA2 30 19 2 – 5 (Ø 2,5) 0,46Folded Cascode OTA1 22 17 2 – 3 (Ø 2,2) 0,31Buffer3 42 21 2 – 14 (Ø 2,9) 0,65

1 [Laker, Sansen: Design of Analog Integrated Circuits 94]2 [Galdi et al. JSSC’08], 3 [Fisher et al. JSSC’ 87]

• Runtime of placer ~ group size


Comparison with Cadence Virtuoso

20

0

10

20

30

40

50

60

I N I N I N I N I N

Num

ber o

f Con

stra

ints

Miller Example FD OTA FC OTA Buffer

I: Cadence Virtuoso Schematic Editor XL; N: New approach

Constraintscluster (hierarchical)symmetry (pairs)cluster (devices)same variantalignment


Experimental Set-up

21

sized schematic of fully differential ota

hierarchical placement using Plantage [Strasser et al.; ICCAD’08]

parasitics extraction (Cadence Assura)

post layout simulation (Cadence Spectre)

industrial tool:Circuit Prospector of

Cadence Virtuoso Schematic Editor

new approach

automatic routing (Cadence Chip Assembly Router)

unco

nstra

ined


22

[Galdi & al., JSSC’08]

differential pair

current mirrors

Schematic of Fully Differential OTA


Hierarchical Placement Rules of FD OTA

23

MG

S1

N1

N2

P11

P14

P12

P15

P13

P16 P8

P9

P10 P4

P7

P1

P2

P3

P5

P6

N6

N9

N5

N7

N8

N11

N12

N14 N

3N

4N

10

MG

S2

MG

S3

MG

S4

MG

S5

MG

S6

MG

S7

MG

S8

MG

S9

MG

S10

N13

MGB1 MGB2 MGB3 MGB4 MGB5 MGB6

PGB1

SG1

PGN1differential pair

current mirrors

MGS/B: Matching group (symmetry / building blocks); SG: Symmetry group; PGB/N: Proximity group (building blocks / netlist)


Layout and Post Layout Simulation

24

perfor-mance un

cons

tr-

aine

d

indu

stria

l

new

appr

oach

A0 [dB] 72 72 72f0 [MHz] 22 22 22Voffset [μV] 140 93 -6.6CMRR [dB] 78 76 110

differential pair current mirrors

Post layout simulation

placementconstraints


Conclusion

• Generation of hierarchical placement rules– Structure and symmetry analysis– Assignment of constraints to constraint graph– Generation of hierarchical groups– Constraints within and among groups:

matching, symmetry, proximity• Experimental results

– Feasible for hierarchical placement approaches– Comprehensive constraint generation– Improved post layout performance

25

Thank you!


26


Constraint Assignment (Netlist)

27

• Connections → proximity constraints (netlist)

• Beneficial for routing

Constraint Requirement Graph(Netlist)

Nodes = Devices

Edges = Constraint RequirementsHere: Proximity Constraint (Netlist)


Constraint Assignment (Building Blocks)

28

Requirement Graph(Building Blocks)

• Two transistor blocks → matching constraints (building blocks)

• Larger blocks: additionalproximity constraint (building block)


Conflict Avoidance

Priority order TI:

Criteria:

29

5. Proximity constr. (netlist) 4. Symmetry constr.3. Proximity constr. (building b.)2. Matching constr. (building b.)1. Matching constr. (symmetry)

• Differential principle• Increasing size


Generated Placement

30

Placement Constraints:

alignmentcommon centroid

symmetry axis

group

differential pair

current mirrors


31Enumeration of placements of fundamental module sets

Hierarchically Bounded Enumeration

M5 M6 M7CM

M1 M2DP

M3 M4CM

DSCORE

OPAM8 C

Fundamentalmodule sets

M5

M6 M7M5

M6

M7M5

M6M7…

M3 M4

M3

M4M3

M4

…

M8

CM8

C

M8

C

…

M1aM2a

M2bM1b

…M

2aM

1a

M1b

M2b

M5 M6 M7CM

M1 M2DP

M3 M4CM

DSCORE

OPAM8 C


32

Enhanced Shape Functions

M5 M6 M7CM

M1 M2DP

M3 M4CM

DS

COREOPA

M8 C

M5

M6 M7M5

M6

M7M5

M6M7…

M3 M4

M3

M4M3

M4

…

M8

CM8

C

M8

C

…

M1aM2a

M2bM1b

…M

2aM

1a

M1b

M2b

• Hierarchical approach• Good for semi-automatic

layout generation• High flexibility• Enhanced shape function

for each node of hierarchy• Close proximity of modules

is achieved by hierarchy

Enhanced Shape Functions

Enhanced Shape Addition

automatic generation of hierarchical placement rules · pdf fileautomatic generation of...

Documents