at94 training 2001slide 1 at40k10 at40k20 at40k40 at40k80...

AT94 Training 2001Slide 1

AT40K10AT40K10

AT40K20AT40K20

AT40K40AT40K40

AT40K80AT40K80

5K-10K5K-10K

10K-20K10K-20K

20K-30K20K-30K

40K-50K40K-50K

80K-100K80K-100K

125K-150K125K-150K

256256

576576

1,0241,024

2,3042,304

4,0964,096

6,4006,400

AT40K Family w/ FreeRAM AT40K Family w/ FreeRAM TMTM

PIN

OU

T C

OM

PA

TIB

ILIT

YP

INO

UT

CO

MP

AT

IBIL

ITY

DD Q

CLK

RESET

Q

SET

Gates

Registers

128128

192192

256256

384384

512512

640640

I/Os

5Volt/ 3.3Volt5Volt/ 3.3VoltCom / Ind TempCom / Ind TempPCI-CompliantPCI-Compliant

Specs/Pkgs

CLEAR

LOAD

FreeRAMTM

AT40K125AT40K125

AT40K05AT40K05

2,0482,048

4,6084,608

8,1928,192

18,43218,432

32,76832,768

51,20051,200

84 - PLCC100 - VQFP144- TQFP160 - PQFP208 - PQFP225 - BGA240 - PQFP304 -PQFP352 - BGA


Proven AT40K FPGA Technology

• SRAM based technology

• LUT cell based

• Distributed SRAM blocksFreeRamTm from 4.6K – 18.4K bits

• Fully symmetrical architecture

• Partial/Dynamic reconfiguration

• Family of AT40K05/10/20/40 in production for more than 3 years

• Tools/application notes/ IPs available.

FPSLIC- Embedded FPGA Core


FPGA Core Overview

Distributed FPGA RAM

I/O

Repeaters

CoreCells

>> Patented RAM can reduce FPGA size requirements by >50%

Interface to

AVR and SRAM


FPGA Cell to Bus Connections

• Each Cell input can be connected to a local bus

• Each Cell output can be connected to a local bus

• 5 Local buses horizontally per sector row

• 5 local buses vertically per sector column

cell

cell

cell

cell


cell cell

cell cell

cell cell

cell

cell

cell

Cell to Cell Direct Connections

• Each Cell connects to 8 nearest neighbors

• Each Cell has 4 orthogonal connections

• Each Cell has 4 diagonal connections


X3Y0 X2Y0 X1Y0 X0Y0

X3Y1 X2Y1 X1Y1 X0Y1

X3Y3 X2Y2 X1Y2 X0Y2

X3Y3 X2Y3 X1Y3 X0Y3

X3 X2 X1 X0

Pi Ci

Ci+1

Pi+1

Y0

Y1

Y2

Y3

P7 P6 P5 P4 P3 P2 P1 P0

+

Pi

Ci Xi

Yi

Ci+1

Pi+1

Array Multipliers

Parallel Multiplier Cell

>> Key to High-Performance Processing


FPGA Core CellNW NE SE SW"1" N S E W"1"

8x1 LUT

a0a1a2

out

8x1 LUT

a0 a1 a2

out

"1""0""1"

Z

CLOCKRESET or SET

0 1

D

Q

NW NE SE SW N E S W

"1" OEH OEV

"1"

X W Y

Z(L) X(L) W(L) Y(L)

V1

H1

V2

H2

V3

H3

V4

H4

V5

H5

X Y

1-X3-W 2-Y

4-Z

Cell Inputs Highlighted in italics

5-OEFeedback


Sample AT40K Core Cell ‘Modes’

‘Arithmetic’ Mode ‘Synthesis’ Mode

‘DSP’ Mode ‘Network’ Muxing Mode

ABCIN

Full Adder/Counter

Sum

Carry

AB

CINMultiplier Cell

Carry

Product

A

AB

Select

Switches

BCD

Reg4

LU

T

3 L

UT

3 L

UT

PPSI

LU

T 3

LU

T 3

Logic Out

Enable

OUT

2:1

MU

X

Random Logic

Reg

Reg


AT40K Key Features DSP

Atmel Features:

Core cell ‘up-stream’AND gate give 1 multiplier ‘tile’ percore cell.

Diagonal andOrthogonal core cellconnection mean nobussing resource consumed to make array multiplier

AT40K 4 X 4 arraymultiplier16 core cells

Xilinx 4K series requires 12CLBs to create a 4 x 4 arraymultiplier.

Each CLB is equivalent to 2 Atmel core cells which meansa Xilinx 4 x 4 array multiplieris equivalent to 24 Atmel core cells.

Xilinx does not have diagonal direct connects so they also consume a large number ofbus resources to do multiplier.

CLB CLB

CLBCLB

cell

cell

cell

cell

AtmelDiagonaldirectconnection

Xilinx needtwo busesto make aDiagonal


FPGA SRAM

• 32 X 4 Ram in corner of each sector

• Ram can be sync or async

• Ram can be single or dual ported

• Ram can be reset via configuration

• Ram can operate at 100MHz

• Data and address come from local and express bus connections

32x4 RAM

Din Dout

WAddr RAddr

WE

OE

Dedicated SRAMrouting resource

cell cellcell cell

cell cellcell cell

cell cellcell cell

cell cellcell cell


AT40K Key Features FreeRAMAtmel Features:

Distributed SRAM“FreeRAM”

Fast 10ns access time

Fully ProgrammableSingle or Dual portSynch or Async

Using RAM does not use core cells

Xilinx 4K series has 16 x 1Dual port Ram in each CLB32 x 4 Dual port RAM is 8 CLBs and each Xilinx CLBis 2 X an Atmel core cell.

A Xilinx 32 X 4 Dual port RAMconsumes the equivalent of16 Atmel core cells !!!!

With AT40K the RAM is FREE 32x 4 bits of Dual port RAM


FCF 7/10/96

AT40KMacro: 128X8Dual-Ported RAM

Atmel CONFIDENTIAL

2-to-4Decoder

WriteAddress

Din(0)

Din(1)

Din(2)

Din(3)

Din(4)

Din(5)

Din(6)

Din(7)

Dout(0)

Dout(1)

Dout(2)

Dout(3)

Dout(4)

Dout(5)

Dout(6)

Dout(7)

ReadAddress

WE

2-to-4Decoder

Din Dout

WEOE

RAddr WAddr

Din Dout Din Dout

WEOE

Din Dout

WAddr RAddr

WEOE

RAddr WAddr

WEOE

WAddr RAddr

Din Dout

WAddr RAddr

WE

OE

Din Dout

WE

OE

RAddr WAddr

Din Dout

WAddr RAddr

WE

OE

Din Dout

WE

OE

RAddr WAddr

2-to-4Decoder

WriteAddress

Din(0)

Din(1)

Din(2)

Din(3)

Din(4)

Din(5)

Din(6)

Din(7)

Dout(0)

Dout(1)

Dout(2)

Dout(3)

Dout(4)

Dout(5)

Dout(6)

Dout(7)

ReadAddress

WE

2-to-4Decoder

Din Dout

WE

OE

RAddr WAddr

Din Dout Din Dout

WE

OE

Din Dout

WAddr RAddr

WE

OE

RAddr WAddr

WE

OE

WAddr RAddr

Din Dout

WAddr RAddr

WE

OE

Din Dout

WE

OE

RAddr WAddr

Din Dout

WAddr RAddr

WE

OE

Din Dout

WE

OE

RAddr WAddr


"0"

"0"

AT40K Clocking Scheme

• Individual Clock per sector column• Clock and Clock BAR at sector boundary• Column Clock can be any one of 8 Global

clocks• Clock from Column Clock or Express Bus• 4 Fast Clocks (2 per side for PCI spec)• Low power tie-off


"0"

"0"

AT40K Reset Scheme

• Individual reset per Sector column• Reset and Reset BAR• Any device pin can be designated as reset• Reset from Global Reset or Express Bus• Each D Flip-Flop can be Set or Reset


FPGA Primary I/O

• I/O interfaces to core cell

• I/O connects into repeaters on row above and row below

• Programmable input delay

• CMOS/TTL input levels

• Pull-up or pull-down resistor

• Open source/drain output

• System friendly bus keeper

>> Supports Pin-Locking!

"0"

"1"

DR

IVE

TR

I-S

TAT

E

"0"

"1"

TT

L/C

MO

S

SC

HM

ITT

DE

LAY

PULL-DOWN

PULL-UP

GN

DV

CC

PAD

CELL

CELL

CELL

ICLK R

ST

RS

T

0CLK


cell cellcell cell

cell cellcell cell

cell cellcell cell

PP

SS

PP PP PP PP

PP PP PP PP

PP PP PP PP

SS SS SS SS

SS SS SS SS

AT40K Key Features Pin Locking

Unique I/O bus connections mean that pin locking problems are virtually eliminated1 Primary I/O connects to 12 core cells & 1 Secondary I/O connects to 8 core cells

AT40K ‘Lock-it and Leave-it’tm I/O structure


FPGA Designs

•IDS supports Schematic, VHDL or Verilog Design Entry•It generates a BST file for programming the Configurator

AT40K FPGA

AT17

Figaro IDS

FPGA Development Tools


HDLPlanner™

• Technology independent design entry• Enhances design re-use• Shorter design cycle• Supports Verilog & VHDL• Syntax correct templates • Support for macro generators• Context highlighting• Seamless interface to synthesis • Integrate user defined components• Knowledge archival

FPGA HDLPlanner™


Push Button IP - Macro Generators

Macro Generators

• Hard or Soft Layouts• Parameterizable• Auto HDL generation• Auto Schematic Generation• Auto Simulation Model• Power Calculation• Area Calculation• Post Layout Performance• Architecture Optimized• Open development lang..• Auto insertion of pipelining• Supports Logic & Memory


Exemplar Leonardo Spectrum HDL Synthesis

• Easy to use• Fast RTL Optimization• Produces the best

results• Integrated RTL to P&R


ModelSim HDLSimulation

• Committed to HDL Simulation Leadership

• Quick Compilation• Fast Simulation• Ease-of-Use• Full debug at any

level


FPSLIC-FPGA Development Software


• Push Button 85%+ APR• XNF/EDF/WIR Import• Hierarchy Browser• Architecture Mapping• Multi-Chip Partitioning• Floor planner• Bitstream Utilities• Incremental Design Change• Export VHDL/Verilog netlists• Back Annotation support• Extensive interactive help.


FPSLIC-FPGA Development Software


• User Library Management• Enhances Design re-use• Interactive Layout Editor • Timing Driven Design• Graphical Constraint Entry• Multi Cycle Clk Constraint• Async. Path Delay Constraint• Static Timing Analysis• Interactive Timing Analysis

at94 training 2001slide 1 at40k10 at40k20 at40k40 at40k80...

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