assignment iii eeeb163 fsm

8/18/2019 Assignment III Eeeb163 Fsm

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Assignment EEEB163 #1

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ID :

Section No :

1. An MN flip-flop function table and a state diagram (Figure 3b of an s!nc"ronous s!stem are

pro#ided belo$. %eali&e t"e s!stem b! using t"e MN flip-flop $it" additional logic gates.

S"o$ clearl! t"e follo$ing items in !our design:

(i 'ransition)*citation table ( + mar,s

(ii State 'able for t"e seuential circuit $it" flip-flop input ( mar,s

(iii Input and /utput euations (10 mar,s(i# Dra$ t"e circuit ( mar,s

Figure 3b : MN flip-flop function table and a state diagram

Input /utput

M N 2loc, 0 0 4 05

0 1 4 1

1 0 4 0

1 1 4 0


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1. A 3-bit s!nc"ronous counter can perform eit"er counting up or do$n. 6se t"ree ' flip-flops as

main components to implement it.

a Dra$ its bloc, diagram $it" inputs and outputs appropriatel! labelled. (+ mar,s

b Dra$ its ne*t state table. (7 mar,s

c Find ne*t state euation for t"e middle bit flip-flop. (3 mar,s

d Assume t"e counter is initiall! 80009 dra$ its timing diagram up to ; cloc, c!cles for

counting-up. Do not forget to include t"e cloc, signal as $ell in !our diagram.

(<

mar,s


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Section No :

1. 6se t"ree ' flip-flops as main components to implement a 3-bit s!nc"ronous counter t"at can

count-up to si*. In ot"er $ord counter restarts to count up from &ero $"en si* is reac"ed.

i. Dra$ t"e ne*t state table for t"e counter => mar,s?

ii. Dra$ @-Maps and t"en use t"em to find t"e ne*t state euations: '0 =< mar,s?

'1 =< mar,s?

'+ =< mar,s?

iii. Dra$ a complete circuit to s"o$ "o$ t"e t"ree ' flip-flop are interconnected and label it

appropriatel!. =< mar,s?

i#. If freuenc! of t"e cloc, is 1 @B& estimate output freuenc! of t"e "ig"est order 'FF.

=

mar,s?


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assignment iii eeeb163 fsm

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