Assembly and Reliability of a Wafer Level CSPParvez M Patel,

MotorolaLibertyville, IL 60048

W18315@email.mot.comAnthony Primavera, PhDUniversal Instruments Corporation,

Binghamton, NY.primaver@uic.comK. Srihari, PhD

Professor – State University of New York – Binghamton,Binghamton, NY.

srihari@binghamton.edu

INTRODUCTION

Many of the CSPs in production today are presently beingmanufactured by the extension of the conventional packagemanufacturing techniques. Individual chips are attached to abase support substrate, such as a lead frame or a substrate,connecting the die pads to solder contacts used for the nextlevel assembly. Electrical contacts between the chip and thecarrier package can be made either by wire-bonding, tapeautomated bonding, or by flip-chip methods. A significantadvantage of the chip-size package is that it can be madedirectly on the wafer, since each CSP covers only itsindividual chip site. Using this approach, each “package” isassembled to the corresponding IC while still on the wafer.The ICs can be burned-in and tested before being diced intoindividual, fully furnished packages. The definition of a truewafer-level packaging solution has been expanded to includepackages that:

• use material and equipment that process diesimultaneously on the wafer;

• are not dependent on layer fabrication off-line, orindividual placement and connection of features;

• use equipment and processes consistent withstandard semi-conductor processing;

• allow for wafer-level burn-in and test strategies.

Other advantages include:• elimination of different redistribution and stack-up

layers by a single layer of polyimide or any otherdielectric;

• the process is independent of the fabrication oflayers off-line, such as flex films, or the individualplacement and connection of features;

• the process steps assure quick turn-over for newdesigns, as well as the ability to rapidly adapt tochanges, such as die shrinkage [Juskey, 1998];

• wafer-level packaging eliminates risks of supplyissues with a flex film, and the attendant inventoryand scrap costs that this incurs during designchanges or a product’s end of life [Elenius, 1999];

• in comparison to flip chip packages, the wafer-level CSPs provide equivalent size andperformance, while retaining the advantages of anSMT package [DiStefano, 1997].

• wafer-level CSPs can be more easily burned-in andtested;

• by using wafer-level CSPs, peripheral arrays with adense bump pitch can be redistributed to full areaarrays with a more convenient bump pitch withoutusing an intermediate substrate.

Currently, there are more than a dozen wafer-level CSPsavailable in the market. Some of the well-known onesinclude Flip Chip Technology’s Ultra CSPTM, NationalSemiconductor’s MicroSMD, Fujitsu’s Super CSP,ShellCase’s Shell CSP, Amkor Anam’s wsCSPTM, Tessera’sWafer level µBGA, Mitsubishi Electric’s Molded CSP, andSandia National Laboratories’s Mini BGA.

RELIABILITY OF WAFER -CSPS

The reliability of the wafer-level CSP is dependent on thestructure of the package. Compared to conventional CSPs, thewafer-level CSPs have fewer problems such as pop-corning,die-substrate de-lamination, and other moisture-induceddefects. The failure mode in CSPs during accelerated thermalcycling is affected by the construction of the package and thetemperature extremes. The package can fail internally (withinthe package such as wire-bond, redistribution traces, tapes,leads, etc.) or due to solder fatigue.

The reliability data available in the industry is highlyconfusing. [Gaffarian, 1999], reports that wafer-levelassemblies often show very few cycles to failure, and most ofthem require underfilling to achieve reliability comparable toconventional mounted packages. Reliability data on theSandia MiniBGATM package for the 0 to 1000C thermal cycleregime was found to be > 2000 cycles with underfill and lessthan 40 cycles without underfilling [Chanchani, et al., 1997].Test results indicated (>1000 cycles) solder joint reliability ofthe Amkor Anam wsCSPTM format [www.amkor.com]. TheµSMD from National Semiconductor Devices is reported tohave passed 2300 cycles at the 0 to 1000C thermal cycles[Nguyen, et al., 1998].

The Tessera wafer-level µBGA package is built on multi-layerpolyimide flex, supported by a layer of compliantencapsulation. The wiring layers are connected to the pads on

the chip by flexible bond ribbons embedded in the compliantmaterial [DeStefanio, 1997]. Reliability is claimed to be highbecause of the flexible ribbon bonds that allow thermalexpansion without damaging the solder attachment to theboard. A number of results have shown that the µBGApackage fails at a very low number of cycles, with the failuresmost likely occurring at the bonding pad [Wang, et al. 1998].

The package that has been used for our evaluation – PackageA is different from other conventional CSPs in that PackageA does not employ an interposer between the IC and thesolder ball array. The assembly of the device to the boardrequires the assembler to follow specific rules to achieveoptimal reliability, because the stress is taken up within thesolder interconnection itself [Barrett, et al., 1998]. Since theintermediate substrate is absent in most of the wafer-levelCSPs, the CTE of the package is significantly less thanmolded devices. Wafer-level CSPs combined with lowstandoff offer an unfavorable combination with respect tothermal reliability [Partridge, 1999].

Board level reliability of similar wafer level CSPs has beenevaluated and published. Thermal cycle reliability testing ofthese packages has shown the ability to pass > 1000 cycles of0 to 1000C and > 500 cycles for the –40 to +1250C. In all thecases, the failure mode of the package joints has been solderjoint fatigue [Barrett, et al., 1998].

PACKAGE A - DESCRIPTION

The daisy chained parts (Package A) used for the assemblyexperiments do not have an interposer nor does it requireunderfill. The pads are routed to JEDEC standard pitchesusing CSP-size balls on the re-routed pads. This device isideally meant for memory devices such as flash memory,DRAM, EEPROM, SRAM, and integrated passives in avariety of applications.

Package A is a true wafer level package as it uses standardsemiconductor processing equipment to produce a thin-filmredistribution layer and a wafer-level ball attach technology.The package uses a two-layer polymer dielectric system ofBenzocyclobutene (BCB) and a thin film solderableredistribution layer of Al/NiV/Cu. The use of the thin filmallows the use of a single metal layer for both theredistribution trace as well as the under bump metallization.BCB was chosen because it is compatible with coppermetallization and has excellent resistance to moisture andchemicals [Elenius, 1999]. The total thin film thickness isapproximately 10 microns. The thin-film redistribution layerconstruction consists of the following [www. flipchip.com]:

• Dielectric layer 1 for passivation and planarizationof the die passivation (when redistribution isrequired);

• Al/NiV/Cu, a thin-film layer that is sputtered andthen etched to form the trace and UBM pad;

• Dielectric layer 2 for passivation of theredistribution wiring and definition of thesolderable area for the ball.

A standard ball attach process of fluxing, ball placement, andreflow is used for attaching the solder balls. Because the I/Opitches are standard, the only design limits with Package Aare size of the die and the number of I/Os; for a larger diewith big I/O there is a limit to the number of rows that can beredistributed. In cases of higher I/O count chips, it is oftenmore cost effective to use a standard flip chip device [Elenius,1999]. Thus, the package is a transition package between aCSP and flip chip.

Package A has 46 solder bumps distributed in an area array (6by 8 pattern), depopulated at the center. The package isrectangular in shape with physical dimensions of 317*246mils and a thickness of 43.8 mils (from the top of the die totip of the bump). The silicon has an overall thickness of 27mils and is attached to a flex layer with a thickness of 0.3mils. The solder bumps have a mean diameter of 21.5 milsand a height of 16.5 mils. The package construction detailsare shown in Figure 1.

Figure 1: Package Construction Details

TEST PLAN

The main objective of the experiment were:• To investigate and study the assembly issues concerning

the wafer level CSP, Package A;• To study the effect of using solder paste and flux on

solder joint reliability;• Assemble Package A on via-in-pad land patterns and

compare the solder joint integrity on the via-in-padconnections with conventional NSMD pad connections;

• To study the effect of varying pad diameters on thesolder joint strength for both the conventional and thevia-in-pad structures.

A total of 96 packages were assembled on the test board. Ofthese, half were built using flux and the other half with solderpaste. Nitrogen was used as the reflow atmosphere as itincreases the wettability and reduces the chances of voids inthe solder joint [Primavera, 1998]. For comparison, PackageA was built on conventional Non Solder Mask Defined

(NSMD) pads and the via-in-pad design pads having NSMDgeometry (Figure 2). Both the via-in-pad and the conventionalpads had three levels of pad diameters available: 11 mils, 13mils and 15 mils. Prior to assembly, the boards werecharacterized and documented. Table 1 shows the designvalues of pads and vias for the different sites assembled.

Figure 2: Via-in-Pad and Conventional Pad

Solder Paste

No-clean, Type IV, eutectic solder paste with a 90% metalcontent was used. Prior to use, the solder paste jars werekept in a running water bath at around 250C for 4 hours. Thepaste was then thinned by stirring it using a spatula. The pastebead diameter on the stencil was maintained at approximatelyone-inch.

Flux

Flux was applied to components before placement using theThin Film Applicator (TFA). The TFA device is attached tothe placement machine and is used to apply small andrepeatable amounts of flux to solder balls on components. Ithas a rotating drum which has a flat top, coated with a thin,uniform film of flux. A fixed blade (doctor blade) maintainedthe thickness of the flux film. Before placement, thecomponent was placed onto the drum surface by the pick andplace machine, causing flux to transfer to the solder balls. Themachine waits for 150 milliseconds before picking thecomponent off the film and placing it onto the PCB. Thethickness of the flux film applied was maintained at 4.5 mils.

ASSEMBLY

The assembly process was done in two parts; the firstinvolved the assembly of packages using solder paste whilethe latter half was done using flux. The assembly processinvolved the following process steps:

Board cleaning - Solder paste printing / fluxing - Printinspection - Component placement – Reflow - Electricalcircuit test - X-ray inspection.

Prior to assembly, all the boards were visually examined toobserve any defects such as debris, fingerprints,contamination, etc. The components assembled were baked at1250C for about 12 hours prior to assembly to drive away anymoisture that could lead to defects. Representative packageswere examined using x-ray for voids or any other defects.

A fully automatic stencil printer was used for printing solderpaste onto the boards. Polyurethane, 9” long squeegees with adurometer of 95 on the Shore A scale were used for theprinting operation. The squeegee angle was maintained at 600.

A 5-mil thick, laser cut, stainless steel stencil was used for theprinting operation. The stencil was characterized in terms ofits aperture size openings. Before the solder paste wasdeposited onto the experimental boards, it was thawed andkneaded to attain a homogeneous mixture with uniformviscosity. A few set-up boards were first printed in bothdirections in order to stabilize the process. After attaining therequired print quality, the experimental boards were printed.Visual inspection with an optical microscope was used todetermine the quality of the print deposits. Print parametersused for the build are:Print Pressure – 0.49 kg/linear inch;Print Speed – 15 mm/sec;Print Gap – On contact;Separation Speed - 0.3 mm/sec;Strokes – 1;Stencil Wipe – 3 prints;Squeegees – Polyurethane 9 inches - 95 durometer;

A flexible and highly accurate placement machine was usedfor placing the components on the board. The componentswere picked from matrix tray feeders and placement andreflow were performed using an inline board handling system.The same program, with minor modifications, was used forboth the solder paste and the flux assemblies.A forced nitrogen convection oven was used for reflow andsoldering of the assembled components as shown in Figure 3.

This profile is designed to ramp up to 1650C at a rate of1.50C/second. The recipe holds the dwell temperatureat 1650C for approximately 140 seconds. This dwellzone starts with the solvent evaporation followed by theactivation of the flux. Flux activation reduces oxides onthe solder bumps and cleans the pads. After this, theboard temperature is quickly raised to 2200C in 20seconds. Once peak temperature is attained, the boardis cooled to 850C (exit temperature). The time that theassembly is at the maximum temperature of the reflowsystem was limited to approximately 30 to 50 seconds,depending upon the thermal mass of the assembly. Areduced oxygen atmosphere was used throughout thereflow operation. Oxygen content of less than 50 ppmwas maintained using nitrogen gas.

Figure 3: Reflow Profile Used

OBSERVATIONS AND ANALYSIS

Inspection of the paste deposits indicated good print qualityin terms of paste registration and print definition. The solderdeposits were photographed for documentation. Theassembled packages were monitored using an edge fingerconnector region on the board. Probe testing of theassemblies showed that all the solder joints were electricallygood. X-ray evaluation did not show any solder bridging orsolder balling defects. However, the assemblies showedpresence of voids in the via-in-pad solder joints. The voidswere found to be present for both the cases of solder paste andflux assemblies and were distributed on and around viaopenings. Some of the voids in the via-in-pad solder jointswere located right above the via opening and were difficult todetect during x-ray evaluation.Cross sectioning of representative assemblies was done tostudy solder joint quality, component standoff, wetting ofpads, and the presence of any defects like voids, micro cracks,and insufficient wetting. Figures 4a and 4b are cross-sectionsof packages assembled on conventional and the via-in-padstructures using solder paste. The solder joints on theconventional pads showed excellent wetting and solder jointshape. For the via-in-pad joints, voids were seen at theentrance of the vias in most of the solder joints. These voidswere as big as the via diameter. Note that even for thecomponents assembled using flux, the solder joints showedthe presence of voids above the via. Some solder jointshowever, showed the presence of voids towards thecomponent side (Figure 4b).

Figure 4: Solder Joint Cross-Sections

These were few in number as compared to the ones that hadvoids towards the board side, just above the via opening. Thepresence of voids could be due to a number of reasons:

• improper reflow profile,• entrapment of air/gases,• contamination of soldering surfaces [Sturm, 1996].

Past research has shown that the failure of second level solderjoints was mainly towards the component side. [Primavera,1999.] Thus, the presence of a void at the component sidemight help crack propagation and reduce solder jointreliability.

There was a noticeable trend in increase in standoff as the paddiameter decreased for flux assemblies. As the pad diameterdecreases, the amount of solderable pad area decreases, thus,the amount of collapse of the solder bump is different forthese pad diameters. For the solder paste assemblies, as thepad diameter decreases, the amount of solder paste depositedalso decreases; thus, there is no significant decrease instandoff (Figure 5). Standoff values were measured using alaser profilometer and by cross sectional analysis.

Figure 5: Measured Stand-Off

RELIABILITY ANALYSIS

Reliability of an electronic assembly or an individualcomponent is "the ability to function for an expected periodof time without exceeding an expected acceptable failureprobability". Accelerated testing is one of the more commonmethods that are used to test the reliability of electroniccomponents. The goal is to accelerate the time-dependentwear out failure mechanism and the accumulation of damagethat reduces the time to failure. The samples that wereassembled were subject to air-to-air thermal cycling using a20 minute 00C to 1000C cycle with a 5 minute dwell and a 5minute ramp. Continuous electrical monitoring of theassemblies was done during cycling to find out the exactfailure cycle. Data acquisition and storage were done byusing an event detector and Datalog software. The resistancethreshold was preset at 300 Ω. If the coupon overshot thisvalue, an event was reported. (An assembly was said to havefailed at a particular cycle ‘n’, if it is open for 10 cyclesbetween cycle number ‘n’ and cycle number 1.1n, beginningat cycle ‘n’). Once a package was found to have failed, it waselectrically probed to locate the failed joints and then anelectrical mapping of the failure joint location was done.Cross sectioning was carried out, and the sections wereexamined using a metallographic microscope.

Data analysis was done using lognormal and Weibull testing(2-parameter, 3-parameter, Bi-Weibull). The cycles to failure

SOLDERFLUX

Observed Standoff

PCB Pad Diameter (mils)

Stan

doff

(mils

)

11.6

11.8

12.0

12.2

12.4

12.6

12.8

13.0

13.2

13.4

11 mil Pad 13 mil Pad 15 mil Pad

data was fitted to a 2P Weibull distribution using WinSmithWeibull software. The failure data underwent the followinghypothesis:

• The reliability of the assemblies on the conventionalpad was as good as the reliability on the via-in-padstructures;

• The reliability of samples assembled using flux wasas good as the reliability of assemblies using solderpaste.

Finally, conclusions were drawn based on the hypothesistesting results.

Results and Failure Analysis

• Of the 72 packages sent for testing, one sample showedvery early failure at 309 cycles. This package wasassembled on a 13 mil conventional pad using solderpaste. Cross sectional analysis did not show anynoticeable cause for early failure. The remainingpackages show a characteristic life of 3143 cycles(Figure 6).

• The packages assembled on the via-in-pad structuresshowed Eta (N63) value of 3123 cycles while thoseassembled on conventional pad had an Eta value of 2798cycles. Figure 7 shows the Weibull plot of the packagestested. Hypothesis analysis showed that the reliability ofthe via-in-pad assemblies was significantly more than thereliability of packages on the conventional pad. Samplet-test statistics are mentioned in Table 2.

Figures 6 & 7: Weibull Plot – All CSPs , Via in pad

• With decreasing pad diameter, the solder joint reliabilitywas seen to increase (Figure 8). Smaller pads increasestandoff and trace routing density [Primavera, 1999].The pad diameter could be decreased with acorresponding result of increase in standoff andreliability upto a certain limit beyond which placementyield is affected. It was shown that by decreasing the paddiameter from 15 mils to 11 mils the Eta was increasedin value by more than 40%. Hypothesis analysis showedthat the reliability of packages assembled on the 11 milpad was significantly more than the reliability ofpackages on the 15 mil pads. The t-test statistics arementioned in Table 2.

Figure 8: Weibull Plot - Pad Diameters

• There was no significant difference in reliability betweenpackages assembled using solder paste and flux,although the flux assemblies showed slightly highernumber of cycles to failure. Cross-sectional analysisrevealed that the package failure mode was of a solderfatigue type. This fatigue failure happened in the soldernear the component side, independent of the board padsize or type (Figure 9). Immaterial of the pad type, thecracks were very fine and originated from the solder jointcorners and moved towards the solder joint center,indicating fatigue type cracks.

Figure 9: Cross Section of Failed Solder Joints

• Electrical mapping of the failed samples showedthat most of the solder joints showing failures werelocated at the corner of the package. This is due tothe fact that the distance to neutral point (DNP) wasthe maximum for these solder joints. The CTE ofthe package, in this case the silicon with polyimide,was in the 4-5 ppm/0C, while the CTE of the boardwas in the 14-16 ppm/0C range.

• Dye penetration tests were carried out supported theobservations made by cross sectional analysis andelectrical mapping as shown in Figure 10.

CONCLUSIONS

This research effort generated a substantial quality ofknowledge regarding the effects of use of solder paste andflux, pad diameter and the use of via-in-pad structures on theCSP assembly process as well as the reliability of thepackage. The results of this experiment can be summarized asfollows.

• A total of 96 wafer level packages (4416 solderjoints, of which 2208 via-in-pad) were successfullyassembled.

• The reliability of the test package was found to beexceed 1000 cycles 0 to 1000C.

• The solder joints assembled on the via-in-pad padswere equivalent to conventional pads;

• Increased standoff resulted in higher reliability. Bydecreasing the pad diameter from 15 mils to 11 milsthe characteristic life increased 40%

• The via-in-pad solder joints showed the presence ofa void at the via opening. However, the presence ofthis void did not affect the reliability of the solderjoint;

Although the above observations are specific to the packageassembled and evaluated, some of the conclusions can begenerically applied to CSP assembly and reliability.

REFERENCES

1. Barrett, S., Hong, Y., Larson, A., and Elinius, P.,"Reliability Evaluation of Ultra CSPTM", SMTAEmerging Technologies Conference, Chandler, AZ,November 1998.

2. DiStefano, T. H., "Wafer-level Fabrication of ICPackages", Chip Scale Review, May 1997, pp. 20-27.

3. Elenius, P., "Wafer-level Processing GainsMomentum", Solid State Technology, April 1999,pp. 45-50.

4. Elenius, P., & Hong Yang, “The Ultra CSPTM

Wafer Scale Package”, Application Notes, HDIExpo, Tempe AZ, September 1998.

5. Ghaffarian, R., “Chip Scale Package and AssemblyReliability”, IMAPS Advanced Chip ScalePackaging Workshop, Portland, OR, August 1999.

6. Juskey, F., "Advanced IC PackagingDevelopments", Electronic Packaging andProduction, July 1998, pp. 65-68.

7. Nguyen, L., Kelkar, N., Kao, L., & Takiar, H.,“Wafer Level Chip Scale Packaging – Solder JointReliability”, Proceedings IPC/SMTA ElectronicsAssembly Expo 1998 – San Diego, CA, September1998.

8. Partridge, J., & Hart, C., "Taking the CSP Plunge",Electronic Packaging and Production, April 1999,pp. 48-53.

9. Patridge, P., & Gunn, R., " Paste Printing andCharacterization for CSP Assemblies", SMTAInternational Proceedings, San Jose, CA., 1998.

10. Primavera, A., "Influence of PCB Parameters onChip Scale Package Assembly and Reliability",SMTA International Proceedings, San Jose CA.,September 1999.

11. Primavera, A., & Srihari, K., "Factors That AffectVoid Formation in BGA Assembly", IPC/SMTAElectronics Assembly Exposition, Long Beach,CA., 1998.

12. Primavera, A., ‘Factors Contributing to VoidFormation in BGAs’, IPC SMTA Annual NationalSymposium on BGA – Rhode Island, RI, October1998.

13. Sturm, R., "Voiding in BGAs", BGA/DCAConsortium Report, Universal InstrumentsCorporation, Binghamton, New York, December1996.

14. Wang, Z., Tan, Y., & Chua, K., “Board LevelReliability of Chip Scale Packages”, ProceedingsIPC/SMTA BGA Annual National Symposium,Minneapolis, MN, May 1998.

Pad Type Pad Diameter Capture Pad Via Diameter15 - -13 - -11 - -15 15 513 15 511 15 5

Conventional NSMD Pad

Via-in-Pad NSMD Pad

Table 1

Table 2

Mean Std. Dev. N Diff. Std. Dev Diff. t df pVia-in-Pad 2675.17 279.075Con. Pad 2087.5 207.12

11 mil Pad 2805.67 868.5615 mil Pad 2087.5 207.12

11 0.019712 718 913.005 2.725

290.19 7.015 11 0.000022312 588