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Downloaded from www.pencilji.com Downloaded from www.pencilji.com VISVESVARAYA TECHNOLOGICAL UNIVERSITY BELGAUM, KARNATAKA SUBMITTED BY BHARATH . S . BHARATH . S . BHARATH . S . BHARATH . S . & KOUSHIK . G . K. KOUSHIK . G . K. KOUSHIK . G . K. KOUSHIK . G . K. (1RN03CS015) (1RN03CS026) GUIDED BY MR. PRASAD . B . & PROF. ASHOKA . D . V . DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING R.N.S.I.T. ASSEMBLERS TWO PASS MODEL FOR WORKING OF 8086

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VISVESVARAYA TECHNOLOGICAL UNIVERSITY BELGAUM, KARNATAKA

SUBMITTED BY

BHARATH . S .BHARATH . S .BHARATH . S .BHARATH . S . & KOUSHIK . G . K.KOUSHIK . G . K.KOUSHIK . G . K.KOUSHIK . G . K. (1RN03CS015) (1RN03CS026)

GUIDED BY

MR. PRASAD . B . & PROF. ASHOKA . D . V .

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING R.N.S.I.T.

ASSEMBLERS

TWO PASS MODEL FOR WORKING OF 8086

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A PROJECT ON:

Two pass model for working of 8086

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CERTIFICATE

This is to certify that Mr. KOUSHIK. G. K and Mr. BHARATH. S. have satisfactorily completed the project on IMPLEMENTATING A 2-PASS ASSEMBLERFOR THE WORKING MODEL OF 8086 Prescribed by VISVESVARAYA TECHNOLOGICAL UNIVERSITY Course in our

college in the year 2005-2006.

SIGNATURE:

STAFF H.O.D PRINCIPAL

SIGNATURE OF EXAMINERS:

1.EXTERNAL 2.INTERNAL

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ACKNOWLEDGEMENT

Our sincere gratitude is extended to UG course of V.T.U for the

inclusion of this mini project in the 5th semester B.E. We are grateful to

R.N.S. Institute of Technology for helping to pursue our B.E. course. I am

extremely thankful to our Principal Dr.H.N.Shiva Shankar, H.O.D of

Computer Science Department A.M.Padma Reddy and faculty members

Mr.Prasad.B and Prof.Ashoka.D.V. for their kind advice and co-operation.

(BHARATH. S and KOUSHIK. G .K.)(BHARATH. S and KOUSHIK. G .K.)(BHARATH. S and KOUSHIK. G .K.)(BHARATH. S and KOUSHIK. G .K.)

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ABSTRACT

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CONTENTS

1. Introduction To Assemblers 2. Concept Used in the Project

3. Explanation of each function used in the project

4. Coding

5. Testing 6. Conclusion 7. Bibliography

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INTRODUCTIONINTRODUCTIONINTRODUCTIONINTRODUCTION

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INTRODUCTION TO ASSEMBLERS

� Definition of Assemblers

“An assembler is a program that accepts assembly language program as input and produces its equivalent machine code.”

An assembly language is a low level programming language for

the system.

� Block Diagram Of An Assembler

The above diagram is the basic block diagram of an assembler. � Assembling

“Assembling is a translating process in which source program in

assembly language will be translated in to object module containing only machine codes and data.” Assembler also recognizes the symbol definition and symbol reference, Computes the values for the expression and use them while generating machine codes.

� An assembler can handle Assembler Directives and Decode Assembly language instructions.

� An Assembler is capable of the following:

� Generates machine code that can be loaded and executed. � Providing syntax errors.

SOURCE PROGRAM

<filename>.asm ………………….

mov ax,[bx] and cx,dx …………………………………….

end

Read Line by Line.

Analyzes and generates the code.

Write line by line.

Error messages

ASSEMBLED LIST FILE

<filename>.lst #01………… #02 8B07 #03 23CA #04………….. #05…………..

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� Provide symbolic labels for representation of constants and address.

� Access to all the machine’s resources by the assembled program.

� Run time locations of program and memory.

� Task of an Assembler

The major task of an assembler is to translate the given assembly language program to its machine language program. Other tasks of assembler are:

• Checking each line of the source input i.e. check whether the input line is instruction, assembler directive or comment etc….

• Processing Assembler Directive. • Recognizing symbol definitions. • Flagging Errors for undefined symbols, invalid symbols etc…. • Recognizing addressing modes. • Evaluating expressions during assembling time.

TWO PASS ASSEMBLER There are options available while designing an Assembler. They are:

1. One-Pass Assembler 2. Two-Pass Assembler 3. Multi-Pass Assembler

We use Two-Pass Assemblers in the design of 2-Pass Assembler for the working model of 8086 because of the ease of construction and the simple data structures used in it.

� Two-Pass Assembler:

� A two Pass Assembler scans the source code twice, once during first pass and the other during the second pass.

� During the first pass, all the symbols defined in the code are stored in the symbol table (SYMTAB) and memory is allocated for the instructions.

� During the second pass the machine codes are loaded into the memory allocated for each instructions.

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� Design of Two-Pass Assembler:

PASS-1: The main aim of Pass-1 is to prepare symbol table (SYMTAB). The other tasks of Pass-1 are:

• Keep track of location counter. i.e. assign addresses to all statements in the program.

• Determining length of data and updating location counter. • Save the values assigned to all labels in symbol table (SYMTAB)

for use in Pass-2. • Checking for multiple symbol definitions in the symbol table

(SYMTAB). • Perform some processing of Assembler directives.

PASS-2: The main aim of Pass-2 is to assemble instructions and generate object program. The task of Pass-2 is to:

• Assemble instructions. • Perform processing of Assembler directives not done during Pass1. • Write the object program.

� Advantages of Two-Pass assembler:

A Two-Pass assembler is more convenient to work with than a One-Pass

Assembler. The basic idea behind using a Two-Pass Assembler is to resolve forward references that are encountered during first pass.

2-PASS ASSEMBLER FOR THE WORKING MODEL OF 8086.

Now, in our Project we need to Implement 2-Pass Assembler for the working model of 8086.

The main aim of our project is to convert an assembly level program in 8086 to its

equivalent opcode .

• 8086 Instruction set contains six Bytes. • Any instruction in 8086 can have a minimum of 1 byte and a

maximum of 6 bytes. • So, each and every instruction in 8086 differs in their opcode

depending on the instruction set.

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The instruction set of 8086 is as follows: BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6

OPCODE D W MOD REG R/M LOWER BYTE DISP/DATA

HIGHER BYTE DISP/DATA

LOWER BYTE DATA

HIGHER BYTE DATA

Byte 1:

o Opcode occupies 6 bits; it defines the operation to be carried out by the instruction. Ex: mov 100010

o D occupies 1 bit. o W occupies 1 bit.

Byte 2: o MOD occupies 2 bits. o REG occupies 3 bits. o R/M occupies 3 bits.

Byte 3 to Byte 6:

Third to Sixth byte are optional and it depends on the instruction and contains displacement or data values. Most of the instructions use two bytes of the instruction set.

Aim and Description of the Project:

The main aim of our project is to convert an assembly level program in 8086 to its equivalent opcode, only if the instructions used in the program use only the instructions, which are designed in the project.

Here we don’t analyze the logic present in the program but rather check for the instruction if present in the project designed then its equivalent opcode will be as the output, otherwise there will be an error message displayed.

There are many instructions present in the working model of 8086. But, we in our project design the code in such a way that it recognizes only a few instructions of 8086 model.

For example there are instructions such as

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mov, add, sub, cmp, and, aaa, daa, je, cld, pushf, popf, inc, dec, hlt,……………. Each of the above instruction has their own opcode. Example:

If the input is a program or a part of the program then the output consists of the input with its equivalent opcode. Input:

mov bx,si mov ax,[bx] and cx,dx pushf popf cld end

Output:

Opcode Source Program

8bde mov bx,si 8b07 mov ax,[bx] 23ca and cx,dx

9c pushf 9d popf fc cld

end

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Concept Used in the ProjectConcept Used in the ProjectConcept Used in the ProjectConcept Used in the Project

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CONCEPT USED IN THE PROJECT

THIS TABLE IS REFERED FOR STURCTURES USED IN PROJECT

R/M MOD-00 MOD-01 DISP 08

MOD-10 DISP-16

MOD-11 W=0 W=1

000 BX+SI BX+SI+DISP BX+SI+DISP AL AX

001 BX+DI BX+DI+DISP BX+DI+DISP CL CX

010 BP+SI BP+SI+DISP BP+SI+DISP DL DX

011 BP+DI BP+DI+DISP BP+DI+DISP BL BX

100 SI SI+DISP SI+DISP AH SP

101 DI DI+DISP DI+DISP CH BP

110 DIRECT BP+DISP BP+DISP DH SI

111 BX+SI BX+DISP BX+DISP BH DI

Formats for register to register , memory to register & implied instructions . 1. aaa

0 0 1 1 0 1 1 1

2. daa

0 0 1 0 0 1 1 1

3. hlt

1 1 1 1 0 1 0 0

4. je

0 1 1 1 0 1 0 0

5. cld

1 1 1 1 1 1 0 0

6. pushf

1 0 0 1 1 1 0 0

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7. popf 1 0 0 1 1 1 0 1

8. aas

0 0 1 1 1 1 1 1

9. clc

1 1 1 1 1 0 0 0

10. cli

1 1 1 1 1 0 1 0

11. cmc

1 0 0 1 1 0 0 0

12. das

0 0 1 0 1 1 1 1

13. nop

1 0 0 1 0 0 0 0

14. sahf

1 0 0 1 1 1 1 0

15. lahf

1 0 0 1 1 1 1 1

16. xlat

1 1 0 1 0 1 1 1

17. stc

1 1 1 1 1 0 0 1

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18. sti

1 1 1 1 1 0 1 1 19. std

1 1 1 1 1 1 0 1 20. and

0 0 1 0 0 0 D W MOD REG R/M

21. inc 16-bit increment

0 1 0 0 0 REG

8-bit increment 1 1 1 1 1 1 1 W MOD 0 0 0 R/M

22. dec 16-bit increment

0 1 0 0 1 REG

8-bit increment 1 1 1 1 1 1 1 W MOD 0 0 1 R/M

23. mov

1 0 0 0 1 0 D W MOD REG R/M

24. add

0 0 0 0 0 0 D W MOD REG R/M 25. sub

0 0 1 0 1 0 D W MOD REG R/M

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26. cmp

0 0 1 1 1 0 D W MOD REG R/M

27. xchg

1 0 0 0 0 1 1 W MOD REG R/M 28. adc

0 0 0 1 0 0 D W MOD REG R/M 29. xor

0 0 0 1 1 0 D W MOD REG R/M Formats for immediate addressing mode .

1. mov

1 0 1 1 W REG

2. add 1 0 0 0 0 0 S W MOD 0 0 0 R/M

3. sub

1 0 0 0 0 0 S W MOD 1 0 1 R/M 4. cmp

1 0 0 0 0 0 S W MOD 1 1 1 R/M

5. and

1 0 0 0 0 0 S W MOD 1 0 0 R/M

6. xor

1 0 0 0 0 0 S W MOD 1 1 0 R/M

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7. adc

1 0 0 0 0 0 S W MOD 0 1 0 R/M

The concept used in our project is to generate the opcode for the above instructions. We also refer to the table given in page number 12 to get the register values and the mode used.

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Explanation of each functiExplanation of each functiExplanation of each functiExplanation of each function used in the projecton used in the projecton used in the projecton used in the project

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Explanation of each function used in the project int findopc(int,int) This function is used to find the opcode of an instruction. If the instruction consists of only one byte then we return the opcode of the instruction. If the instruction consists of two bytes then the opcode of the instruction is left shifted by 2 positions, d bit is left shifted by 1 position and finally we return the sum of d, opcode and w. For inc and dec instructions, if the operand field is 16-bit then return the respective opcode . If the operand field is 8-bit then the opcode is left shifted by 1, added to w bit, the result is returned. int regop(int) This function is used to find opcode of the register.i.e 2nd byte.

When there are both operands

It calls immed16, immed8 functions if there are immediate 16 and 8 bit operands respectively. If it is not immediate then find reg is called. When there is single operand

The manipulations are done according to the function and returns opcode

of the register. int read_ins(FILE) This function reads one instruction , returns 1 if the instruction is end otherwise returns 0 . This function also eliminates the braces (‘[‘,’]’), if the operand is memory. int getins(FILE) Basically in this function we have 3 arrays (ins,op1,op2) . The arrays will be containing the instruction, operand1 and operand2 respectively. This function returns the position of operand2.

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int syerror() This function is used to check for errors in the program. int checkins() This function checks whether the instruction is present or not . It return 0, if the instruction is found, else it returns 1.

int checkregop1() This function checks whether the register is present or not. It return 0, if register is found, else it returns 1. int checkregop2() This function checks whether the 2nd register is present or not . It return 0, if 2nd register is found, else it returns 1. int function()

This function with the name function is used to display errors. When we encounter end instruction we come out of this function. int immed16(int)

This function returns the opcode for immediate addressing mode of 16-bit

register. int immed8(int)

This function returns the opcode for immediate addressing mode of 8-bit register.

int findreg(int,int) If both the operands are register then we evaluate the opcode of the registers, which is returned to the calling function. int check_label(char[]) This function is used to find whether the instruction is a label or not. If it is a label we return 1 else we return 0.

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void prog(FILE)

This function is used to display the input of the program. int checkmem(int)

This is used check the memory operand in an instruction. It returns 0 if it is memory operand else it returns the 3. void main()

It reads the file name from the user, checks whether the file is open or not and displays appropriate messages. The function () is called which sets the flag 10 according to errors, if flag10 is not equal to 1 then are no errors, then we display the program with its equivalent opcode else we display the errors with the program.

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CODECODECODECODE

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CODE

#include<stdio.h>

#include<conio.h> #include<string.h>

/* Global Declarations */ char ins[10],op1[10],op2[10]; int flag9,flag10,flag11,flag12,flag14;

char label1[10]; int w,linctr,e,mod;

FILE *fp2; char filename[20];

int locctr,loc;

/* Structure to store the name,length,opcode */

struct optab {

char name[10]; int len;

int op; };

struct optab std[30]={{"mov",2,34},{"add",2,0},{"inc",1,4},{"dec",1,4},{"sub",2,

10},{"aaa",1,55},{"daa",1,39},{"cmp",2,14},{"hlt",1,244},{"je",2,116},{"cld",1,252},{"pushf",1,156},{"popf",1,157},{"and",2,8},{"xchg"

,2,33},{"aas",1,63},{"clc",1,248},{"cli",1,250},{"cmc",1,152},{"das",1,47},{"nop",1,144},{"xlat",1,215},{"sahf",1,158},{"lahf",1,159},{"

stc",1,249},{"sti",1,251},{"std",1,253},{"xor",2,6},{"adc",2,4}};

/* Structure to store the name of the registers & its value */

struct regtr {

char segreg[10]; int value;

}; struct regtr

rg[15]={{"ax",0},{"bx",3},{"cx",1},{"dx",2},{"si",6},{"di",7},{"al",0},{"bl",3},{"cl",1},{"dl",2},{"ah",4},{"bh",7},{"ch",5},{"dh",6}};

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/* Function to check whether the instruction is present or not */ int checkins()

{ int i;

for(i=0;i<29;i++) {

if(strcmp(ins,std[i].name)==0) {

return 0;

} if(strcmp(ins,"end")==0)

{ return 0;

} }

return 1; }

/* Function to check whether the register is present or not */ int checkregop1()

{ int i;

for(i=0;i<14;i++) {

if(strcmp(op1,rg[i].segreg)==0) {

return 0; }

} if(i==14 && strcmp(label1,op1)==0)

{ return 0;

}

return 1; }

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/* Function to check whether the second register is present or not */ int checkregop2()

{ int i;

for(i=0;i<14;i++) {

if(strcmp(op2,rg[i].segreg)==0) {

return 0; }

}

if(i==14 && isdigit(op2[0])) {

return 0; }

return 1; }

/* Function to read the instruction */

int read_ins(FILE *fp2)

{ int g=1,k,f=0;

while(1) {

k=getins(fp2); if(strcmp(ins,"end")==0)

{ return 1;

} if(op2[0]=='[' && op2[k-1]==']')

{ while(g!=k-1)

{ op2[f++]=op2[g++];

}

op2[f]='\0'; }

return 0; }

}

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/* Function to store the operand and instruction in array */ int getins(FILE *fp2)

{ int h=0,j=0,k=0,s=0;

char space[20]; char ch;

while(ch!='\n') {

ch=fgetc(fp2);

while(ch==' ') {

ch=fgetc(fp2); space[s++]=ch;

} while(ch!=' '&&ch!='\n')

{ ins[j++]=ch;

ins[j]='\0'; ch=fgetc(fp2);

} if(strcmp(ins,"end")==0)

{ flag14=1;

break;

} while(ch!=',' && ch!='\n')

{ ch=fgetc(fp2);

if(ch!=',') {

op1[h++]=ch; }

} while(ch!='\n')

{ ch=fgetc(fp2);

if(ch!='\n') {

op2[k++]=ch;

}

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}

op1[h]='\0'; if(strcmp(op2,'\0')==0)

{ op1[h-1]='\0';

} else

{ op2[k]='\0';

} }

return k; }

/* Function to check for errors in the program */

int syerror() {

int i,j,temp; for(i=0;i<14;i++)

{ if(strcmp(op1,rg[i].segreg)==0)

{ break;

} }

for(j=0;j<14;j++)

{ if(strcmp(op2,rg[j].segreg)==0)

{ break;

} }

if(j==14 && isdigit(op2[0])) {

return 0; }

if(i<6 && j>=6) {

return 1; }

else if(i>=6 && j<6)

{

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return 1;

} return 0;

}

/* Function to display the errors if any */ void function()

{ int flag,flag1,flag2,flag3,flag4;

int a; e=0;

printf("\n");

while(1) {

e++; flag=read_ins(fp2);

if(flag==1) {

strcpy(ins,'\0'); break;

} a=check_label(ins);

flag1=checkins(); if((strcmp(op1,'\0') || strcmp(op2,'\0') !=0) &&

(flag1!=1)) {

flag2=checkregop1();

if(strcmp(op2,'\0')!=0 && flag2!=1) {

flag3=checkregop2(); if(flag3!=1)

{ flag4=syerror();

} }

} if(flag1==1)

{ flag1=0;

flag10=1; printf("%d:no such instruction found\n",e);

}

if(flag2==1)

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{

flag2=0; flag10=1;

printf("%d:no such register found or label found\n",e);

} if(flag3==1)

{ flag3=0;

flag10=1; printf("%d:no such register found\n",e);

} if(flag4==1)

{ flag4=0;

flag10=1;

printf("%d:operands mismatch\n",e); }

strcpy(op1,'\0'); strcpy(op2,'\0');

strcpy(ins,'\0'); }

return; }

/* Function to opcode of the instruction */

int findopc(int d,int w)

{ int x,y,z,res,i,j;

if(flag11!=1) {

for(i=0;i<29;i++) {

if(strcmp(ins,std[i].name)==0) {

break; }

}

if(i==0||i==1||i==4||i==7||i==13||i==14||i==27||i==28) {

x=std[i].op<<2;

y=d<<1;

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z=y+w;

res=x|z; return res;

}

if(i==5||i==6||i==8||i==9||i==10||i==11||i==12||i==15||i==16||i==17||i==18||i==19||i==20||i==21||i==22||i==23||i==24||i

==25||i==26) {

return std[i].op; }

if(i==2||i==3) {

for(j=0;j<14;j++) {

if(strcmp(op1,rg[j].segreg)==0)

{ break;

} }

if(j<6) {

return std[i].op; }

else {

x=127<<1; res=x|w;

locctr=locctr+1;

return res; }

} }

}

/* Function to opcode of the register */ int regop(int mod)

{ int i,j,o,z,res,result,temp1,flag=0;

if(strcmp(op2,'\0')!=0)

{

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for(i=0;i<14;i++)

{ if(strcmp(op1,rg[i].segreg)==0)

{ break;

} }

for(j=0;j<14;j++) {

if(strcmp(op2,rg[j].segreg)==0) {

break; }

} if(j==14 && i<6)

{

w=1; flag11=1;

immed16(i); }

if(j==14 && i>=6)

{ w=0;

flag11=1; immed8(i);

} if(i<6 && j<6)

{ w=1;

}

else if(i>=6 && j>=6) {

w=0; }

if(flag11!=1) {

result=findreg(rg[i].value,rg[j].value); return result;

} }

else if(strcmp(op2,'\0')==0) {

for(i=0;i<14;i++)

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{

if(strcmp(op1,rg[i].segreg)==0) {

if(i<6) {

flag=0; w=1;

} else if(i>5)

{ flag=1;

w=0; }

if(strcmp(ins,std[3].name)==0) {

if(flag!=1)

{ o=1<<3;

result=o|rg[i].value; return result;

} else

{ o=mod<<6;

z=1<<3; res=rg[i].value+z;

result=o|res; return result;

} }

else if(strcmp(ins,std[2].name)==0)

{ if(flag!=1)

{ return rg[i].value;

} else

{ o=mod<<6;

z=0<<3; res=z|rg[i].value;

result=o|res; return result;

}

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34

}

} else if(strcmp(ins,std[9].name)==0)

{ flag9=1;

return NULL; }

} }

}

/* Function to find opcode of immediate addressing mode for 16-bit registers */

int immed16(int i) {

int x,y,z,imval; flag12=1;

if(strcmp(ins,std[0].name)==0) {

x=23<<3; z=rg[i].value+x;

locctr=locctr+1;

return z; }

if(strcmp(ins,std[1].name)==0)

{ x=129<<8;

y=mod<<6; z=rg[i].value+y+x;

locctr=locctr+2; return z;

} if(strcmp(ins,std[4].name)==0)

{ x=129<<8;

y=mod<<6;

z=5<<3; imval=rg[i].value+x+y+z;

locctr=locctr+2; return imval;

} if(strcmp(ins,std[7].name)==0)

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35

{

x=129<<8; y=mod<<6;

z=7<<3; imval=rg[i].value+x+y+z;

locctr=locctr+2; return imval;

} if(strcmp(ins,std[13].name)==0)

{ x=129<<8;

y=mod<<6; z=4<<3;

imval=rg[i].value+x+y+z; locctr=locctr+2;

return imval;

} if(strcmp(ins,std[27].name)==0)

{ x=129<<8;

y=mod<<6; z=6<<3;

imval=rg[i].value+x+y+z; locctr=locctr+2;

return imval; }

if(strcmp(ins,std[28].name)==0) {

x=129<<8; y=mod<<6;

z=2<<3;

imval=rg[i].value+x+y+z; locctr=locctr+2;

return imval; }

}

/* Function to find opcode of immediate addressing mode for 8-bit registers */

int immed8(int i) {

int x,y,z,imval; flag12=1;

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36

if(strcmp(ins,std[0].name)==0)

{ x=22<<3;

z=rg[i].value+x; return z;

} if(strcmp(ins,std[1].name)==0)

{ x=128<<8;

y=mod<<6; z=rg[i].value+y+x;

locctr=locctr+1; return z;

} if(strcmp(ins,std[4].name)==0)

{

x=128<<8; y=mod<<6;

z=5<<3; imval=rg[i].value+x+y+z;

locctr=locctr+1; return imval;

}

if(strcmp(ins,std[7].name)==0)

{ x=128<<8;

y=mod<<6; z=7<<3;

imval=rg[i].value+x+y+z;

locctr=locctr+1; return imval;

} if(strcmp(ins,std[13].name)==0)

{ x=128<<8;

y=mod<<6; z=4<<3;

imval=rg[i].value+x+y+z; locctr=locctr+1;

return imval; }

if(strcmp(ins,std[27].name)==0)

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37

{

x=128<<8; y=mod<<6;

z=6<<3; imval=rg[i].value+x+y+z;

locctr=locctr+1; return imval;

} if(strcmp(ins,std[28].name)==0)

{ x=128<<8;

y=mod<<6; z=2<<3;

imval=rg[i].value+x+y+z; locctr=locctr+1;

return imval;

} }

/* Function to evaluate opcode for registers */

int findreg(int reg1,int reg2) {

int y,z,res; y=mod<<6;

reg1=reg1<<3; z=reg2+reg1;

res=y|z;

return res; }

/* Function to check for label in the program */

int check_label(char sting[ ]) {

int i=0,b=0,j,p=0,q=0; char label[10];

while(sting[i]!=':' && sting[i]!='\0')

{ label[b++]=sting[i++];

} label[b]='\0';

if(sting[i]=='\0')

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38

{

sting[i]='\0'; return 0;

} else

{ i++;

j=0; while(p!=b)

{ label1[p++]=label[q++];

} label1[p]='\0';

while(sting[i]!='\0') {

ins[j++]=sting[i++];

} ins[j]='\0';

return 1; }

}

/* Function to check for memory operand in an instruction */ int checkmem(int k)

{ int i=1,j=0;

if(op2[0]=='[' && op2[k-1]==']')

{ while(i!=k-1)

{ op2[j++]=op2[i++];

} op2[j]='\0';

return 0; }

return 3; }

/* Function to display program */ void prog(FILE *fp1)

{ char ch1;

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39

printf("\t\t");

printf("%d: ",linctr); while(ch1!='\n')

{ ch1=fgetc(fp1);

if(ch1==EOF) break;

else printf("%c",ch1);

} linctr++;

}

void err() {

int i;

char ch; getch();

rewind(fp2); printf("\nPROGRAM\n");

i=1; printf("\n%d : ",i);

while(1) {

ch=fgetc(fp2); if(ch==EOF)

{ break;

} else

{

printf("%c",ch); if(ch=='\n')

{ getch();

printf("\n%d : ",++i); }

} }

fclose(fp2); }

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void noerr(FILE *fp,FILE *fp1)

{ int k,flag2,reg,opc,i,temp,temp1;

printf("\nLOCCTR\t OPCODE\t\t PROGRAM\n\n");

printf("%-5d",1000); flag14=0;

while(1) {

k=getins(fp); if(flag14==1)

break; flag2=check_label(ins);

mod=checkmem(k); if(mod==0)

{

if(strcmp(op1,"si") || strcmp(op2,"si")==0) {

rg[4].value=4; }

if(strcmp(op1,"di") || strcmp(op2,"di")==0) {

rg[5].value=5; }

if(strcmp(op1,"bx") || strcmp(op2,"bx")==0) {

rg[1].value=7; }

}

reg=regop(mod); opc=findopc(1,w);

rg[4].value=6; rg[5].value=7;

rg[1].value=3;

if((strcmp(op1,'\0') && strcmp(op2,'\0'))!=0 && flag11!=1)

{ opc=opc<<8;

reg=reg+opc; printf("%8x",reg);

}

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41

else if((strcmp(op1,'\0') || strcmp(op2,'\0'))!=0 &&

flag11!=1) {

if(flag9!=1) {

printf("%6x",opc); printf("%x",reg);

} }

else if((strcmp(op1,'\0') && strcmp(op2,'\0'))==0) {

printf("%7x",opc); }

if(flag12==1) {

printf("%5x",reg);

printf(",%s",op2); flag11=0;

flag12=0; }

for(i=0;i<29;i++) {

if(strcmp(ins,std[i].name)==0) break;

}

if(flag2==1) {

loc=locctr;

} temp=std[i].len;

locctr+=temp; if(flag9==1)

{ printf("%6x",opc);

temp1=255-(locctr-loc); printf("%x",temp1);

flag9=0; }

prog(fp1); getch();

printf("\n%-5x",4096+locctr);

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42

k=0;

strcpy(op1,'\0'); strcpy(op2,'\0');

strcpy(ins,'\0'); }

printf("\t");

prog(fp1); fclose(fp1);

fclose(fp); printf("\n\tLength of the PROGRAM is %x h\n",locctr);

}

/* Function main */

void main() {

FILE *fp1,*fp; linctr=1;

strcpy(op1,'\0'); strcpy(op2,'\0');

clrscr(); printf("Enter the filename\n");

scanf("%s",filename); fp1=fopen(filename,"r");

fp=fopen(filename,"r"); fp2=fopen(filename,"r");

if(fp==NULL)

{ puts("\nError : Cannot open the file\n");

getch(); exit(0);

}

function();

(flag10!=1) ? noerr(fp,fp1) : err();

getch(); }

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43

CONCLUSION CONCLUSION CONCLUSION CONCLUSION

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44

CONCLUSION

The main aim of the project was to implement a 2-pass Assembler for the working model of 8086,which was exclusively exhaustive.Though the project is not a full fledged software as TASM, it provides all the basic requirements .

We can improve our project by including an interactive case sensitive of the

instructions and all formal beginning of the 8086 program like .model, .data, .code etc… This project nevertheless provides the basic features of an assembler i.e.

conversion of source program to object program and also indicating errors in any.

ADVANTAGES:

• Main advantage – this project mainly concentrates on generating opcode for only the instructions which has been implemented.(refer page )

• Opcode is being generated for almost all 1-byte instructions. DISADVANTAGES:

• the project doesn’t concentrate on generating output for the given assembly program.

• Opcode is not generated for formal beginning of the 8086 program like .model, .data, .code etc…

• Symbol is not been generated. • In our implementation D-bit is always 1 i.e. REG is always the destination

operand.