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ASP-DACAsia and South Pacific DesignAutomation Conference 1998

February 10-13, 1998Pacifico YokohamaYokohama, Japan

ASP-DAC ‘98 Proceedings © 1998 by IEEE. All rights reserved. No part of this book may be reproduced in any form,nor may it be stored in a retrieval system or transmitted in any form without written permission of IEEE.

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ASP-DAC98:Cover Page Front Matter Table of Contents

Session Index Author Index

i

Proceedings of the

ASP-DAC ’98Asia and South Pacific Design Automation Conference 1998

February 10 - 13, 1998Pacifico YokohamaYokohama, Japan

Sponsored by:

IEICE (Institute of Electronics, Information andCommunication Engineers)

IPSJ (Information Processing Society of Japan)ACM SIGDAIEEE Circuits and Systems Society

Supported by:

EIAJ (Electronics Industries Association of Japan)STARC (Semiconductor Technology Academic

Research Center)

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Additional copies may be ordered from:

IEEE Order Dept.Hoes LaneP.0. Box 1331Piscataway, NJ 08854, U.S.A.

Copyright and Reprint Permission: Abstracting is permitted with credit to the source.Libraries are permitted to photocopy beyond the limit of U.S. copyright law for privateuse of patrons those articles in this volume that carry a code at the bottom of the firstpage, provided the per-copy fee indicated in the code is paid through CopyrightClearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprintor republication permission, write to IEEE Copyrights Manager, IEEE Service Center,445 Hoes Lane, P.O.Box 1331, Piscataway, NJ 08855-1331. All rights reserved.

Copyright ©1998 by the Institute of Electrical and Electronics Engineers, Inc.

IEEE Catalog Number 98EX121ISBN 0-7803-4425-1 (Softbound Edition)ISBN 0-7803-4426-X (Microfiche Edition)ISBN 0-7803-4427-8 (CD-ROM Edition)Library of Congress: 97-80907

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ASP-DAC ’98 Organizing Committee

General Chair:

Tokinori KozawaSTARC (Semiconductor TechnologyAcademic Research Center)Onarimon BN Build. 5F16-10 Shimbashi 6-chome, Minato-ku,Tokyo 105 JapanPhone: +81-3-3436-1250, FAX: +81-3-3436-1295E-mail: kozawa@crl.hitachi.co.jp

Secretaries:

Toshihiro HattoriHitachi, Ltd.,hattori@crl.hitachi.co.jp

Osamu KaratsuAdvanced Telecommunications ResearchInstitute InternationalE-mail: kara@ctr.atr.co.jp

Past Chair:

Isao ShirakawaOsaka University

Steering Committee Chair:

Tatsuo OhtsukiWaseda University

Assistant Secretary:

Nobuyuki HayashiHitachi, Ltd.

Technical Program Co-Chairs:

Shuji TsukiyamaChuo University

Philip ChanThe Hong Kong University ofScience and Technology

Vice TPC Chair:

Hiroaki KuniedaTokyo Institute of Technology

Tutorial Co-Chairs:

Hidetoshi OnoderaKyoto University

Jack PoonMotorola Semiconductors Hong Kong Ltd.

Tutorial Vice Chair:

Takashi KambeSHARP Corporation

Design Contest Co-Chairs:

Akihiko MorinoNEC Corp.,

Chak-Kuen WongThe Chinese University of Hong Kong

Design Contest Vice Chair:

Akinori NishiharaTokyo Institute of Technology

EDA Technofair Chair:

Yoshitada FujinamiNEC Corp.

Finance Chair:

Michiaki MuraokaMatsushita Electric Industry Co.,Ltd.

Publicity Chair:

Takashi MitsuhashiToshiba Corporation

Publication Chair:

Masaharu ImaiOsaka University

Audio Visual Chair:

Tsuneo NakataFujitsu Laboratories Ltd.

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Local Arrangement Chair:

Katsuhiko SeoMitsubishi Electric Corporation

Registration Chair:

Masahiro KoyamaSony Corporation

Promotion Chair:

Nagisa IshiuraOsaka University

IEICE/VLD Chair:

Hitoshi KitazawaNTT Corp.

IEICE/TGCAS Chair:

Akinori NishiharaTokyo Institute of Technology

IEICE/ICD Chair:Gensuke GotoFujitsu Laboratories Ltd.

IPSJ/SIGDA Chair:

Kenji YoshidaToshiba Corporation

EIAJ/EDA TC Chair:

Sagoro HazamaFujitsu LTD.

JIPC Rep.:

Akinori KanasugiSaitama University

DAC Rep:

Fumiyasu HiroseFujitsu Laboratories Ltd.

ASP-DAC ’98 SECRETARIAT:c/o CONVEX Inc.,Ichijoji Bldg., 2-3-22 Azabudai, Minato-ku,Tokyo 106 JapanTel: +81-3-3589-3355Fax: +81-3-3589-3974E-mail: convex@po.iijnet.or.jp

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ASP-DAC ’98 Advisory Board Members

Takeo HashimotoSenior General Manager, SystemLSI DivisionExecutive Vice President,Semiconductor CompanySony Corporation

Tatsuo IzawaSenior Vice President, NTT

Susumu KohyamaCorporate Director and VicePresident,Deputy Group Executive,Semiconductor Group, ToshibaCorp.

Susumu KoikeDirector, Corporate SemiconductorDevelopment Division,Matsushita Electric Industrial Co.Ltd.

Heihachi MatsumotoGeneral Manager, System LSIDevelopment CenterMitsubishi Electric Corp.

Shigeo MisakaCorporate Senior ExecutiveDirector,Electronic Components and Devicebusiness,Sharp Corp.

Hisakazu MukaiFellow, Oki Electric Industry Co.,Ltd.

Hajime SasakiSenior Executive Vice President,NEC Corp.

Shigeru SatoPresident, Fujitsu Labs., Ltd.

Yasutsugu TakedaSenior Executive ManagingDirector,Member of the Board, Hitachi Ltd.

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ASP-DAC Steering Committee

Chairperson

Tatsuo OhtsukiDepartment of Electronics, Information &Communication EngineeringWaseda University3-4-1 Okubo, Shinjuku Tokyo 169, JapanTel: +81-3-5286-3387Fax: +81-3-3203-9184E-mail: ohtsuki@ohtsuki.comm.waseda.ac.jp

Vice Chairperson

Fumiyasu HiroseFujitsu Laboratories Ltd.E-mail: hirose@flab.fujitsu.co.jp

Secretary

Tsuneo NakataFujitsu Laboratories Ltd.E-mail: nakata@flab.fujitsu.co.jp

ASP-DAC ’98 General Chair

Tokinori KozawaSemiconductor Technology AcademicResearch Center (STARC)

ASP-DAC ’98 Secretary

Toshihiro HattoriHitachi, Ltd.

ASP-DAC ’98 Technical Program Co-Chairs

Shuji TsukiyamaChuo University

Philip ChanThe Hong Kong University of Science andTechnology

IEICE TGCAS Chair

Akinori NishiharaTokyo Institute of Technology

IEICE TGVLD Chair

Hitoshi KitazawaNTT Corporation

IEICE TGICD Chair

Gensuke GotoFujitsu Laboratories Ltd.

IPSJ SIGDA Chair

Kenji YoshidaToshiba Corporation

JIPC Representative

Kunihiro AsadaUniversity of Tokyo

ACM SIGDA Representative

Nikil DuttUniversity of California at Irvine

IEEE CAS Representative

Graham R. HellestrandUniversity of New South Wales

DAC Representative

Basant R. ChawlaLucent Technologies

EDA Techno Fair Chair

Yoshitada FujinamiNEC Corporation

EIAJ EDA TC Rep.

Sagoro HazamaFujitsu Limited

International Members

Xian-Long HongTsinghua University, Beijing

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Chong-Min KyungKorea Advanced Institute of Science andTechnology

Hon-Wai LeongNational University of Singapore

Youn-Long Steve LinTsing Hua University, Hsin-Chu

Sunil D. SherlekarSilicon Automation Systems (India) Pvt. Ltd.

David SkellernMacquarie University

Omar WingThe Chinese University of Hong Kong

Ellen J. YoffaIBM Corporation

Qianling ZhangFudan University, Shanghai

Advisory Members (Industries)

Kazuyuki HirakawaOki Electric Industry Co., Ltd.

Eisaburo IwamotoSony Corporation

Takashi KambeSharp Corporation

Osamu KaratsuAdvanced Telecommunication ResearchInstitute International

Nobuaki KawatoFujitsu Laboratories of America

Shigeo KuninobuMatsushita Electric Industrial Co., Ltd.

Masami MasuyamaSeiko Instruments Inc.

Shin’ichi MuraiMitsubishi Electric Corporation

Fusao WadaZuken Inc.

Kenji YoshidaToshiba Corporation

Takeshi YoshimuraNEC Corporation

Advisory Members (Academia)

Toshiro AkinoKinki University

Hideo FujiwaraNara Institute of Science and Technology

Masaharu ImaiOsaka University

Michitaka KameyamaTohoku University

Hiroaki KuniedaTokyo Institute of Technology

Yoshikazu MiyanagaHokkaido University

Yukihiro NakamuraKyoto University

Hidetoshi OnoderaKyoto University

Tsutomu SasaoKyushu Institute of Technology

Isao ShirakawaOsaka University

Kazuhiro UedaShibaura Institute of Technology

Shin’ichi WakabayashiHiroshima University

Masao Yanagisawa (formerly Sato)Waseda University

Hiroto YasuuraKyushu University

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General Chair’s Message

Welcome to ASP-DAC’98

This is the third meeting of the Asia and South Pacific Design Automation Conference(ASP-DAC’98) with EDA Techno Fair ’98 to be held in the Pacifico Yokohama, Japan.This conference provides an international forum for researchers and engineersworldwide in electronic systems, VLSI design, and CAD/EDA. ASP-DAC is regardedas a sister conference of DAC in the U.S.

A recent topic in design technology has been the Design Productivity Crisis in the deepsubmicron era. In order to overcome this difficulty it will be essential to have interactionbetween different communities, that is, academia, industry, electronic system and circuitdesign engineers, and EDA (Electronic Design Automation) developers.

ASP-DAC’98 will facilitate technical interchanges among people in these variouscommunities and thereby advances the state of the art in VLSI design and designautomation.

Keynote speakers will present topics and strategies for VLSI design in the deepsubmicron era. Gady Singer, general manager of design technology at Intel, will talkabout the strategy for breaking through the design difficulties that will be encounteredin developing general-purpose microprocessors, including the Pentium series, in future.Hisashi Yamada, Chief Fellow of Technology of Toshiba, will talk about his group’sexperience in developing a DVD multimedia system. Anantha Chandrakasan will talkabout design methodologies for low power LSI such as dynamically variable supply,multiple and variable threshold CMOS, self-powered systems, custom vs.programmable implementations, etc.

The program, decided by the Technical Program Committee (TPC), consists of technicalsessions, special sessions, and panel sessions. The university design contest is the secondtrial to encourage academics to enter VLSI implementation. Prof. Onodera has selectedfive one-day tutorials on Tuesday. Topics are design for merging logic and DRAM, high-performance system LSI design, deep submicron design, co-design with IP core, andlow-power design.

EDA Techno Fair’98 (the fifth of these annual premier Japanese EDA shows) is collocatedwith ASP-DAC’98. Exhibitors are companies including EDA vendors, EDA developers,and ASIC vendors.

I would like to thank all the members of the steering committee, organizing committee,technical program committee, and university design contest committee for theirvoluntary services.

I hope you enjoy the conference and the various events to be held in conjunction with it.

Tokinori KozawaGeneral Chair, ASP-DAC’98

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ASP-DAC ’98 Technical Program Committee

Co-Chairs:

Shuji TsukiyamaChuo UniversityDept. ISC, Chuo University1-13-27 Kasuga, Bunkyo-ku,Tokyo 112, JapanPhone: +81-3-3817-1871FAX: +81-3-3817-1847Email: tsuki@elect.chuo-u.ac.jp

Philip ChanHong Kong University of Science andTechnologyDepartment of Electrical andElectronic EngineeringHong Kong University ofScience and TechnologyClear Water Bay, Hong KongPhone: +852-2358-7041FAX: +852-2358-1485Email: eepchan@ee.ust.hk

Vice-Chair:

Hiroaki KuniedaTokyo Institute of TechnologyDept. of Electrical andElectronic EngineeringTokyo Institute of Technology2-12-1 Ookayama, Meguro-ku,Tokyo 152, JapanPhone: +81-3-5734-2574FAX: +81-3-5734-2842Email: kunieda@ss.titech.ac.jp

Secretaries:

Kazutoshi WakabayashiC & C Research Labs.NEC Corporation4-1-1 Miyazaki, Miyamae-ku,Kawasaki, Kanagawa 216, JapanPhone: +81-44-856-2134FAX: +81-44-856-2235Email: wakaba@sbl.cl.nec.co.jp

Kazuhito ItoDepartment of Electrical andElectronic SystemsSaitama University255 Shimookubo, Urawa,Saitama 338, JapanPhone: +81-48-858-3731FAX: +81-48-855-0940Email: kazuhito@elc.ees.saitama-u.ac.jp

TPC Members:

Hideharu AmanoKeio Univ.

Kunitoshi AonoMatsushita Electric Industrial Co., Ltd.

Hideki AsaiShizuoka Univ.

M. BalakrishnanIndian Inst. of Technology, Delhi

Neil W. BergmannQueensland Univ. of Technology

Jinian BianTsinghua Univ.

Tapan J. ChakrabortyBell Labs

Kwang-Ting (Tim) ChengUniv. of California, Santa Barbara

Ying S. CheungUniv. of Hong Kong

Mely Chen ChiCCL/ITRI

Shih-Chieh ChangNational Chung-Cheng Univ.

Henk CorporaalDelft Univ. of Technology

Zdzislaw CzarnulToshiba Corp.

Hiroshi DateInst. of Systems & Information Technologies/Kyushu

Masato EdahiroNEC Corp.

Kunihiro FujiyoshiTokyo Univ. of Agriculture & Technology

Masahiro FukuiMatsushita Electric Industrial Co., Ltd.

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Tetsuya FujimotoSharp Corp.

Hisanori FujisawaFujitsu Labs. Ltd.

Raanan D. GewirtzmanIBM Corp.

Sandeep K. GuptaUniv. of Southern California

Soonhoi HaSeoul National Univ.

Kiyoharu HamaguchiOsaka Univ.

Reiner W. HartensteinUniversitaet Kaiserslautern

Kazumi HatayamaHitachi Ltd.

Ikuo HaradaNTT Corp.

Terumine HayashiMie Univ.

Graham R. HellestrandUniv. of New South Wales

John HillawiDA Solutions Ltd.

Hiromi HiraishiKyoto Sangyo Univ.

Xianlong HongTsinghua Univ.

Tomoo InoueNara Inst. of Science and Technology

Nagisa IshiuraOsaka Univ.

Kazuhiko IwasakiTokyo Metropolitan Univ.

Jawahar JainFujitsu Labs. of America

David M. JohnstoneCanon Information Systems ResearchAustralia

Wen-Ben JoneNational Chung-Cheng Univ.

Seiji KajiharaKyushu Inst. of Technology

Kaoru KawamuraFujitsu Labs. Ltd.

Beomsup KimKorea Advanced Inst. of Science andTechnology

Seok-Yoon KimSoong Sil Univ.

Hitoshi KitazawaNTT Corp.

Shinji KimuraNara Inst. of Science and Technology

Hideaki KobayashiKnowledge Based Silicon Corp.

Tetsushi KoideHiroshima Univ.

Hisao KoizumiMitsubishi Electric Corp.

Stanley J. KrolikoskiCadence

Yuji KukimotoUniv. of California, Berkeley

Wolfgang KunzUniv. of Potsdam

Hajime KubosawaFujitsu Labolatories

Feipei LaiNational Taiwan Univ.

Tak-Kwan LeeChinese Univ. of Hong Kong

Gueesang LeeChonnam National Univ.

K. J. LeeNational Cheng-Kung Univ.

Howard LuongHong Kong Univ. of Science and Technology

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Sharad MalikPrinceton Univ.

Yossi MalkaIBM Corp., Israel

Peter MarwedelUniv. of Dortmund

Hiroshi MatsumotoNEC Corp.

Yusuke MatsunagaFujitsu Labs. Ltd.

Eiji MasudaToshiba Corp.

Kazuhiko MatsumotoHitachi Ltd.

Yinghua MinChinese Academy of Sciences

Shin-ichi MinatoNTT Corp.

Yukiya MiuraTokyo Metropolitan Univ.

Toshiaki MiyazakiNTT Corp.

Mitiko Miura-MattauschHiroshima Univ.

Mutsumi MitarashiOki Electric Industry Co.,Ltd.

Seijiro MoriyamaToshiba Corp.

Vasily G. MoshnyagaKyoto Univ.

Akira NagoyaNTT Corp.

Tsuneo NakataFujitsu Labs. Ltd.

Takashi NanyaUniv. of Tokyo

Kenji NumataToshiba Corp.

Hiroyuki OchiHiroshima City Univ.

Kiyoshi OguriNTT Corp.

Naohisa OhtaNTT Corp.

Hidetoshi OnoderaKyoto Univ.

Takao OnoyeOsaka Univ.

Sandeep PageyCadence Design Systems India

Rubin A. ParekhjiTexas Instruments, India

Manish PandeyCarnegie Mellon Univ.

Keshab K. ParhiUniv. of Minnesota

Miodrag PotkonjakUniv. of California, Los Angels

Changge QiaoTsinghua Univ.

Jan M. RabaeyUniv. of California, Berkeley

Tsutomu SasaoKyushu Inst. of Technology

Hiroshi SawadaNTT Corp.

Hyunchul ShinHanYang Univ.

Yoichi ShiraishiGunma Univ.

Toru ShonaiHitachi Ltd.

Toshiyuki ShibuyaFujitsu Labs. Ltd.

Naoyuki ShigyoToshiba Corp.

Fumio SuzukiMitsubishi Electric Corp.

Atsushi TakaharaNTT Corp.

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Pusan TangFudan Univ.

Shigetaka TakagiTokyo Inst. of Technology

Koichiro TakayamaFujitsu Labs. Ltd.

Yoshinori TakeuchiOsaka Univ.

Nozomu TogawaWaseda Univ.

Masahiko ToyonagaMatsushita Electric Industrial Co., Ltd.

Jiarong TongFudan Univ.

Toru ToyabeToyo Univ.

Chi-ying TsuiHong Kong Univ. of Science and Technology

Akihiro TsutsuiNTT Corp.

Tsuneo TsukaharaNTT Corp.

Kazuhiro UedaShibaura Inst. of Technology

Nachiket UrdhwaresheSilicon Automation Systems

Ad J. van de GoorDelft Univ. of Technology

G. VenkateshSilicon Automation Systems

Shin’ichi WakabayashiHiroshima Univ.

Takahiro WatanabeYamaguchi Univ.

Yosinori WatanabeCadence European Labs.

Jinn-Shyan WangNational Chung-Cheng Univ.

Xiaoqing WenAkita Univ.

C.-K. WongChinese Univ. of Hong Kong

Hei WongCity Univ. of Hong Kong

Allen C.-H. WuTsing Hua Univ.

Angus WuCity Univ. of Hong Kong

Cheng-Wen WuTsing Hua Univ.

Yu-Liang WuChinese Univ. of Hong Kong

Hans-Joachim WunderlichUniv. of Stuttgart

Hongxi XueTsinghua Univ.

Xiaolang YanHangzhou Inst. of Electronics Engineering

Shoichiro YamadaOsaka City Univ.

Masayuki YamaguchiSharp Corp.

Chingwei YehNational Chung-Cheng Univ.

Tokumi YokohiraOkayama Univ.

Goichi YokomizoHitachi Ltd.

Tomohiro YonedaTokyo Inst. of Technology

Takeshi YoshimuraNEC Corp.

Michio YotsuyanagiNEC Corp.

Kyoji YuyamaHitachi Ltd.

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Technical Program Co-Chairs’ Message

On behalf of the Technical Program Committee, we would like to welcome you to ASP-DAC ’98,which is the third, but the second after changing biennial to annual, in a series of internationalconferences to be held in Asia and South Pacific regions concerning the fields of designautomation and design methodology of electronic systems. This year, we received more than120 good papers from around 12 countries. The high technical standard of the submitted papersreflects that researchers and engineers in the fields have begun to recognize this annualconference as an important forum for interchanging their ideas and opinions.

In order to further stimulate the discussion between system/circuit designers and designautomation researchers, we have tried to emphasize design methodology more than the lastyear, and hence the "Area of Interest" in the Call for Papers were divided into two bigcategories; "Design Technology" and "Design Automation Technology."

The Technical Program Committee consisting of experts from industry and academia aroundthe world was organized into 9 groups according to the categories of the Area of Interest. Eachgroup conducted the peer review and discussion for evaluating and selecting the submittedpapers. Thanks to their great efforts, 74 regular and short papers were accepted and arranged inthe three regular tracks of the technical program.

Similarly to the last ASP-DAC, the technical program is structured under four parallel tracks;three regular tracks and one special track. Special sessions composed of invited talks and panelsessions are incorporated into the special track, together with University LSI Design Contestpresentation and poster. These invited talks and panels are selected carefully by the TechnicalProgram Committee from the hot topics in Design Technology and Design AutomationTechnology, and features the conference. Since the embedded tutorials were well received andattended last year, seven embedded tutorials are put into the regular tracks in order to introducethe state of the art. Please attend the sessions you are interested in and enjoy stimulatingdiscussions about Design Technology and Design Automation Technology.

Finally, we would like to take this opportunity to thank all individuals, in particular, all authors,members of the Technical Program Committee, and session co-chairs. Without theircontributions and dedications, the conference could not maintain the high level of quality. Webelieve that due to their efforts, ASP-DAC is establishing its position in thefastest developing area of the high-technology world.

Shuji Tsukiyama and Philip Chan

Technical Program Co-Chairs, ASP-DAC ’98

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Best Paper Award CandidatesAsia and South Pacific Design Automation Conference 1998 (ASP-DAC ’98)

1A.2 Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal Communications

Kazuya Yamamoto, Takao Moriwaki, Yutaka Yoshii, Takayuki Fujii, Jun Otsuji, YoshinobuSasaki, Yukio Miyazaki, Kazuo Nishitani

2C.3 Concurrent Technology, Device, and Circuit Development for EEPROMs

U. Feldmann, R. Kakoschke, M. Miura-Mattausch, G. Schraud

3C.1 On the CSC Property of Signal Transition Graph Specifications for Asynchronous CircuitDesign

Mohit Sahni, Takashi Nanya

3C.2 Practical Synthesis of Speed-Independent Circuits Using Unfoldings

Uisok Kim, Dong-Ik Lee

5A.1 Software Licensing Models in the EDA Industry

Dinesh R. Bettadapur

5A.2 Pre-layout Delay Calculation Specification for CMOS ASIC Libraries

Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi

5B.1 A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs

Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki

8B.3 Automatic Test Generation for Linear Analog Circuits under Parameter Variations

C.-J. Richard Shi, Michael W. Tian

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University LSI Design Contest Co-Chairs’ Message

On behalf of the University LSI Design Contest Committee, we would like to welcome you tothe University LSI Design Contest. The aim of this Contest is to encourage the education andresearch on LSI design and its implementation into chips, at universities and other educationalorganizations, by providing the opportunities to present and discuss those designs at theconference. And also, a certain number of awards will be given to the designs selected fromthose presented at the conference.

Application areas, or types of circuits include, Microprocessors, Digital Signal processing,Custom Application Specific Circuits, and Analog and Mixed-Signal Circuits. Methods, ortechnologies employed in the implementation include, full custom and cell-based LSIs, gatearrays,and field programmable devices, including FPGA/PLDs.

This year, thirteen selected designs from three countries will be disclosed in Session 5D, with ashort aural presentations, followed by Q & A, using posters. Demonstrations on theachievements will also be made for some designs. Opportunities for demonstrations at EDATechnoFair’98 will be provided for the above designs.

Submitted designs were reviewed by the members of the University LSI Design ContestCommittee, based on the following criteria: (1) Reliability of design and implementation, (2)Quality of implementation, (3) Performance of the design, (4) Originality, and (5) Additionalfactors. In the selection process, emphasis were placed more on the above criteria (1) and (2). Asa result, thirteen designs were selected for the presentation at the conference.

It is our great pleasure if the design contest will contribute to the promotion of LSI design andits implementation at universities and other educational organizations. It is also our hope thatmany people in the industry will be interested in the contest.

Akihiko Morino and Chak-Kuen Wong,

Co-Chairs, University LSI Design Contest

Akinori Nishihara

Vice Chiar, University LSI Design Contest

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University LSI Design Contest Committee

Co-Chairs:

Akihiko MorinoNEC Corp.

Chak-Kuen WongThe Chinese University of Hong Kong

Vice Chair:

Akinori NishiharaTokyo Institute of Technology

Secretaries:

Mineo KanekoJapan Advanced Institute of Science andTechnology

Hiroaki HirataKyoto Institute of Technology

Members:

Yukio AkazawaNTT Electronics Corp.

Hideharu AmanoKeio Univ.

Liang-Gee ChenNational Taiwan Univ.

Howard ChenIBM

Tadayoshi (Tad) EnomotoChuo Univ.

Graham HellestrandThe Univ. of New South Wales

Akihiro HigashiFujitsu Labs. Ltd.

Nagisa IshiuraOsaka Univ.

Beomsup KimKorea Advanced Inst. of Science andTechnology

Hitoshi KitazawaNTT System Electronics Labs.

Noboru KuboSharp Corp.

Chong-Min KyungKorea Advanced Inst. of Science andTechnology

S. MadhusudhananSilicon Automation Systems Ltd.

Eiji MasudaToshiba Corp.

Yoshikazu MiyanagaHokkaido Univ.

Yasuhiro NakakuraMatsushita Electric Industrial Co., Ltd.

Yasunobu NakaseMitsubishi Electric Corp.

Keisuke OkadaMitsubishi Electric Corp.

Jan M. RabaeyUniv. of California, Berkeley

Keitaro SekineScience Univ. of Tokyo

Chandra ShekharCentral Electronics EngineeringResearch Inst. (CEERI)

Chi-ying TsuiHong Kong Univ. of Science andTechnology

Toshirou TsukadaHitachi, Ltd.

Yoshiaki UmezawaOki Electric Industry Co., Ltd.

Neil WesteMacquarie Univ.

Futao YamaguchiSONY Corp.

Kaichi YamamotoSONY Corp.

Hironori YamauchiRitsumeikan Univ.

Yoichi YanoNEC Corp.

Jun YuFudan Univ

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University LSI Design Contest Summary

Submission

Fourteen designs were submitted from four countries, Japan, Korea, China, andAustralia.�Statistics in terms of the application areas, and design methodologies are as follows:

Application Area Design MethodologyCountry Number of

Submission A D M C F/C G/A F/P

Japan 8 2 0 3 3 7 1 0

Korea 4 1 3 0 0 3 1 0

China 1 0 0 1 0 0 0 1

Australia 1 0 0 0 1 1 0 0

A: Analog, A/D Mixed, D: Digital, M: Microprocessor, and C: Custom/Appl F/C: Full Custom, G/A: Gate Array, and F/P: FPGA/PLD

Selection Process

1. Submitted designs were subjected to the reviewing by all of the committee members. Eachcommittee member was requested to fill in the review sheet, including the recommendationpoints and comments.

2. Design selection was carried out at the committee meeting held on Wednesday, October 8.Discussion on the selection/rejection of each design was carried out, based on therecommendation points and comments.

3. As a result, 13 designs were selected, and one design (#09) was rejected.4. A candidate for the Outstanding Design Award, and two candidates for Special Feature

Awards were selected.

Session Assignment

1. The session has 2 hours time slot, for easier presentation of the designs.2. Presentations will be made in a sequence of microprocessors, digital, custom, and analog.3. For each design, an aural presentation for 7 minutes, and Q&A by the use of the posters are

planned.

xviii

University LSI Design Contest Award

Recipient for Outstanding Award

"TITAC-2: An Asynchronous 32-bit Microprocessor"

Akihiro Takamura*, Masashi Imai+, Motokazu Ozawa*, Izumi Fukasaku*,Taro Fujii*, Masashi Kuwako+, Yoichiro Ueno*, and Takashi Nanya*+

* Graduate School of Information Science and EngineeringTokyo Institute of Technology, Tokyo, Japan

+ Research Center for Advanced Science and TechnologyUniversity of Tokyo, Tokyo, Japan

(Microprocessor, Cell-based LSI)

This paper describes an asynchronous microprocessor design, based on MIPS R2000microprocessor, but targeted to asynchronous circuitry for 0.5 um CMOS Standard Cell. Itsachievements include not only the world-first working large scale real microprocessor design byasynchronous circuits, but also wide range of device behavior testing to guarantee thecorrectness of the design. These design features, testing method, complexity of thedevelopment, and well-written paper clearly distinguish itself from other submitted designs.Thus, this design is worthy of the Outstanding Design Award.

Recipient for Special Feature Award

"MetaCore: A Configurable & Instruction-Level Extensible DSP Core"

Jin-Hyuk Yang, Byung-Woon Kim, Sung-Won Seo, Sang-Jun Nam,Chang-Ho Ryu, Jang-Ho Cho, and Chong-Min Kyung

Department of Electrical EngineeringKorea Advanced Institute of Science and Technology, Taejon, Korea

(Digital Signal Processing, Cell-based LSI)

In order to pursue cost-effective solutions for diversified applications, a configurable andinstruction-level extensible DSP will be useful and viable. This design proposes such a DSP corenamed MetaCore, and a platform for its development. The MetaCore has an architecture tofacilitate tuning itself to specific applications by changing a set of parameters. The developmentplatform provides retargetability to support configurability and instruction-level extensibility.The first version of MetaCore, which is a 16-bit fixed point DSP core, is realized by using 0.6 umthree level metal CMOS process, has a core size of 4.5mm x 5mm, and 50 MIPS performance.Judging from the design rule, and standard cell design methodology employed, the above dataare considered to be excellent. Above achievements demonstrate the excellent feature of thedesign as compared with other submitted designs. Thus, this design deserves a Special FeatureAward.

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Recipient for Special Feature Award

"A CMOS Smart Image Sensor LSI for Focal-Plane Compression"

Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki,Yoshiaki Tadokoro, Kenji Murata*, Shiro Doushou* and Akira Matsuzawa*

Department of Information and Computer SciencesToyohashi University of Technology

*Matsushita Electric Industrial Co. Ltd.

(Analog and Mixed-Signal Circuits, Full-Custom LSI)

A CMOS imaging array with block access function and an analog two-dimensional discretecosine transform (DCT) processor using switched capacitor circuits are implemented in onechip. Two-dimensional 8x8-point DCT is computed by repeated 1-D 8-point DCTs. SC circuitsperform 32 multiplications and 32 additions in 8-point DCT in parallel. This chip is combinedwith an adaptive A-D converter and an entropy coder to produce motion JPEG signals. Analogapproach makes it possible to reduce the power dissipation. The chip consisting of 128 x 128-pixel imager and a DCT processor is fabricated with 0.35 um CMOS. The chip size is 4.95 mm x4.95 mm and it consumes less than 20 mW. Although there are some contribution from acompany, the original idea, circuit design and layout design come from university side. Thedesign shows the performance feasibility of analog approach, and deserves a Special FeatureAward.

xx

Keynote Address IEDA beyond 2000 - Evolution or Revolution?

Gadi Singer General Manager, Design Technology, Microprocessor Group, Intel

The keynote address will analyze future semiconductor design trends and characterize the EDAcapabilities that can help meet some of the critical design and test challenges for the year 2000and beyond. Further, the address will offer an analysis of the current state and the futuredirection of the EDA industry from four perspectives. In each area, the potential inflectionpoints will be sought, identifying where the EDA world is likely to experience radical changescompared to the evolutionary trends of the past decade. The four perspectives are -

1. Technology: Chip designs of the future will have to address ever-increasing complexity(>50M transistors), high frequencies (>2 GHz), low voltages (<1V), and surging currents(>100A). After a look at current trends, the address will examine the implications for thetools and methods needed to design and test the new generations of chips. In addition,ways to enhance the alignment between the semiconductor and EDA roadmaps will beexplored.

2. Computing: Today’s computing paradigms are based on decade-old concepts and may notbe able to meet future design complexity and design productivity needs. The address willoutline the opportunities created by the new computing/software era, including multipleCPUs, tightly integrated high horsepower workstation farms, seamless integration ofoffice and engineering applications, use of the Internet, and similar phenomena.

3. Business: The continuing consolidation of the EDA industry and new business trends, suchas the push into design services, is leading to a new set of business dynamics in theindustry. The address will examine these and other market forces (system on chip, the newage IP market) and assess the implications for the EDA industry.

4. Standards and Interoperability: The address will draw comparisons between the EDAindustry and other industries in terms of their use of standards and resultinginteroperability. A demonstration of how standards and interoperability will be one of thekeys to growing the industry and staying aligned with future design needs will bepresented. The address will also provide a brief overview of the EDA industry council'sefforts in trying to bring about greater standardization in the industry.

xxi

Keynote Address IIDVD and Role of LSI in Multi-Source Multimedia

Hisashi Yamada Toshiba Corp.

LSI has been the key technology to construct electronic systems for past 30 years. Anyinformation technology or signal processing technology has been depending on the LSItechnology at real implementation stage. Although the basic theory was established long beforethe real application of the theory, actual introduction can be predicted by estimating thehardware size of the system required for the real implementation. Since LSI progress has beenmeasured by the DRAM capacity and microprocessor computational power, we can estimatethe logic LSI through put by those LSI progress power. DVD has been proposed considering theLSI progress and it’s introduction timing was estimated from the cost estimation of the key LSIsuch as MPEG decompression LSI.

DVD is proposed as a unified media for multi-source multimedia era that provides unifiedenvironment for multi-source handling. Any software or application of information processingtechnology is depending on the LSI technology and system integration is key issue for costreduction and compact system realization.

Mainly there is two major area for role of LSI, one is performance improvement and costreduction by increasing system integration scale namely system on chip, and the other one isminiaturization and power consumption reduction by integration to realize mobile equipment.There are always trade-off between power consumption and system complexity. Usually, indigital system, system designer want to integrate more sophisticated feature into the LSI, butalways there is a definite limit for power consumption for mobile equipment. So the key issue towin the competition is how fast you can achieve system integration and low powerconsumption. Since life of a LSI is very short until that becomes mature, then continuousevolution of the integration is always required. From the environment stated above, CADtechnology becomes key issue for competition in multi-source multimedia era. More accurateand user friendly design tool is the most important for competition today.

xxii

Keynote Address III

Trends in Energy Efficient Computing

Anantha ChandrakasanMassachusetts Institute of Technology, Cambridge

Energy efficient system design requires systematic optimization at all levels of the designabstraction ranging from process technology and logic design to architectures and algorithms.Significant advances have been made in reducing the energy consumption of digital processorsover the past few years and this presentation will highlight some the recent directions in energyefficient computing.

The energy expended per operation is continually improving as the power supply voltages arescaled. Reduced device thresholds and electronic tuning techniques have enabled the aggressivescaling of power supply voltages, but the increased leakage is not acceptable for "event-driven"computation that have long idle periods. Several emerging process technologies such asMultiple and Variable threshold CMOS (bulk and SOI) have addressed the idle mode leakageproblem by providing a "knob" to dynamically adjust leakage currents; this enables high-performance during active periods and low-standby leakage. These technologies pose severalnew challenges in fabrication technology, design methodologies, and CAD tools.

In many applications, it is desirable to design digital processors that allow a trade-off betweenthe quality of service provided and the average energy consumption (e.g., trading the level ofencryption/security for energy). For such applications, there is significant energy advantage inusing an embedded power supply scheme where the voltage can be adapted based oncomputational demand. Rather than designing a system with a static supply to meet a specifictiming constraint under worst case conditions (i.e., establishing the feedback around the powerconverter to fix the output voltage), it is more energy efficient to allow the voltage to vary suchthat the timing constraints are just met at any given temperature and operating conditions; thisis accomplished by establishing the feedback around a fixed processing rate or delay. Thisapproach requires the design of high-efficiency switching regulators that have a fast transientresponse. Embedded power supply systems can minimize energy consumption under varyingtemperature, process parameters and computational workload.

Voltage scaling alone is not enough as the complexity increases and as applications that use theportable energy source require further energy reductions. The switched capacitance must beminimized by avoiding unnecessary transitions beyond what is required to implement a givenlogic function and by minimizing node capacitances. While several interesting techniques havebeen proposed and used (e.g., clock gating, transistor sizing, compilation techniques, etc.),many opportunities exist to reduce the switched capacitance by exploiting properties of specificsystems. For example, in some video applications, exploiting knowledge about signaldistributions during architecture development can save more than order of magnitude inenergy at a fixed power supply voltage. Similarly, restructuring algorithms to exploitcommunications capabilities of emerging wireless systems can save orders of magnitude inpower consumption of the energy constrained portable unit.

Session Index

Session 1A: High-Speed Design TechniquesSession 1B: Hardware/Software Codesign ISession 1C: Technology CAD for Interconnections and EnvironmentsSession 1D: Panel: Design Technology Challenges in the Design Productivity CrisisSession 2A: Combinational Logic SynthesisSession 2B: Compiler for Embedded ProcessorsSession 2C: Technology CAD for Lowest Level DesignSession 2D: Panel & Embedded Tutorial: Coupling of Synthesis and Layout: Challenges and

SolutionsSession 3A: DSP System DesignSession 3B: System SimulationSession 3C: Asynchronous Logic SynthesisSession 3D: Invited Talks: Design and EDA Road MapSession 4A: Design for TestabilitySession 4B: Model Checking: Its Basics and RealitySession 4C: Pass Transister LogicSession 4D: Panel: Upcoming Deep Sub Micron EDA Tool ProblemSession 5A: Towards New EDA StandardsSession 5B: High-Level and System-Level SynthesisSession 5C: Performance Driven LayoutSession 5D: University LSI Design ContestSession 6A: Digital PLL & Timing DesignSession 6B: Hardware/Software Codesign IISession 6C: Layout Optimization and VerificationSession 6D: Invited Talk & Embedded Tutorial: Interconnections and Packaging for High

Speed and High Frequency PCB/MCMSession 7A: High-Performance CMOS CircuitsSession 7B: Decision DiagramsSession 7C: Reconfigurable SystemsSession 7D: Panel: Asian-Pacific LSI Business in the 21st CenturySession 8A: TestingSession 8B: Analog CADSession 8C: Physical Design for FPGASession 8D: Panel & Embedded Tutorial: The Next-Generation System Level Design

LanguageSession 9A: Analog HDLSession 9B: System-Level Power MinimizationSession 9C: FloorplannningSession 9D: LSI Designs in Multimedia Era

Conference Author Index

A

Adams, P. 5A.4SAizawa, K. 5D.13PAllara, A. 5A.5SAmano, H. 5D.10P, 7C.3Ambershambi, R. 4DAmril, I. 5D.7PArivoli, T. 5D.9PAsada, K. 5D.3P, 6D.3

B

Binh, N.-N. 6B.3Barke, E. 8A.3Basu, A. 2B.1Becker, J. 1B.3Bettadapur, D. R. 5A.1Bhattacharya, B. B. 8A.2Bickerstaff, M. 5D.9PBombana, M. 5A.5SBryant, R. E. 7B.1Bushroe, R. G. 5A.4S

C

Cavalloro, P. 5A.5SChakraborty, S. 8A.2Chang, H.-C. 3A.1Chen, L.-G. 3A.1Chen, Y.-A. 7B.1Cheng, K.-T. 9B.2Chi, M. C. 7DChien, J. 1A.3Chien, R. 1A.3Cho, J.-H. 5D.4PChoi, K. 6B.2Cong, J. 2DCottrell, D. 5A.3, 5A.4S

D

Das, D. K. 8A.2DasGupta, S. 5A.4SDebnath, D. 2A.2Devgan, A. 6A.1Dey, S. 4A.1Doushou, S. 5D.11PDrechsler, R. 2A.3, 7B.2

E

Edahiro, M. 1C.3, 5C.2Edamatsu, H. 5A.2Ernst, R. 6B.1Etoh, H. 6C.3Eun, S. Y. 5D.6

F

Feldmann, U. 2C.3Fisher, P. 5A.4SFujii, Takayuki 1A.2Fujii, Taro 5D.1PFujita, G. 9D.2Fujita, M. 4B.1Fujitaka, I. 1DFujiwara, H. 4A.3Fukasaku, I. 5D.1PFunaba, S. 8B.1Furuya, M. 9C.2

G

Goto, H. 2C.2Grout, S. 5A.4SGuardiani, C. 1C.2Guo, H. 2B.3, 9B.1Gupta, R. 5A.4S

H

Ha, S. 3B.3Hagi, K. 8C.2Hama, T. 6C.3Hamamoto, T. 5D.13PHanawa, T. 5D.10PHartenstein, R. W. 1B.3Hatori, M. 5D.13PHayashi, Y. 1C.3He, J.-A. 6C.1Henkel, J. 6B.1Herz, M. 1B.3Hirano, K. 5D.8PHirose, M. 2C.1Hisaki, T. 5B.1Ho, C. 9B.2Homma, K. 5A.2

Hong, I. 5B.3, 5B.4Horeth, S. 7B.2Hsieh, E. 2DHuang, S.-Y. 9B.2Hutt, J. 2D

I

Ikeda, M. 5D.3PImai, Masaharu 6B.3, 8DImai, Masashi 5D.1PInoue, Takahide 8DInoue, Tomoo 4A.3Ishihara, T. 5D.2PIshiura, N. 2B.2Isshiki, T. 5D.7PIzumi, T. 9C.1

J

Janac, G. 2DJang, H. K. 5D.5PJeon, J. 6B.2Jiang, Y.-M. 9B.2Jiu, J.-Y. 3A.1

K

Kajitani, Y. 9C.1, 9C.2Kakimoto, M. 5A.2Kakoschke, R. 2C.3Kambe, T. 2B.2Kamei, T. 5D.10PKaratsu, O. 7DKarri, R. 5B.4Kawaguchi, H. 1C.1Kawahito, S. 5D.11P, 9D.3Keutzer, K. 4DKim, B. 6A.3Kim, B.-W. 5D.4PKim, T. H. 6A.3Kim, T.-M. 7A.2Kim, U. 3C.2Kim, Wonchan 5D.12PKim, Wonjong 6C.2Kirovski, D. 9B.3Kishimoto, T. 7DKitagawa, A. 8B.1Kitahara, T. 5C.3Kleine, U. 8B.2Kobayashi, Hideaki 6C.1Kobayashi, Hiroaki 3C.3

Kobayashi, S. 5C.2Koide, T. 9C.3Koike, Y. 5A.2Koizumi, H. 3B.2Komatsu, S. 5D.3PKoyanagi, M. 5D.8PKu, C.-W. 3A.1Kubo, M. 5C.2Kundu, S. 6A.1Kunieda, H. 5D.7PKurino, H. 5D.8PKurosaki, M. 3B.1Kuwako, M. 5D.1PKyung, C.-M. 5D.4P, 7D

L

Ledenbach, G. 3D, 4D, 5A.4SLee, C. 2B.4, 9B.3Lee, D.-I. 3C.2Lee, G. 2A.3Lee, Y.-P. 3A.1Leupers, R. 2B.1Li, S. C. 1A.3Lin, K.-L. 1A.3Lou, J. 5C.1

M

Mallis, D. 5A.3, 5A.4SMangione-Smith, W. 9B.3Marek-Sadowska, M. 2DMartin, G. 8DMarwedel, P. 2B.1Masuda, H. 2C.4Matsuzawa, A. 5D.11P, 9D.3Mehendale, M. 3A.2Meinel, C. 2A.4Mido, T. 6D.3Midorikawa, T. 5D.10PMiki, M. H. 9D.2Minami, F. 5C.3Mitsuhashi, T. 2D, 5C.3Miura-Mattausch, M. 2C.1, 2C.3Miyamoto, S. 3B.1Miyazaki, D. 5D.11PMiyazaki, T. 7C.1, 8C.3Miyazaki, Y. 1A.2Mori, K. 2C.4Moriwaki, T. 1A.2Morrell, J. 5A.3, 5A.4SMurakata, M. 5C.3Murata, Kenji 5D.11P

Murata, Koichi 1A.1Murooka, T. 8C.3

N

Nageldinger, U. 1B.3Nagoya, A. 2A.1Nakagoshi, J. 3B.1Nakamura, T. 3C.3Nakatake, S. 9C.2Nam, S.-J. 5D.4PNanya, T. 3C.1, 5D.1PNarahara, K. 1A.1Nebel, W. 5A.5SNewton, A. R. 1D, 4D, 8DNishio, S. 5C.3Nishitani, K. 1A.2

O

O’Hallaron, D. R. 7B.1Oba, N. 3C.3Oh, J. 5C.4Ohta, A. 5D.7POhtsuki, T. 5B.1, 8C.2Okuhata, H. 9D.2Ono, T. 5D.8POnodera, K. 1A.1Onoye, T. 9D.2Otsuji, J. 1A.2Otsuji, T. 1A.1Oyanagi, Y. 8B.4Ozawa, M. 5D.1P

P

Pan, J. 8C.4Pandini, D. 1C.2Parameswaran, S. 1B.1, 2B.3, 9B.1Patel, P. 5A.4SPedram, M. 2D, 2D.1, 5C.1,

5C.4, 7A.3Percival, T. 9D.1Peterson, G. 8DPotkonjak, M. M. 2B.4, 5B.3, 5B.4,

9B.3Putzke, W. 5A.5S

R

Radetzki, M. 5A.5SRaghunathan, A. 4A.1

Rikino, K. 4C.3Roy, R. K. 4A.1Ryan, R. J. 5D.9PRyu, C.-H. 5D.4P

S

Sahni, M. 3C.1Sakurai, T. 1C.1Salek, A. H. 5C.1Sano, K. 1A.1Sasaki, M. 5D.11PSasaki, T. 3C.3Sasaki, Yasuhiko 4C.3Sasaki, Yoshinobu 1A.2Sasao, T. 2A.2, 7B.3Sato, H. 2C.4Sawada, H. 2A.1Sayah, J. 5A.4SScandolara, P. 1C.2Schafer, F. 8B.2Schibuya, N. 6D.2Schraud, G. 2C.3Schreyer, T. A. 6D.1Schulz, S. E. 4D, 8DSedaghat-Maman, R. 8A.3Seo, K. 3B.2Seo, S.-W. 5D.4PShackleford, B. 3B.2Shepard, D. 1DSherlekar, S. D. 3A.2Shi, C.-J. R. 8B.3, 9A.1Shibahara, K. 2C.1Shibata, Y. 7C.3Shimizugashira, T. 5D.7PShin, G. S. 7A.2Shin, H. 6C.2Shinsha, T. 8A.1Shirakawa, I. 9D.2Silva, J. P. M. 8A.4Singer, G. 1DSinha, A. 3A.2Skellern, D. 5D.9P, 7D, 9D.1Somenzi, F. 2A.4Stankovic, R. S. 7B.3Suda, R. 8B.4Suga, M. 2C.1Sung, W. 3B.3Sunwoo, M. H. 3A.3, 5D.6PSuzuki, F. 3B.2Suzuki, K. 3B.1

T

Tabuchi, K. 5A.2Tadokoro, Y. 5D.11P, 9D.3Takahara, A. 8C.3Takahashi, A. 9C.1Takahashi, S. 1C.3Takahashi, T. 6D.2Takamura, A. 5D.1PTakano, K. 3C.3Takasaki, T. 4A.3Takeuchi, Y. 6B.3Taki, K. 4C.1Tanaka, M. 2C.1Tandai, M. 8A.1Tang, P. S. 7A.1Tang, P. 8C.1Tarui, Y. 6D.2Theobald, T. 2A.4Tian, M. W. 8B.3Togawa, N. 5B.1, 8C.2Tomiyama, H. 5B.2Tong, J. 8C.1Tse, C. K. 7A.1Tsukada, T. 8B.1Tsuneno, K. 2C.4Tsuno, M. 2C.1Tsutsui, A. 8C.3

U

Ueda, T. 5C.3Ueno, Y. 5D.1PUsami, K. 5C.3

W

Wakabayashi, S. 9C.3Wang, D. C. 9B.2Weste, N. 5D.9P, 9D.1Wolf, M. 8B.2Wong, C. K. 8C.4Wu, Q. 7A.3Wu, X. 7A.3Wu, Y.-L. 8C.4

X

Xu, Z. Y. 7D

Y

Yamaguchi, M. 2B.2Yamaguchi, S. 2C.2Yamamoto, K. 1A.2Yamashita, S. 2A.1Yanagisawa, M. 5B.1, 8C.2Yang, B. 7B.1Yang, J.-H. 5D.4PYano, K. 4C.3Yasuda, M. 3B.2Yasuura, H. 5B.2, 5D.2PYokomizo, G. 8B.1Yoo, C. 5D.12PYoon, S. H. 3A.3Yoshida, M. 5D.11PYoshii, Y. 1A.2

Z

Zeng, X. 7A.1Zhou, R. 8C.1