Bangladesh University of Engineering and Technology

Department of Electrical and Electronic Engineering

Course No.: EEE 315

Course Name: Microprocessor and Interfacing.

Term: November 2013

Assignment on: Almost Simple As Possible Computer (ASAP) Design.

( Phase-I )

Submitted to: Submitted by: Musbiha Binte Wali

Shuvro Chowdhury, Dept.: EEE

Lecturer, Level: 3 Term: 2

Dept. of EEE, BUET. Section: A

Student No.: 0906022

Date of Submission: 21/02/2014

Block diagram of ASAP-13

Block pins:

28 pins on design blocks are:

,Cp Ep , Lp , Up , Dn , Es , Lm , Rd , Wr , La , Ea , Lb , Eb , Ein , LLL , ELL , LLH , ELH , LHL, EHL , Li , Selector , 1con , 2con , alu ,

Lt , Et , Lo

CON pins:

For this design, probable 24 pins from control ROMs are:

AA, BB, LL, LH, HL, con, Lt , Et ,

,Cp Ep , Lp , Up , Dn , MM, Rd , Wr ,

Ein , Li , Sel, 1con , 2con , alu , Lo, 1NOP

Control word:

CON = AA BB LL LH HL con Lt Et Cp Ep Lp Up Dn MM Rd Wr Ein Li Sel 1con 2con alu Lo 1NOP

Some Commands interpreted by CON pins:

Command Control pins’ combination

Dn [Stack pointer value decrement] Up =0 and Dn=1

Up [Stack pointer value increment] Up =1 and Dn=0

Es [Stack pointer „send‟ enable] Up =1 and Dn=1

Lm [MAR‟s „load‟ enable] MM=1

La [Accumulator‟s „load‟ enable] AA=1 and con=1 [or Logic gates]

Ea [Accumulator‟s „output‟ enable] AA=1 and con=0

Lb [B register‟s „load‟ enable] BB=1 and con=1

Eb [B register‟s „output‟ enable] BB=1 and con=0

LLL [LL register‟s „load‟ enable] LL = 1 and con =1

ELL [LL register‟s „output‟ enable] LL=1 and con=0

LLH [LH register‟s „load‟ enable] LH=1 and con=1

ELH [LH register‟s „output‟ enable] LH=1 and con=0 [or Logic gates]

LHL [HL register‟s „load‟ enable] HL=1 and con=1

EHL [HL register‟s „output‟ enable] HL=1 and con=0

ADD (input1 + input2) [in ALU] con2 = 0 and con1 = 0

SUB (input1 – input2) [in ALU] con2 = 0 and con1 = 1

NOT [inverts input2 in ALU] con2 = 1 and con1 = 0

SHL B [in ALU] con2 = 1 and con1 = 1

Micro-instructions:

Fetch cycle:

Opcode T state Active control pins illustration

For all opcodes

T1 Ep =0 , MM=1 Program counter (PC)‟s value is sent to Memory Address

Register (MAR)

T2 Cp =1, Rd =0 , Li =1 PC‟s value incremented.

RAM‟s „read‟ pin enabled. Instruction register (IR)‟s load

pin enabled. So addressed byte is loaded on IR.

Execution cycles for different instructions:

Opcode T-state Active CON pins illustration

00

SHL B

T3 BB=1, con=0 Lt =1, Et =0

B register‟s „output‟ enabled.

B value loaded on Temporary register (temp). Then

this value reaches Arithmetic & Logic Unit (ALU).

T4 Et =0, con1=1,

con2=1, alu=1,

BB=1, con=1

ALU‟s “SHL B” command enabled. ALU‟s output

enabled. B register‟s „load‟ enabled.

So, ALU‟s output (Left shifted B) reaches B reg.

T5 1NOP = 0 Execution terminated. Controller/Sequencer will

generate T1 state in the next clock cycle.

01

MOV A, byte

T3 Ep =0 , MM=1 Program counter (PC)‟s value is sent to Memory Address

Register (MAR).

T4 Cp =1, Rd =0 ,

AA=1, con=1

PC‟s value incremented.

RAM‟s „read‟ pin enabled. A register‟s load pin enabled. So

addressed byte is loaded on A reg.

T5 1NOP = 0

02

NOT A

T3 AA=1, con=0 Lt =1, Et =0

A register‟s „output‟ enabled.

A value loaded on Temporary register (temp). Then

this value reaches Arithmetic & Logic Unit (ALU).

T4 Et =0, con2=1,

con1=0, alu=1,

AA=1, con=1

ALU‟s “NOT” command enabled. ALU‟s output

enabled. A register‟s „load‟ enabled.

So, ALU‟s output (inverted A) is loaded by A reg.

T5 1NOP = 0

03

CALL address

T3 Ep =0 , MM=1 PC‟s value is sent to MAR.

T4 Cp =1, Rd =0 ,

LL=1, con=1

PC‟s value incremented.

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Cp =1, Rd =0 ,

LH=1, con=1, Dn=1

PC‟s value incremented.

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

Stack pointer (SP)‟s value decremented.

T7 Ep =0, HL=1, con=1 The higher byte of PC‟s value is loaded by HL register.

T8 Up =1 , Dn=1, MM=1 SP‟s value is sent to MAR.

T9 HL=1, con=0, Wr =0,

Dn=1

HL register‟s „output‟ enabled. RAM‟s „write‟ pin

enabled. HL‟s value is loaded as the addressed byte on RAM.

SP‟s value decremented.

T10 Up =1 , Dn=1, MM=1 SP‟s value is sent to MAR.

T11 Ep =0, Wr =0 The lower byte of PC‟s value is loaded as the addressed

byte on RAM.

T12 LL=1, LH=1, con=0,

Lp =0

Both LL and LH registers‟ „output‟ enabled. PC‟s

„load‟ pin enabled. So PC loads that 16 bits from LL & LH.

T13 1NOP = 0

04

IN [address]

T3 Ep =0 , MM=1 PC‟s value is sent to MAR.

T4 Cp =1, Rd =0 ,

LL=1, con=1

PC‟s value incremented.

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Cp =1, Rd =0 ,

LH=1, con=1

PC‟s value incremented.

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

T7 LL=1, LH=1, con=0,

MM=1

Both LL and LH registers‟ „output‟ enabled. MAR‟s

„load‟ pin enabled. So MAR loads that 16 bits from LL &

LH.

T8 Wr =0, Ein =0 Input register‟s „output‟ enabled. RAM‟s „write‟ pin

enabled. So input byte is written as the addressed byte

on RAM.

T9 1NOP = 0

05

POP [address]

T3 Up =1 , Dn=1, MM=1 SP‟s value is sent to MAR.

T4 Rd =0 , LL=1, con=1, Up =1

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

SP‟s value incremented.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Rd =0 , LH=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

PC‟s value incremented.

T7 HL=1, con=1 LH register‟s „output‟ pin is enabled using logic gate

(~(POP&T7)). HL register‟s load pin enabled using control

pins. So, LH‟s byte is transferred to HL.

T8 Ep =0 , MM=1 PC‟s value is sent to MAR.

T9 Rd =0 , LH=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

PC‟s value incremented.

T11 LH=1, HL=1,

con=0, MM=1

Both LH and HL registers‟ „output‟ enabled. MAR‟s

„load‟ pin enabled. So MAR loads that 16 bits from HL &

LH.

T12 Wr =0, LL=1, con=0 LL register‟s „output‟ enabled. RAM‟s „write‟ pin

enabled. So LL‟s byte is written as the addressed byte

on RAM.

T13 1NOP = 0

06

MOV B, [address]

T3 Ep =0 , MM=1 PC‟s value is sent to MAR.

T4 Rd =0 , LL=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

PC‟s value incremented.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Rd =0 , LH=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

PC‟s value incremented.

T7 LL=1, LH=1, con=0,

MM=1

Both LL and LH registers‟ „output‟ enabled. MAR‟s

„load‟ pin enabled. So MAR loads that 16 bits

T8 Rd =0 , BB=1, con=1 RAM‟s „read‟ pin enabled. B register‟s load pin enabled. So

addressed byte is loaded on B reg.

T9 1NOP = 0

07

RET

T3 Up =1 , Dn=1, MM=1 SP‟s value is sent to MAR.

T4 Rd =0 , LL=1, con=1, Up =1

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

SP‟s value incremented.

T5 Up =1 , Dn=1, MM=1 SP‟s value is sent to MAR.

T6 Rd =0 , LH=1, con=1, Up =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

SP‟s value incremented.

T7 LL=1, LH=1, con=0,

Lp =0

Both LL and LH registers‟ „output‟ enabled. PC‟s

„load‟ pin enabled. So PC loads that 16 bits from LL & LH.

T8 1NOP = 0

08

CMP B, [address]

T3 Ep =0 , MM=1 PC‟s value is sent to MAR.

T4 Rd =0 , LL=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

PC‟s value incremented.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Rd =0 , LH=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

PC‟s value incremented.

T7 LL=1, LH=1, con=0,

MM=1

Both LL and LH registers‟ „output‟ enabled. MAR‟s

„load‟ pin enabled. So MAR loads that 16 bits

T8 Rd =0 , T=1, con=1 RAM‟s „read‟ pin enabled. Temporary register (Temp)‟s

load pin enabled. So addressed byte is loaded on Temp.

T9 BB=1, T=1, con=0, B‟s value to ALU as input1.

[address] value to ALU as input2.

T10 con2 = 0, con1 = 1,

alu=1

SUB command to ALU. Flags updated.

T11 1NOP = 0

09

OUT B

T3 BB=1, con=0, Lo=1 B register‟s „output‟ enabled.

B value loaded on output register & hex display.

T4 1NOP = 0

0A

PUSH B

T3 Dn=1 SP‟s value decremented.

T4 Up =1 , Dn=1, MM=1 SP‟s value is sent to MAR.

T5 Wr =0, BB=1, con=0 B register‟s „output‟ enabled. RAM‟s „write‟ pin

enabled. So B‟s byte is written as the addressed byte

on RAM.

T6 1NOP = 0

0B

ADD A, B

T3 BB=1, con=0 Lt =1, Et =0

B register‟s „output‟ enabled.

B value loaded on Temporary register (temp). Then

this value reaches Arithmetic & Logic Unit (ALU).

T4 Et =0, AA=1, con=0 A register‟s „output‟ enabled.

So, both A and B values reach ALU.

T5 con2=0, con1=0,

alu=1, AA=1,con=1

ALU‟s “ADD” command enabled. ALU‟s output

enabled. A register‟s „load‟ enabled.

T6 1NOP = 0

0C

JA address

T3 Ep =0 , MM=1 PC‟s value is sent to MAR.

T4 Rd =0 , LL=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

PC‟s value incremented.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Rd =0 , LH=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

PC‟s value incremented.

T7 BB=1, con=0 Lt =1, Et =0

B register‟s „output‟ enabled.

B value loaded on Temporary register (temp). Then

this value reaches Arithmetic & Logic Unit (ALU).

T8 Et =0, AA=1, con=0 A register‟s „output‟ enabled.

So, both A and B values reach ALU.

T9 Jump selector, sel=1 If jump condition fulfilled, NOP =1, otherwise NOP =0

(as soon as NOP =0, execution terminated)

T10 If NOP =1, then LL=1,

LH=1, con=0, Lp =0

Both LL and LH registers‟ „output‟ enabled. PC‟s

„load‟ pin enabled. So PC loads that 16 bits from LL & LH.

T11 1NOP = 0

0D

HLT

T3 1NOP = 0

0E

SUB A, [address]

T3 Ep =0 , MM=1 PC‟s value is sent to MAR.

T4 Rd =0 , LL=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

PC‟s value incremented.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Rd =0 , LH=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

PC‟s value incremented.

T7 LL=1, LH=1, con=0,

MM=1

Both LL and LH registers‟ „output‟ enabled. MAR‟s

„load‟ pin enabled. So MAR loads that 16 bits

T8 Rd =0 , T=1, con=1 RAM‟s „read‟ pin enabled. Temporary register (Temp)‟s

load pin enabled. So addressed byte is loaded on Temp.

T9 AA=1, T=1, con=0, A‟s value to ALU as input1.

[address] value to ALU as input2.

T10 con2 = 0, con1 = 1,

alu=1, AA=1, con=1

SUB command to ALU. Flags updated.

ALU‟s output enabled. A register‟s „load‟ enabled.

T11 1NOP = 0

0F

XCHG [address],A

T3 Ep =0 , MM=1 PC‟s value is sent to MAR.

T4 Rd =0 , LL=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LL register‟s load pin enabled.

So addressed byte is loaded on LL reg.

PC‟s value incremented.

T5 Ep =0 , MM=1 PC‟s value is sent to MAR.

T6 Rd =0 , LH=1, con=1, Cp =1

RAM‟s „read‟ pin enabled. LH register‟s load pin enabled.

So addressed byte is loaded on LH reg.

PC‟s value incremented.

T7 LL=1, LH=1, con=0,

MM=1

Both LL and LH registers‟ „output‟ enabled. MAR‟s

„load‟ pin enabled. So MAR loads that 16 bits

T8 Rd =0 , LL=1, con=1 RAM‟s „read‟ pin enabled. LL register (Temp)‟s load pin

enabled. So addressed byte is loaded on LL.

T9 Wr =0, AA=1, con=0 A register‟s „output‟ enabled. RAM‟s „write‟ pin

enabled. So A‟s byte is written as the addressed byte

on RAM.

T10 LL=1, con=0 LL register‟s „output‟ enabled. Accumulator‟s „load‟

enabled using logic gates (XCHG&T10).

T11 1NOP = 0

For any other

opcode,

T3 1NOP = 0 Execution terminated. Controller/Sequencer will

generate T1 state i.e. new Fetch cycle in the next

clock cycle.