arm winter sem

8/12/2019 ARM Winter Sem

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1TM

T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D

ARM Advanced RISC Machines

Advanced RISC Machines


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3TM

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ARM Partnership Model


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4TM

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ARM Powered Products


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History of the ARM Processor

ARM1 ,ARM2 .. ARM 7

ARM9, ARM10 ,ARM11

CORTEX


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6TM

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The ARM CoreWhat is meant by the core?

The core is the processing unit or thecomputing engine.

It has all the computing power, and thisaspect is decided by the architecture,which represents the basic design of theprocessor.


7/1127TM 7T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D

ARM provides hard and soft views to licenceesRTL and synthesis flowsGDSII layout

Licencees have the right to use hard or soft views of the IPsoft views include gate level netlistshard views are DSMs

OEMs must use hard viewsto protect ARM IP

Intellectual Property



THE RISC ARCHITECTURE

These apply to most of the instructionsof ARM, but

not necessarily to all.

i) Instructions are of the same size, thatis, 32 bits

ii) Instructions are executed in one cycleiii) Only the load and store instructionsaccess memory



The ARM Microcontroller

It is ARM core with peripherals added toit.



Features of ARM which make it special

Data bus width

Computational capability

Low PowerPipelining

Multiple Register instructionsDSP Enhancements



ARCHITECTURE

A large Uniform Register File

Load Store Architecture

Uniform and Fixed Length instructions

Good speed and low power consumption

High Code density



ENHANCEMENT FROM RISC

Control over ALU and shifter over everydata processing instructions to maximizetheir usage

Auto increment and auto decrementaddressing modes

Multiple load store instructions

Conditional execution of instruction tomaximize throughput



Data items are placed in register fileInstructions use two source registersand single destination register

Barrel shifter can preprocess the databefore going to ALU

Increment/Decrement logic updateregister content to provide sequentialaccess independent of ALU

Core Data Path : Overview


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General purpose registers either hold data or Address

All registers:32 bit

In user mode 16 data registers and 2 status registersare visible

Data registers r0-r15

r13,r14,r15 :special functions

r13 : Stack pointerr14 : Link registerr15 :PC

REGISTERS


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23TM 23T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D

When the processor is executing in ARM state: All instructions are 32 bits wide All instructions must be word alignedTherefore the pc value is stored in bits [31:2] with bits [1:0] undefined (asinstruction cannot be halfword or byte aligned).

When the processor is executing in Thumb state: All instructions are 16 bits wide All instructions must be halfword alignedTherefore the pc value is stored in bits [31:1] with bit [0] undefined (asinstruction cannot be byte aligned).

When the processor is executing in Jazelle state: All instructions are 8 bits wideProcessor performs a word access to read 4 instructions at once

Program Counter (r15)


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Data Alignment


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Data Alignment

For word (32-bit ) the specified address

have its least significant 2 bits as 0For half word (16-bit ) the specifiedaddress have its least significant bit as 0


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CPSR :Current program Status register

SPSR : Saved Program Status register

STATUS REGISTERS


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Program Status Registers

Condition code flagsN = Negative result from ALUZ = Zero result from ALUC = ALU operation Carried outV = ALU operation o Verflowed

Sticky Overflow flag - Q flag Architecture 5TE/J onlyIndicates if saturation has occurred

J bit Architecture 5TEJ onlyJ = 1: Processor in Jazelle state

Interrupt Disable bits.I = 1: Disables the IRQ.F = 1: Disables the FIQ.

T Bit Architecture xT onlyT = 0: Processor in ARM stateT = 1: Processor in Thumb state

Mode bitsSpecify the processor mode

2731

N Z C V Q

28 67

I F T mode

1623 815 5 4 024

f s x c U n d e f i n e dJ


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Processor mode determine Access rights to CPSR

Which registers are active

Each processor mode is eitherPrivileged : Full read write access to the CPSR

Non-Privileged : Only read access to the control fieldof CPSR but read write access to conditional flags

Processor Modes


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Processor Modes

The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run

FIQ : entered when a high priority (fast) interrupt is raised

IRQ : entered when a low priority (normal) interrupt is raised

Supervisor : entered on reset and when a Software Interruptinstruction is executed

Abort : used to handle memory access violations

Undef : used to handle undefined instructions

System : privileged mode using the same registers as user mode


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Register File contains in all 37 registers20 registers are hidden from program at different timesThese registers are called Bank ed Regis ters

Banked Registers are available onlywhen the processor in a particular mode

Processors Mode other than system mode have a setof banked register that are subset of 16 registersMaps one-to-one onto a user mode register

Banked Registers


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r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

FIQ IRQ SVC Undef Abort

User Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

Current Visible Registers

Banked out Registers

FIQ IRQ SVC Undef Abort

r0

r1

r2

r3

r4

r5

r6

r7

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr



User IRQ SVC Undef Abort

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

FIQ Mode IRQ Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr



User FIQ SVC Undef Abort

r13 (sp)

r14 (lr)

Undef Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr



User FIQ IRQ SVC Abort

r13 (sp)

r14 (lr)

SVC Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr



User FIQ IRQ Undef Abort

r13 (sp)

r14 (lr)

Abort Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr



User FIQ IRQ SVC Undef

r13 (sp)

r14 (lr)

The ARM Register Set


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Register Organization Summary

User moder0-r7,

r15,and

cpsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

FIQ

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)r15 (pc)

cpsr

r0r1

r2

r3

r4

r5

r6

r7

User

r13 (sp)

r14 (lr)

spsr

IRQ

User mode

r0-r12,r15,

andcpsr

r13 (sp)

r14 (lr)

spsr

Undef

User mode

r0-r12,r15,

andcpsr

r13 (sp)

r14 (lr)

spsr

SVC

User mode

r0-r12,r15,

andcpsr

r13 (sp)

r14 (lr)

spsr

Abort

User mode

r0-r12,r15,

andcpsr

Thumb stateLow registers

Thumb stateHigh registers

Note: System mode uses the User mode register set


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SPSR present in every privileged modeexcept system mode

Save the state of CPSR when theprivileged mode is entered so that theuser state is fully restored when theprocess is resumed

SPSR


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INTERRUPT VECTOR TABLE


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36TMT H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D

Programming with Assemblyand C .


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Data Formats


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Instruction Set


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Manipulate data within registersMOVE instructions

Arithmetic Instructions

Logical instructionsComparison Instructions

Suffix S on data processing instructions

updates flags in CPSR

Data processing Instructions


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Operands are 32-bit wide come fromregisters or specified as literals in the

instruction itselfSecond operand placed in ALU via Barrelshifter

Data processing Instructions


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MOV and MVN-Examples


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Shift and Rotate


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Combining Mov and Shift


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Conditional Execution


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h


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Arithmetic Instructions


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L i l I i


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Logical Instructions


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C I t ti


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Compare Instructions

M lti l I t ti


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Multiply content of a pair of registers

Long multiply generates 64 bit result

MUL r0,r1,r2Contents of r1 and r2 multiplied and put in r0

UMULL r0,r1,r2,r3Unsigned long multiply with result stored inr0 and r1

Multiply Instructions

Multiplication


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Multiplication

Multiplication Examples


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Multiplication -Examples

Multiply and Accumulate


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Result of multiplication can beaccumulated with content of anotherregister

MLA Rd ,Rm,Rs,RnRd =(Rm*Rs)+Rn

UMLAL Rdlo,Rdhi,Rm,Rs[Rdlo,Rdhi] = [Rdlo,Rdhi,]+ (Rm*Rs)

Multiply and Accumulate


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Directives AREA and ENTRY-


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Examples

General Structure of an assembly


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Language Line

Directives for Defining data


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Directives for Defining data

The EQU directive Examples


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The EQU directive -Examples

Constants allowed


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Constants allowed

The RN directive-for naming


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registers

Assembly Programs


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Assembly Programs

Solution


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Solution

Branch Instructions


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Branch Instructions

Branch instruction usage -


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examples


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Division by repeated subtraction


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Division by repeated subtraction

Subroutines/Procedures using the Link register


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There is a form of the branch instruction

which is BL standing forBranch and Link.

When a BL instruction is encountered,the PC value is changed to that of thetarget, but the old PC value is copied tothe LR register.

At the end of the procedure, the LR valuecan be copied back to the PC.


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Solution


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Solution

Loading constants-immediated


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mode

Constant specified in the instruction to becopied to register or used as an operand

MOV r1,#0x7867

ADD r1,r2,#567

It is thus apparent that we cant have a 32 -bit

constant embedded in the instruction .

Loading constants


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Loading constants

So then w hat is th e maximu m s ize of theco ns tant tha t can b e us ed in th eim m ediate m od e?

We would like to be able to useimmediate constants as large as 32 bits.

ARM uses an ingenious technique, the

idea being the use of rotation of a smallnumber to generate a large number.

Using the Barrel Shifter:Th S d O d


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The Second Operand

* Immediate value

8 bit number

Can be rotated right throughan even number of positions.

Assembler will calculaterotate for you from constant.

Register, optionally withshift operation applied.

Shift value can be eitherbe:

5 bit unsigned integerSpecified in bottom byteof another register.

Operand 1

Result

ALU

Barrel

Shifter

Operand 2


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Mechanism


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12 bit for operand 2

12 bit modified as 8 bit immediate constand 4 bit rotate operator

Maximum possible rotation 32 bits,hence4bit rotate operand multiplied by 2 andthen rotated

8 bit shifted by even number positions8 bit will become 32 bit during dataprocessing

Generating a 32 bit constanti t ti


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using rotation


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Second Operand :Immediate Value (2)


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Immediate Value (2)This gives us:

0 - 255 [0 - 0xff]

256,260,264,..,1020 [0x100-0x3fc, step 4, 0x40-0xffror 30]1024,1040,1056,..,4080 [0x400-0xff0, step 16, 0x40-0xff ror 28]4096,4160, 4224,..,16320 [0x1000-0x3fc0, step 64, 0x40-0xff ror 26]

These can be loaded using, for example:MOV r0, #0x40, 26 ; => MOV r0, #0x1000 (ie 4096)

To make this easier, the assembler will convert to this form for usif simply given the required constant:

MOV r0, #4096 ; => MOV r0, #0x1000 (ie 0x40 ror 26)

The bitwise complements can also be formed using MVN:MOV r0, #0xFFFFFFFF ; assembles to MVN r0, #0

If the required constant cannot be generated, an error willbe reported.

Load Store Instructions


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Transfers data between memory andprocessor registersSingle register transfer (Signed andunsigned words, half-words and bytes)

Multiple register transfer between memoryand processor in a single instruction

SWAP

swap content of a memory location withregister


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More addressing modes


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Scaled Address is calculated using base register andbarrel shifter

Pre and post indexing

Pre index with write back : LDR r0,[r1,#4]!Updates the address base register with newaddress

Post Index : LDR r0,[r1],#4Updates the address register after address isused

Multiple register transfer


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Load store multiple instructions transfermultiple register contents between the memoryand the processor in a single instruction

More efficient for moving blocks of memoryand saving and restoring context and stack

Can increase In ter rup t Latenc y

Usually these instruction execution are notinterrupted by ARM

Multiple Byte Load Store


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Any subset of current bank of registerscan be transferred to memory or fetchedfrom memory

LDM

STM

The base register Rn determines the

source or destination

SWAP instruction


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Special case of load store instruction

SWP

SWB


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Load and Store Pre-indexedAddressing


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Addressing

STR r0, [r1,#12]

r1

0x200Base

Register

Memory

0x5

0x200

r0

0x5

SourceRegisterfor STR

Offset

120x20c

Load and Store Post-indexedAddressing


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Addressing

STR r0, [r1], #12

r1

0x200

OriginalBase

Register

Memory

0x50x200

r0

0x5

Source

Registerfor STR

Offset

12 0x20c

r1

0x20c

Updated

BaseRegister

MULTIPLE REGISTER LOAD ANDSTORE


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STORE


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LDM{c o n d }address -mode Rn {!},reg-l is t {^}

{cond}

IA - increment after.

IB - increment before.

DA - decrement after.

DB -decrement before


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LDMDA R0, {R4-R9}

STMIA R1,{R2-R4}

STMIA R1!,{R2-R4}


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READONLY AND READ/WRITEMEMORY


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In readonly memory ,data is written usingdirectives like DCD,DCW

From there, it is copied to readwritememory using load and storeinstructions

Literal Pools


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LDR R1,= 0x33333333.

AREA PROG1,CODE,READONLY

ENTRY LDR R1,=0x12400000LDR R2,=0X00555555

ADD R3,R1,R2

LTORGSPACE 4400

STOP B STOPEND


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STACK PROCESSING


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A stack is implemented as linear datastructure which grows up (ascending) ordown (descending)

Stack pointer hold the address of thecurrent top of the stack

Stacks


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A stack is an area of memory which grows as new data ispushed onto the top of it, and shrinks as data ispopped off the top.

Two pointers define the current limits of the stack.

A base pointerused to point to the bottom of the stack (the first location).

A stack pointerused to point the current top of the stack .

SPBASE

PUSH

{1,2,3}

1

2

3

BASE

SP

POP

1

2Result of pop = 3

BASE

SP

Stack


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OperationTraditionally, a stack grows down in memory, with the last pushed value atthe lowest address. The ARM also supports ascending stacks, where the stack

structure grows up through memory.The value of the stack pointer can either:

Point to the last occupied address (Full stack)and so needs pre-decrementing (ie before the push)

Point to the next occupied address (Empty stack)and so needs post-decrementing (ie after the push)

The stack type to be used is given by the postfix to the instruction:STMFD / LDMFD : Full Descending stackSTMFA / LDMFA : Full Ascending stack.STMED / LDMED : Empty Descending stackSTMEA / LDMEA : Empty Ascending stack

Note: ARM Compiler will always use a Full descending stack.

Stack Examples


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Stack ExamplesSTMFD sp!,

{r0,r1,r3-r5}

r5

r4

r3r1

r0SP

Old SP

STMED sp!,{r0,r1,r3-r5}

r5

r4

r3

r1

r0

SP

Old SP

r5

r4

r3

r1

r0

STMFA sp!,{r0,r1,r3-r5}

SP

Old SP 0x400

0x418

0x3e8

STMEA sp!,{r0,r1,r3-r5}

r5

r4

r3

r1r0

SP

Old SP

STACKS ANDSUBROUTINES/PROCEDURES


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