arm mips. 32 registers, each 32-bit wide. 30 are general purpose, r30(hi) and r31(low) are reserved...
TRANSCRIPT
ARMMIPS
REGISTER BANK
REGISTER BANK IN ARM : WHERE?
multiply
data out register
instruction
decode
&
control
incrementer
registerbank
address register
barrelshifter
A[31:0]
D[31:0]
data in register
ALU
control
PC
PC
ALU bus
A bus
B bus
register
REGISTER BANK OF ARM : DETAIL
R0
R1
R2
R30
R31
5x32 Decoder
32x1MUX
32x1MUX
rs1
rs2
alu_in1
alu_in2
clk
write
32
32
5
5
5
32
rd
32
write_data
REGISTER BANK OF ARM : NUMBER OF REGISTERS
32 registers, each 32-bit wide. 30 are general purpose, R30(Hi) and R31(Low) are reserved for the results of long multiplication (64-bit result).
Register File
Write
RD2 RD3RD1
RA1 RA2 RA3
WD
Clk
Reset
WA
32 32 32
{Hi, Lo}
32
64
Read Address 1 Read Address 2 Read Address 3
Read Data 1 Read Data 2 Read Data 3
Write Data
Write Address5
555
Mul_64
64-bit Multiply Data
REGISTER BANK OF ARM : READ PORTS
The register file has three read ports. Reading is done asynchronously and the addresses of the registers to be read are provided by RA1, RA2 and RA3 (each 5-bit wide) while the data of these addressed registers are reflected on RD1, RD2 and RD3 (each 32-bit wide).
Register File
Write
RD2 RD3RD1
RA1 RA2 RA3
WD
Clk
Reset
WA
32 32 32
{Hi, Lo}
32
64
Read Address 1 Read Address 2 Read Address 3
Read Data 1 Read Data 2 Read Data 3
Write Data
Write Address5
555
Mul_64
64-bit Multiply Data
REGISTER BANK OF ARM : WRITING
Writing into the registers is done at the negative edge of a clock and is enabled by the write control signal. The address of the register to be written is supplied by WA (5-bit wide) and the data is provided by WD (32-bit wide).
Register File
Write
RD2 RD3RD1
RA1 RA2 RA3
WD
Clk
Reset
WA
32 32 32
{Hi, Lo}
32
64
Read Address 1 Read Address 2 Read Address 3
Read Data 1 Read Data 2 Read Data 3
Write Data
Write Address5
555
Mul_64
64-bit Multiply Data
MIPS DATA PATH : REGISTER BANK
REGISTER BANK : MIPS
There are 32 32-bit registers in a MIPS datapath.
The register bank module includes two read register address inputs (5-bits each), one write register address input (5- bits), a write-enable signal input (1-bit), a write data input (32-bits), and two read data outputs (32-bits).
REGISTER BANK : MIPS
On the positive edge of the write-enable input, the register bank will update the contents of the register at the write address with whatever data is on the write data bus.
The read data outputs are output asynchronously – i.e. they are a function of the read register addresses.