Ariadne’s Thread

Kristian Zarb Adami

Simulator Aims

۞Provide the system architect a tool to visualise trade-offs in designs

۞Provide the scientist top-level performance numbers for a given system

۞Maintain a close relationship with the cost-model so that cost estimates can be derived from the model

۞Maintain a close relationship with the telescope simulation environments (eg. MeqTrees)

۞Provide an easy route to implementation

The Specificationhierarchy …

LineSensitivity

ContinuumSensitivity

Survey Speed

FoVDynamic Range

BandwidthAeff Tsys

DynamicRange

# of bits# of channels# of beams

Front-EndAnalog

Antenna Efficiency

Digital Processing

SignalTransport

CORRELATION &IMAGE PIPE

Cost

& F

unct

ional M

od

el

Sky

Sci

ence

Eng

ineeri

ng

Soft

ware

Digital Aperture Array

Beam Pattern showing interference cancellation

2-PadSystem Example

۞ Log-Periodic Dipole Array between 0.3 – 1GHz

۞ Demonstrate All-Digital Aperture Array for beam-forming, calibration and RFI mitigation

۞ Demonstrate scalability in terms of power consumption, cost and performance

۞ Demonstrate functionality in terms of bits, bandwidth and beams

...(0

...

One-tile sub-array antenna unit of8x8x2 LP dipoles

Main LN Amplifiers and WB Filters

63)x2

8x8x2 ADC

...(0 63)x2

(0 63)x2...Frequencysplitting

onto 1024subbands

...

(0 1023)x2 ...(0 1023)x2

Frequencysplitting

onto 1024subbands

2.4GS/s4-bit real4-bit imag

Equaliser Equaliser

2.4MS/s4-bit real4-bit imag

1024x28-bit presetcoefficients

......

Polarisationcorrection

of each H-Vpair

...

Polarisationcorrection

of each H-Vpair

...

...

...

... ...(0 1023)x2 1023)x2(0

... ...

8x8x22D FFT

0

8x8x22D FFT

1023

... ... ... ...

... ...

...

(0 (063)x2 63)x2... ...

8 Beamselector

and beam-steering

8 Beamselector

and beam-steering

...

... ...(0 (08)x2 8)x2

FOVcorrection

FOVcorrection

...

...

...(0 8)x2 ...(0 8)x2

AnalogProcessing

DigitalProcessing

Analog ModelOutside Station

Digitisation

۞ 1st filter response

۞ Channel Selection

۞ 4-bit ‘Ideal’ ADC

A/D Converters

۞ 4-bit 2.4 GS/s CMOS already available at sample level

۞ Front-End bit-count can be increased to 8 (~50dB of Dynamic Range) for RFI mitigation, with reduced bit-count at the back-end

۞Equalization ‘may’ also be included in this block

۞Decimation and digital formatting can be integrated into back-end of A/D

Channelization

۞ Form channels from each ADC

۞ Different channelisation algorithms can be tried

۞ Equalisation can be implemented as part of the channelisation block

۞ Data is now moved to the beamformer (windowing can occur in beamforming block)

ChannelizationAlgorithms

Algorithm

Decomposition into 1024 sub-bands

No. of GMACs

Per polarisation per element

DSP Operations

Direct time Decimator

For 5-taps = 12 72 GOps

FFT (no-filtering)

For Radix-2 = 24

144GOps

Polyphase + FFT

5-taps FIR filter +

FFT (Radix-2)

216GOps

Analysis Filter Bank

(Wavelets)

For 10 stages = 480

2,880GOps

Cost/Power Calculationsfor 1st stage

Total Requirements Stream   XXX (register files) XXX (on-chip mem.)

         

Chips to sustain Ops 1   1 1

Power for Operations (FIR) 1.92 W 0.96 96

Power for Operations (FFT) 1.92 W 0.96 96

         

Chips to sustain Bandwidth 2   1 1

Total Power required for Bandwidth 3.00E-01 W 3.00E-01 3.00E-01

         

Chips required 2.00E+00   1.00E+00 1.00E+00

Power/Chip for Operations (FIR) 9.60E-01 W 9.60E-01 9.60E+01

Power/Chip for Operations (FFT) 9.60E-01 W 9.60E-01 9.60E+01

Power/Chip for Bandwidth 1.50E-01 W 3.00E-01 3.00E-01

         

Total Power per Chip (FIR) 1.11 W 1.26 96.30

(FFT) 1.11 W 1.26 96.30

         

Cost per Chip ($) 149 $ 100 100

Cost per GMAC ($) 1.16 $ 0.78 0.78

         

Total Power 2.22 W 1.26 96.30

Total Cost 298 $ 100.00 100.00

۞ Side-lobes considerably reduced with increasing number of bits

۞Trade-off number of taps with coefficient accuracy

۞ Aim to relate this with science goals

Poly-phase filteringResponse

FFT Beamformer

۞ Form many beams at once

۞ Different beams in different directions

۞Windowing function can be used to suppress sidelobes (especially 13.0dB from rectangular window)

۞ Trade-off windowing with sidelobe height and Aeff/Gain

8-pt FFT

۞ 8-pt FFT real-time model implementation

۞Twiddles can be retrieved from memory

۞Easy mapping onto FPGA/RPA interface

Fixed vs. Floating Point

۞Bit-growth per stage۞4-bit FFT vs. floating point

Windowingfor Sidelobe Cancellation

Reconfigurable Processor Arrays

۞ Heterogeneous Array of Instruction cells

۞ Rate controller to control delay in data paths

۞ I/O Ports mapped as instruction cells

۞ Low Power / Area

۞ Highly Configurable

۞ High I/O Bandwidth

Configurationstream

Programcounter

Data Memory

orADC

I/O Ports

ProgramMemory

RateControl

+<<

x

Example Code

void oned_dct (int *coeff,int *block) {

b0 = coeff[0]; b1 = coeff[1]; b2 = coeff[2]; b3 = coeff[3]; b4 = coeff[4]; b5 = coeff[5]; b6 = coeff[6]; b7 = coeff[7]; e = b1 * const_f7 - b7 * const_f1; f = b5 * const_f3 - b3 * const_f5; c4 = e + f; c5 = e - f;

h = b7 * const_f7 + b1 * const_f1; g = b3 * const_f3 + b5 * const_f5;

c6 = h - g; c7 = h + g; c0 = (b0 + b4) * const_f4; c1 = (b0 - b4) * const_f4; c2 = b2 * const_f6 - b6 * const_f2; c3 = b6 * const_f6 + b2 * const_f2;

b5 = (c6 - c5) * const_f0; b6 = (c6 + c5) * const_f0; b0 = c0 + c3; b1 = c1 + c2; b2 = c1 - c2; b3 = c0 - c3;

block[0] = b0 + c7; block[1] = b1 + b6; block[6] = b1 - b6; block[7] = b0 - c7; block[2] = b2 + b5; block[3] = b3 + c4; block[4] = b3 - c4; block[5] = b2 - b5;}

Datapath example:

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

2 ns

1 ns

4 ns

2 ns

3 ns

1 ns

RPA Solution - Datapath Illustration

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Configurationstream

Programcounter

Data Memory

orADC

I/O Ports

ProgramMemory

RateControl

+<<

x

Off-chip bandwidth ~ 10 Gbit/sIntra-cell bandwidth ~ 100 Gbit/s

Future Work

۞ Include clock delays for each block to ensure real-time data tracking (as well as JITTER !!!)

۞ Include a calibration model for Gain/Phase calibration @ each antenna

۞ Relate beam-forming to FoV to work out the trade-off between number of beams vs. no. of bits/ beam

۞ Relate DSP-induced noise to noise temperature to work out contribution to Tsys

۞ Relate side-lobe suppression models to Dynamic Range and Image Fidelity

۞ Produce Cost / Power benchmarks for each block for input into the Cost Model

۞ Extend model to the full-frequency coverage of a station

۞ Produce technology and architecture roadmaps including cable architecture

Extra slides

ScienceGoals

TechnologyCapabilities

$$

SoftwareCapabilities

Simulations

Simulations

Sim

ula

tion

s

Error Modelling

۞ Quantization error dependent on bit-width

۞ Scaling considerations are IMPORTANT