area selective deposition: challenges and …€¦ · hfn 10 nm 3:1 zro2 10 nm 3:1 al2o3 10 nm 3:1...

AREA SELECTIVE DEPOSITION: CHALLENGES AND

OPPORTUNITIES FOR PATTERNING SOLUTION

EFRAIN ALTAMIRANO-SANCHEZ, B.T. CHAN, ANNELIES DELABIE, SILVIA ARMINI AND

STEVEN SCHEER, IMEC

CONFIDENTIALASD workshop 2019, Leuven

OUTLINE

▪ Intro: ASD state of the art

▪ Big picture - Keeping Moore’s law

▪ Scaling boosters and ASD

▪ New devices and ASD

▪ Summary

2

AREA SELECTIVE DEPOSITION (ASD)


ASD – STATE OF THE ART

3

• Semiconductor on

semiconductor: well

stablished

• Metal on Metal (MoM): Some demonstrations

• Capping layers (Co, Mn ...) on Cu (electro-migration)

• Selective bottom up fill with ELD (Co, Ni...)

• Ru ALD and W LPCVD/CVD

• Dielectric on Dielectric (DoD): few

demonstrations, mainly high-k materials.

• Limited works on low-k materials (<5).

• Metal on Dielectric selective to Metal (MoD): ...?

• Dielectric on Metal selective to Dielectric (DoM)

Loo et al, ECS J. Solid State Science and

Technology, 6, P14 (2017)

Minaye Hashemi et al, ACS Nano, 9, 8710 (2015)

Simon et al, IEEE

IRPS, 2013

B

CACAC

Eric Stevens et al. Chem. Mater 2018.

J. Electrochem. Soc. 1984 volume 131, issue 6, 1427

I Zyulkov, et al. ACS 9 (36), 2017, 31031-31041

CONFIDENTIAL

log 2

(#tr

ansi

stors

/$)

20152013201120092007

Happy scaling era

# transistors per area

doubles every two year

for same cost

14nm

20nm

28nm

40nm

65nm

90nm

Less happy scaling era

Still doubles but device

scaling provides diminishing returns

2017 2019 2021 2023 20252005

Hybrid scaling

CFET

TFET

MX2

SPIN

20nm: First sign of trouble

Double patterning (cost !)

Planar device runs out of steam

14nm: FinFET

FinFET device saves the day

10nm

7nm

5nm

5nm: At last ...

EUV reduces cost

NW devices

3nm: Double whammy

Double patterning EUV

Fin based device runs out of steam

3nm

2nm1.75nm

10-7nm: More trouble

Multi-patterning cost escalates STCO

Scaling boosters

Focus of process technology innovation is

Scale device and wire Scale basic logic cells Scale (sub-)system functions

Special constructs

Track height reduction

New Compute

Machine learning

Quantum computing

Neuromorphic

BIG PICTURE - KEEPING MOORE’S LAWLOGIC SCALING PARADIGM UNDER PRESSURE

2027 2029 2031

Sp

Dp

Dn

Sn

G

Sp

Dp

Dn

Sn

G

CFET


SCALING BOOSTERS AND SILICON IMPLEMENTATION @ IMEC

5

AREA

SCALING

POWER /

PERFORMANCE

Power delivery

to BPR

ST

I o

xid

e

VDD

Vint

M1

Mint

V0

VBPR

M0A

Buried Power Rail

Buried power railSuper Via

Free up routing resources by

moving power rail to the bottom

BPR enables 4-track standard cell

Reduces congestion in

the routing layers and

reduces via R on multi-

level

PROCESS WINDOW and

YIELD

Full Self Aligned ViaEUV SADP + LELE EUV

Self aligned block (SALELE-B)

193i SAQP + LELE EUV

Self aligned block (SAB)

Improves edge placement error

(EPE) and reliability margin.

PROCESS DEVELOPMENT CHALLENGES ON SCALING BOOSTERS

CAN ASD HELP?


SUPER VIA SCALING BOOSTER

7

SV REDUCES CONGESTION IN THE ROUTING LAYERS AND REDUCES VIA R

Through BEOL Via

“technology element”

Super-via

Mx => Mx+2

(e.g. PDN)

Super-via

Through multiple

layers

Dielectric barrier Metallization


SUPER VIA METALLIZATION

▪ ...

▪ Metal via fill (Cu, Co, Ru...)

▪ Voids free

▪ Seams free

▪ Metal CMP

▪ Metal recess

▪ ....

8

▪ ...

▪ Surface passivation

▪ Partial bottom up via fill (MoM ASD)

▪ Wet clean of defects

▪ ....

Bottom up fill

Hard way... New paradigm

Bottom up fill

CONFIDENTIALASD workshop 2019, Leuven 9

Through BEOL Via


Super-via

Mx => Mx+2

(e.g. PDN)

Super-via

Through multiple

layers

SV METALLIZATION: ELECTROLESS DEPOSITION (ELD)

Marleen H. van der Veen et al. IEEE Materials for Advanced

Metallization Conference (IITC/MAM), 2015.

(a) Schematic illustration of the catalytic electroless

reaction of Co on a Pd or Cu. The reducing agent

(Red) is part of the ELD bath (b) Co ELD on Pd/W for

different timed stops to yield an (i) under fill (ii)

potential ideal stop or an (iii) overburden in 28nm

diameter holes (AR 4.5).

Artur Kolics (Lam Research), 20th IEEE IITC, 2018.


FULL SELF-ALIGNED VIA SCALING BOOSTER

10

IMPROVES RELIABILITY MARGIN BY INCREASING THE MIN. DIELECTRIC WIDTH AT THE BOTTOM OF VIA

Through BEOL SAV


• time-dependent dielectric

breakdown (TDDB)

• Overcome EPE, Via-M1

• Towards 1x nm HP M1

M1 Low k SiCN SOC M2

M1_barrier SiN SiO2 TiN HM M2_barrier

Topography of

10nm of dielectric

Via patterning

selective to SiCN.

Topography is

maintained by

selective removal

of SiCNMinimum distance

Via-M1.


FULL SELF-ALIGNED VIA PATTERNING

▪ ...

▪ Metals recess

▪ Cu, Co, Ru...

▪ Barrier: TaN, TiN

▪ Recess depth control (WiD, WiW & WtW)

▪ Roughness

▪ ....

11

▪ ...

▪ SAMs blocking agent for ALD

▪ Dielectric on Dielectric ASD

▪ Strip & wet clean

▪ ....SAM deposition DoD ASD



DOD FOR SAV

12

IDEAL MONOLAYER SAM PASSIVATION IN COMBINATION WITH ALD AL OXIDE ASD

CuSi oxide

ASD Al oxide 5-6 nm

After defect removal

50 nm HP lines

21 nm HP lines

Cu

Si oxide

ASD Al oxide ~3 nm

DoD ASD by a combination of ALD and organic film passivation for self-aligned via patterning M. Pasquali et. al. ASD 2019


SCALING BOOSTERS AND SILICON IMPLEMENTATION @ IMEC

13

AREA

SCALING

POWER /

PERFORMANCE

Power delivery

to BPR

ST

I o

xid

e

VDD

Vint

M1

Mint

V0

VBPR

M0A

Buried Power Rail

Buried power railSuper Via

Free up routing resources by

moving power rail to the bottom

BPR enables 4-track standard cell

Reduces congestion in

the routing layers and

reduces via R on multi-

level

PROCESS WINDOW and

YIELD

Full Self Aligned ViaEUV SADP + LELE EUV

Self aligned block (SALELE-B)

193i SAQP + LELE EUV

Self aligned block (SAB)

Improves EPE and reliability

margin.


SELF ALIGNED BLOCK OR SELF-ALIGNED LELE (eSALELE )

14

A COMPLEX PATTERNING PROCESS FOR 21 nm METAL PITCH

e

Grid formation

1 193i mask

2 EUV masks for

blocks

SAB

4 EUV masks.

2 for gratings

2 for blocks

eSALELE-B

Follow @ imec PTW April 2019; Interconnect (L201) eSALELE

by Stefan Decoster

Block masks

Negative tone

development (NTD)

process with metal

containing resist.

• eSADP : EUV litho self-aligned-double -patterning

• SAQP: 193i self-aligned-quadruple-patterning



15


Follow @ imec PTW April 2019; Interconnect (L201) eSALELE

by Stefan Decoster

EPE budget (perpendicular to trenches) is only 1/4 pitch

e.g. for 21 nm pitch: 5.25 nm

Standard

block

Self-Aligned

Block

Selectively blocking one trench to the neighboring trenches

EPE budget is increased to 3/4 pitche.g. for 21 nm pitch: 15.75 nm



16


e

Grid formation

1 193i mask

2 EUV masks

(for blocks).

SAB

4 EUV masks.

2 for gratings

2 for blocks

eSALELE-B Block masks

Negative tone

development (NTD)

process with metal

containing resist.

Pillar patterning with

lower process window

and big question mark for

scaling.

Self aligned hole development

for tone reverse

Positive tone

development (PTD)

process with chemical

amplified resist.

Hole patterning are more

robust for patterning

transfer and are scalable.


SELF ALIGNED BLOCK PATTERNING

▪ ...

▪ Grating patterning

▪ Block mask NTD development

▪ Metal containing resist (NTD)

▪ Block patterning transfer

▪ Narrow process window

▪ Question mark for scaling

17

▪ ...

▪ Grating patterning

▪ Hole NTD development

▪ Chemically amplified resist (PTD)

▪ Hole patterning transfer

▪ Larger process window

▪ Scalable

▪ Surface passivation

▪ Bottom up selective deposition

▪ DoD

▪ MoM

▪ DoM

▪ ....

Classic patterning strategy Tone reverse without spin-on materials


SCORE CARD

18

SELECTIVE DEPOSITION ON METAL NOT ON DIELECTRIC

Material Thickness required Minimum etch selectivity (to TiN etch)

TiO2 10 nm 3:1

HfN 10 nm 3:1

ZrO2 10 nm 3:1

Al2O3 10 nm 3:1

Ru 2-3 nm 20:1

Other Metals 10 nm 3:1

The proposed materials must withstand subsequent etch steps; TiN HM opening with F chemistry, wet HF resistant and

it should be striped easily dry or wet.

• Dielectric on Metal (DoM)

remains a challenge for

academia and industry.

• Metal on Metal are reported

and there is more know-how.

• The etch resistance of metals is

somehow superior than

dielectrics.


Size-dependent Ru nanoparticle reactivity is used to suppress defect growth

ASD OF Ru FOR BLOCK PATTERNING (300 MM WAFER)

▪ DMA-TMS passivation

▪ Ru ALD: dNP < critical size

▪ Etch of metal NP

TiN

CH3

SiO2 TiN

TiF

TiNRu

CH3

DMA-TMS Ru ALD

SiO2 SiO2

DMA-TMS surface chemistry: dual function

J. Soethoudt et al, Adv. Mat. Int. (2018),

ASD workshop 2018, 2019


Ru ASD defectivity < detection limit of TOFSIMS and SEM

ASD OF Ru FOR BLOCK PATTERNING (300 MM WAFER)

1

m

Defect

etch

RuSiO+ SF-SIMS after ASDTop view SEM after tone inversion

X-TEM after tone inversion


METAL BOTTOM UP DEP ON TIN SELECTIVE TO SIO2 (LINE/SPACE)

21

~10nm of Metal deposition with no defects observed at CDSEM and TEM.

improved processM M M

Applied Materials/imec courtesy Applied Materials/imec courtesy

Applied Materials/imec courtesy Applied Materials/imec courtesy


METAL BOTTOM UP DEP ON TIN SELECTIVE TO SIO2 (LINE/SPACE)

22

Applied Materials/imec courtesy





METAL BOTTOM UP DEP ON TIN SELECTIVE TO SIO2 (HOLE-PILLARS)

23

Applied Materials/imec courtesy Applied Materials/imec courtesy Applied Materials/imec courtesy

NEW DEVICES

CONFIDENTIAL

CFET CONCEPT

25

Sp

Dp

Dn

Sn

G

Sp

Dp

Dn

Sn

G

Complementary FET: P/N stacked

devices with common gate structurally

simplifies device access.

6T

4T CFETCFET provides more than 33% structural gain in CMOS.


CFET – MODULES

26

Si nMOS

NW

Si pMOS

NW

eSiGe: B

Top

contact

Contact isolationInner

spacer

Gate

spacernMOS

RMG

pMOS

RMG20nm

30nm

30nm

Epi / ContactRMG Spacer

eSiGe: P

Bottom

contact

▪ Fin

▪ Gate

▪ Inner spacer

▪ Bottom p-S/D

▪ Bottom contact

▪ Contact isolation

▪ Top n-S/D

▪ Top contact

▪ NW release

▪ RMG

BPR

Contact

to BPR

* Not to scale

CFET on N5 dimensions


TUNGSTEN BOTTOM ELECTRODE

27

Filling material formation

• Metal: W & Ru recess after CMP

• Specifications: -

• W recess uniformity < 5 nm

• Ideally should be flat in trench.

Current status

• Evaluated the ALD vs. CVD W etch back.

• Evaluation on Ru EB is on-going. Problem with RuOx residue on side wall


RUTHENIUM BOTTOM ELECTRODE

28

Ru RECESS BY DRY ETCH LEAVES SIDEWALL RESIDUES

Residue visible on sidewall

• ALD Ru with forming gas anneal

• Uncleanable residue visible on cavity sidewall

• Different process conditions being explored

After Ru CMP

Ru

Ru

After Ru etch-back

W for sample preparation

W for sample preparation

Contact module development for CFET


ISOLATION

29

Isolation dielectric formation

• Ideally 10-15nm isolation dielectric between top

and bottom metal

• Specifications: -

• uniformity < 3 nm WiW

Current status

• 1st demonstration on SiN liner & F-CVD Ox EB.

• SiN EB by H3PO4


CFET: TOP AND BOTTOM CONTACTS AND CONTACT ISOLATION

▪ ...

▪ Bottom electrode▪ Metal fill (W, Ru...)

▪ Voids free

▪ Seams free

▪ Metal CMP

▪ Metal etchback

▪ Contact isolation▪ Dielectric deposition/fill

▪ CMP

▪ Dielectric etch back

▪ Top contact▪ Metal fill (W, Ru...)

▪ CMP

▪ ....

30

▪ ...

▪ Bottom electrode

▪ Bottom up metal ASD (MoM/MoS)

▪ Contact isolation

▪ Bottom up low-k dielectric (DoM) ASD.

▪ Top contact

▪ Bottom up contact (MoD)

▪ ....



SUMMARY

▪ The benefits of ASD can be plugged to N5/N3/N2... technologies.

▪ The challenges of ASD are significant. However, it is an interesting area in science for

fundamental research in academia and industry.

▪ ASD can bring two outstanding benefits: simplicity and cost reduction.

▪ Are ASD processes with “no defects” ( under detection limits) good enough?

▪ Is current metrology sufficient to characterize ASD processes?

▪ New hybrid-devices like CFET can strongly benefit from ASD.

31


ACKNOWLEDGEMENTS

▪ Annelies Delabie, Silvia Armini, Sebastiaan Herregods, Job Soethoudt (PhD), Ivan Zyulkov

(PhD), Kathy Barla, Matty Caymax, Sven Van Elshocht, Wilfried Vandervorst, Christoph

Adelmann, Stefan De Gendt, Zsolt Tokei, Philippe Leray, Juergen Boemmels, Sandip

Halder, Eric Stevens (PhD), BT Chan, Stefan Decoster, Sara Paolillo, Khashayar Babaei and

Frederic Lazzarino.

32

METROLOGY


IS CURRENT METROLOGY AT THE DETECTION LIMIT?

35

ANGSTROM DEFECTS DIFFICULT TO DETECT IN A 300MM WAFER

EDR

TEM

SEM

RBS

AFM

XPS

SF-SIMS

...

• Let's get down to the nitty-gritty – how much do we care?

• Is yield the only metric?


ELD

SPT

Wet

AREA SELECTIVE DEPOSITION (ASD) IN ITS INFANCY

36

KNOWLEDGE NEEDS TO BE BUILT UP AT RELEVANT DIMENSIONS (<32nm)

Bottom up patterning solutions...

Growth curves (ASD)

2016-2020

ASD on pattern structures

2017-2020

ASD on devices

2020-2026

Etch/

ALE

SAMs

Metro-

ALD

Charact

.

CONFIDENTIAL

LOWER CONTACT AND ISOLATON FLOWFORM A METALLIC CONTACT THE LOWER AND ENCAPSULATE WITH AN ISOLATOR

Post Lower EPI ILD0 Fill

Not damaging the

Contact region

Stop on HM

Contact patterning

and Metal Fill

Contact Recess

Need to control height

very well

Need to remove all

conductors from the

sidewall

Isolation fill and

Etchback

Open the Top Wire

stud


DOD FOR SAV

38

SPIN-ON SAM PASSIVATION IN COMBINATION WITH ALD AL OXIDE ASD

~ 7 nm

Al oxide

film

area selective deposition: challenges and …€¦ · hfn 10 nm 3:1 zro2 10 nm 3:1 al2o3 10 nm 3:1...

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