arcticlink® ii vx2 solution platform data sheet · pdf file† tv-quality visual...

• • • • • •Programmable Solution Platform with Visual Enhancement Engine (VEE), Frame Buffer and Programmable Fabric – Tailored for Processors and Displays with RGB or CPU-Bus Display Interface

ArcticLink® II VX2 Solution Platform Data Sheet

Platform Highlights

Visual Enhancement Engine v2.0• TV-quality visual experience in mobile devices

through dynamic range control.

• Greatly enhanced image and video quality even under low backlight or bright ambient conditions.

• Based on proven, patented technology, licensed from Apical Ltd.

Display Power Optimizer (DPO)• Dramatically improves battery life up to 70% by

reducing LCD backlight or OLED brightness.

• Tightly coupled with the VEE technology for optimal operation.

• Directly controls the PWM for backlight management.

SPI Master• Serial interface to control sensors, peripherals,

and/or displays.

LCD Controller• Supports RGB888, RGB666, and RGB565.

• Supports up to WXGA resolution (1366x768) at 24 bits per pixel without frame buffer or WSVGA resolution (1024x600) with frame buffer

• Capable of refresh rates exceeding 60 frames per second.

Optional Frame Buffer• Up to 32 Mbits of embedded frame buffer using

very low power CellularRAM technology.

• Supports buffering of multiple frames up to WSVGA resolution (1024x600) and 24-bit color depth.

• Onboard frame buffer allows mobile processor to be kept in sleep mode or slower refresh rate, while refreshing mobile display at 60+ frames per second.

Pulse Width Modulator (PWM)• 16-bit programmable load count.

• Configurable pre-scalar for the PWM clock.

• Additional PWMs can be included.

Very Low Power (VLP) ModeThe ArcticLink II VX2 has a special VLP pin which can enable a low power sleep mode that significantly reduces the overall power consumption of the device by placing the device in standby.

Timing Controller (TCON)Generates Hsync, Vsync and DE signals and supports up to WSVGA (1024x600 resolution).

I2C ClientCPU interface for configuring and controlling internal VEE registers and look-up tables.

Onboard Clock GenerationIntegrated, very low power Phase Locked Loop (PLL) for generating clocks necessary for the VEE, Frame Buffer, LCD interface, PWM and TCON.

Small Form Factor Packaging121-ball, 6 mm x 6 mm TFBGA, 0.5 mm ball pitch.

Joint Tag Access Group (JTAG)The QuickLogic® ArcticLink II VX2 solution platform supports IEEE 1149.1 boundary scan or post-manufacturing testability. External access to this feature can be completely disabled.

© 2013 QuickLogic Corporation www.quicklogic.com••• •••

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http://www.quicklogic.com

ArcticLink® II VX2 Solution Platform Data Sheet Rev. 1.0

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Flexible Programmable Fabric• Multiple customizable building blocks (CBBs) (see Programmable Fabric Architectural Overview on page

29 for a detailed explanation of CBBs)

• Various amounts of SRAM with embedded FIFO controllers

• Multiple user configurable clock managers (CCMs) (see Configurable Clock Manager – Onboard Clock Generation for the Programmable Fabric on page 31 for an explanation of the CCM)

• Up to 70 programmable I/Os available.

• Ideal platform to implement LCD Controller tailored for OEM/ODM display requirements including support for:

RGB888, RGB666, and RGB565

Up to WXGA (1366x768 resolution) without frame buffer, up to WSVGA (1024x600 resolution) with frame buffer

Capable of refresh rates exceeding 60 frames per second

Support for smart (EBI/CPU interface) or dumb (RGB) display

Support for secondary smart display

• Ability to configure multiple 2-wire serial peripheral host and client controllers for controlling and aggregating multiple low-speed peripherals into single backchannel to mobile processor. These peripherals include ambient light sensor, touch screen controller, proximity sensor, accelerometer, e-paper controller, temperature sensor, and other low-bandwidth peripherals.

• Implement programmable PWM tailored to specific display requirements.

• Autonomously adjust LED backlight based on reflected ambient light, and display content for optimized viewing experience and battery life savings.

Programmable GPIO• Bank programmable drive strength between 1.8 V and 3.3 V.

• Bank programmable slew rate control.

• Independent I/O banks capable of supporting multiple I/O standards in one device.

• Can be used for level shifting, bus switching, and I/O voltage translator and managing clock distribution.

www.quicklogic.com © 2013 QuickLogic Corporation•• ••••





Applications Overview

The ArcticLink II VX2 solution platform is a Customer Specific Standard Product (CSSP) and consists of the following main modules:

• VEE v2.0

• DPO

• SPI Master

• Frame Buffer

• I2C Client

• PWM

This highly integrated, yet flexible architecture makes it the ideal platform to implement display path CSSP solutions for smartphones, multimedia phones, feature phones, Mobile Internet Devices (MIDs), and smartbooks.

The ArcticLink II VX2 solution platform can be used to replace several discrete components typically used in mobile devices today to reduce power consumption, reduce BOM cost, save precious PCB space, and reduce the size of cables through a clamshell/swivel/slider handset hinge.

The onboard programmable Fabric enables an almost endless combination of interface standards and functionality to enable extremely efficient and future-proof system design. The QuickLogic System Solution Group (SSG) provides the Proven System Blocks (PSBs), software drivers, documentation, reference schematics and support to help accelerate OEM and ODM time-to-market with CSSPs based on the ArcticLink II VX2 solution platform.

© 2013 QuickLogic Corporation www.quicklogic.com• • • •••

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Figure 1: System Level Block Diagram with CSSP Based on ArcticLink II VX2 Solution Platform

I2CClient

Registers

Bus Controller

Frame Width

Frame Height

Blanking/Porch

Programmable Polarity

IncomingRGB FIFO

Write AddrGenerator

Read AddrGenerator

OutgoingRGB FIFO

FrameBufferCTRL

Ce

llu

larR

AMAddress

Data

Controls

32 kHzOscillator

PL

L~ MHzOscillator

MobileProcessor

PL

L

DPO

PWM

MobileProcessor

SPIMaster

LCD

RG

B’

HS

YN

C’

VS

YN

C’

DE

’

PIX

EL

_C

LK

’

RG

B

HS

YN

C

VS

YN

C

DE

PIX

EL

_C

LK

CustomizableLCD

Controller

TimingController

(TCON)






Fixed Logic Region

VEE v2.0The ArcticLink II VX2 solution platform embeds the VEE technology as a fixed logic PSB, with very low power and optimal die size for lowest BOM costs. QuickLogic and Apical Limited partnered to architect and develop the optimal blend of algorithms with QuickLogic patented ViaLink® programmable Fabric for mobile and portable multimedia products. The VEE technology is based on a proven core licensed from Apical Limited, which is substantiated by nearly a decade of scientific research. These algorithms implement a model of human perception; resulting in a displayed image that retains detail, color and vitality even under variable viewing conditions. It specifically addresses the problem of the low contrast ratio of mobile LCDs to bring a more TV-like viewing experience to the mobile devices.

The QuickLogic proprietary VEE solution substantially enhances both image and video quality by optimizing the dynamic range, contrast, and color saturation pixel-by-pixel to provide a natural viewing experience under low backlight or bright ambient light conditions. Seamlessly integrated into the display path, the VEE enhances the user’s mobile multimedia visual experience while drastically reducing backlight power to extend battery life.

To further improve display quality, the technology has been supplemented by additional image and video enhancement blocks such as dithering, hue rotation, color correction, and non-linear sharpness filtering, among others. OEMs and ODMs can adopt this innovative display enhancement technology rapidly and easily within a system which has been fully purposed for integration into a multimedia handset.

A bypass path is provided for VEE. Note that when there is a switch between bypass to VEE mode or vice versa, the display will function normally, although there may be with some intermediate flicker due to the switching from VEE to non-VEE processed content. VEE gain registers will be updated based on ambient light condition reads by the SPI Master.

Display Power OptimizerHow to conserve power when playing back video content has also become a significant issue when designing mobile media devices. As displays typically consume 30% to 60% of the total system power, there has been a tremendous amount of research put into methods of reducing display power. A common solution is to lower the backlight level of the LCD or brightness level of an OLED. Unfortunately, this solution significantly diminishes the viewing experience since most details are lost due to the lowered contrast ratio.

While the VEE uses statistical information gathered pixel-by-pixel, frame-by-frame to adjust the value of individual pixels, DPO uses that same information to adjust the backlight. The ability to provide a unique tone curve for each pixel, as well as have tight control over the display backlight, gives greater flexibility than the global adjustments of alternative implementations. The QuickLogic approach results in greater power savings and the entirely new capability of adapting to a bright environment.

DPO seamlessly integrates with the QuickLogic VEE, ensuring longer battery life and an excellent visual experience by coupling the PWM driving the display backlight with the display content processing parameters of the VEE technology.


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6

Optional Frame BufferThe ArcticLink II VX2 solution platform contains a 32-Mbit frame buffer for storing display content between the processor and display. The addition of frame buffer technology allows the mobile processor to update frames of display content at much lower frame rates than the native refresh rate of the display, as shown in Figure 2.

Figure 2: Forward Video Content from Mobile Processor at 15 or 30 Frames per Second, While Refreshing LCD from Frame Buffer at 60 Frames per Second

PL

L

I2CClient

TimingController

(TCON)

Registers

Bus Controller

Frame Width

Frame Height

Blanking/Porch


IncomingRGB FIFO

Write AddrGenerator

Read AddrGenerator

OutgoingRGB FIFO

Ce

llu

larR

AMAddress

Data

Controls

32 kHzOscillator

~ MHzOscillator

PL

L

Refresh at

<60 Hz

Refresh from

Frame Buffer

at 60 Hz

FrameBufferCTRL

DPO

PWM

MobileProcessor

SPIMaster

LCD

RG

B’

HS

YN

C’

VS

YN

C’

DE

’

PIX

EL

_C

LK

’

RG

B

HS

YN

C

VS

YN

C

DE

PIX

EL

_C

LK

CustomizableLCD

Controller






This architecture allows the mobile processor display controller to be in sleep mode longer, or to transmit fewer bits – reducing energy consumption and extending battery life. The ArcticLink II VX2 platform can then refresh the display from the frame buffer at the appropriate refresh rate of the display (e.g., 60+ frames per second). The frame buffer is implemented with very low power CellularRAM technology, optimized for mobile devices that demand low power consumption, and low BOM cost. The ArcticLink II VX2 solution platform contains enough CellularRAM to buffer a full frame of video at 24 bits per pixel color depth, WXGA (1366x768 resolution), and can support a refresh rate capable of 60+ frames per second.

The frame buffer is seamlessly coupled with the VEE system block and LCD Controller.

The RGB data sent to the VEE system block must be in RGB888 mode. If the native system RGB data is in RGB565 or RGB666 format, the programmable Fabric will be used to convert it to RGB888 by padding the appropriate number of 0s in LSB positions as shown in Figure 3.

Figure 3: RGB Data Format to the VEE System Block

Frame rate conversion is one of the primary functions to be achieved while reading from the optional frame buffer. In the case of single buffer mode, the same buffer will be read out 60 times for 60 fps refresh of the display, irrespective of the input frame rate. In the case of ping-pong frame buffer mode, switching over to the other buffer will happen if there is a new frame available, otherwise the same buffer will be continued to be read out.

The frame buffer has the following special features:

• Horizontal Flip: Each row is read in reverse order. For address generation, the last burst is read out first. Pixels are read out and sent out from outgoing FIFO in reverse order also within each burst.

• Vertical Flip: The last row of the media frame is read out first. For address generation, the last row is read out first. Vertical flip is not possible for single buffer mode.

• 180 degree rotation: The frame buffer controller performs a horizontal as well as vertical flip for achieving 180 degree rotation. 180 degree rotation is not possible for single buffer mode.

Timing ControllerThe TCON generates Hsync, Vsync and DE signals with the following configured parameters with minimum and maximum ranges. The TCON is available when the optional frame buffer is used. The optional frame buffer and TCON function support up to WSVGA (1024x600 resolution).

• No of active pixels per line [tha]: 160 to 1024

• No of active lines per frame [tva]: 120 to 600

• Hsync width [thp]: 2 to 128 pixels

24 0

RGB565

RGB666

RGB888 B1G1R1

B1G1R1

B1G1R1


7



8

• Hsync front porch [thf]: 2 to 128 pixels

• Hsync back porch [thb]: 2 to 128 pixels

• Vsync width [tvp]: 2 to 32 lines

• Vsync front porch [tvf]: 2 to 32 lines

• Vsync back porch [tvb]: 2 to 32 lines

Figure 4 shows the TCON timing diagram.

Figure 4: TCON Timing Diagram

SPI MasterThe high-speed SPI Master supports up to three slaves. This SPI interface can be used for secondary display sensors or other peripherals. The SPI clock can be the internal programmable Fabric clock divided by 4 or 8. Therefore, the SPI clock speed is in the range of 1.5 MHz to 27.2 MHz.

The SPI Master has the following features:

• Full duplex synchronous serial data transfer

• Variable length of transfer word up to 256 bits

• MSB or LSB first data transfer

• Rx and Tx on both rising or falling edge of serial clock independently (CPOL)

• Rx and Tx serial clock phase controlled independently (CPHA)

• Three slave select lines

Vsync

Hsync

Hsync

Pixel_clk

DE

tvp tvb tva tvf

1H

thathp thb

1CLK

tha

thf






The SPI CTRL register has the following programmable control inputs:

• LSB/MSB first

• Tx neg/pos edge

• Rx neg/pos edge

• Tx clock phase

• Rx clock phase

• Start transfer

• Transfer length

• Write Transfer status

• Read Transfer status

The SPI clock DIVIDER bits can be selectable for the clock scale factor from /4 or /8 of the programmable Fabric clock.

The host has to poll for Write Transfer status bit set by hardware before it initiates another write. This Write Transfer status bit is also given to the host as an interrupt.

Figure 5 and Figure 6 represent the various modes of the SPI Master.

Figure 5: Data Transfer on the SPI Bus with CPHA=0


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10

Figure 6: Data Transfer on the SPI Bus with CPHA=1

Pulse Width Modulator ControllerThe PWM has following features:

• Intelligently controlled by the DPO block

• 16-bit register to load count, based on which PWM width is to be generated

• Configurable PWM_clk prescale factors of /1 to /1024 of the system clock

• Duty Cycle = Mark Period/Frame Period = Data Value/2n

• Mark Period = Data value*Tclock

• Frame Period = Tclock*2n

• 16-bit PWM Core, n = 16

Figure 7 shows the PWM timing block diagram.

Figure 7: PWM Timing Block Diagram

Mark Period Frame PeriodData Value*Tclock 2n*Tclock






Clock and Reset ControllerFigure 8 shows the Clock and Reset Controller block diagram.

Figure 8: Clock and Reset Block Diagram

There are two levels of clock gating. The first level clock gating is global clock gating, which is based on the use case. The second level clock gating is at the module level, which is based on software configured CSSP global register enables and/or VLP control register set 1/2 enables in VLP mode, as described in Very Low Power Mode on page 17.

PLLclk_in

sd_clk

pixel_clkGating

Gating

use case = “RGBin-RGBout no framebuffer”

Note: Clocks in respective modules shall be gated with software configured register bits.

clk_in_FB

pixel_clk_in

Div/2,/4,/8

sd_clk, /2, /4, /8

/4, /8FB_clk SPI_clk

FB_clk

pixel_clk = pixel_clock_in for “RGBin-RGBout no framebuffer”; else use PLL output

/1 to /1024 PWM_clk

Control from FB

Control from FB

Control from FB

Control from FB

Delay BuffersSystem

Reset_n

Reset in respective clock

domainClock

pixel_clkinFIFO_clk

FB_clk Gating


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12

Phased Locked Loop ControllerThe ArcticLink II VX2 solution platform contains a PLL and corresponding controller for sending user specified clock frequencies to the various logical blocks in the core, VEE block, frame buffer, and programmable Fabric. The input to the PLL is the dedicated input signal SYS_CLK. There are three outputs from the PLL: SD_CLK, Clk_in_FB, and pixel_clock_out. Note, if the frame buffer is not enabled, pixel_clock_out is routed from pixel_clock_in instead.

The default behavior of the PLL is determined by the values of the settings to the core. Each option can also be changed after powering up by modifying the equivalent configuration register. Table 1 lists each PLL configuration anti-fuse and its corresponding register.

The range of the PLL internal clock after multiplying, but before dividing, is 400 MHz to 550 MHz. If the range select (rIn_RNG_Sel) is set to 32 kHz, the output frequency is based on two multipliers; 128x and rVCOM.

Each multiplier and divider factor has a 7-bit binary value that configures the PLL. Refer to Table 2 and Table 3 for the value to enter into the anti-fuse and registers. As an example, to set the PLL multiplier rVCOM to 26 decimal, enter the value 0x34 into rVCOM as shown in Table 2. When choosing a value for SD_Clk, the frequency must range between 95 MHz and 103 MHz.

The following is an example of using a 19.2 MHz input clock, and converting it to a 99.84 MHz SD_Clk and 33.28 MHz pixel_clock_out.

SYS_CLK = 19.2 MHz

PLL multiplier = 26 (rVCOM = 0x34, as per Table 2)

PLL internal clock before dividing = 499.2 MHz

PLL SD_Clk divider = 5 (rSdClkDiv = 0x60, as per Table 3)

PLL pixel_clock_out divider = 15 (rPixelClkDiv = 0x5F, as per Table 3)

SD_Clk = (499.2 MHz/5) = 99.84 MHz

Pixel_clock_out = (499.2 MHz/15) = 33.28 MHz

Table 1: PLL Anti-fuse Settings

Anti-fuse NameBit

WidthDescription

Register Name

Register Address

Bit(s)

AF_pll_in_rng_sel 1

PLL input Range select.0 – 8 MHz to 20 MHz1 – 32 kHz

If set to '1', there is a fixed 128x multiplier applied to the clock.

rIn_RNG_Sel 0x020010 3

AF_pll_by_oenb 1Enable signal for the path from the PLL input directly to Clk_in_FB signal to the Fabric.

rPLLBypass 0x020010 0

AF_pll_cm 7 Multiplication factor for the PLL. rVCOM 0x020014 [6:0]

AF_pll_coa 7 Division factor for the PLL pixel clock. rSdClkDiv 0x020014 [13:7]

AF_pll_cob 7 Division factor for SD_CLK. rPixelClkDiv 0x020014 [20:14]






Table 2: VCO Multiplication Factor

M rVCOM M rVCOM M rVCOM M rVCOM

1 0x7F 33 0x39 65 0x71 97 0x0D

2 0x00 34 0x1C 66 0x78 98 0x06

3 0x40 35 0x4E 67 0x3C 99 0x43

4 0x20 36 0x27 68 0x5E 100 0x61

5 0x50 37 0x13 69 0x2F 101 0x70

6 0x28 38 0x09 70 0x17 102 0x38

7 0x54 39 0x04 71 0x0B 103 0x5C

8 0x2A 40 0x42 72 0x05 104 0x2E

9 0x55 41 0x21 73 0x02 105 0x57

10 0x6A 42 0x10 74 0x41 106 0x6B

11 0x35 43 0x48 75 0x60 107 0x75

12 0x1A 44 0x24 76 0x30 108 0x7A

13 0x4D 45 0x52 77 0x58 109 0x3D

14 0x66 46 0x29 78 0x2C 110 0x1E

15 0x33 47 0x14 79 0x56 111 0x4F

16 0x19 48 0x4A 80 0x2B 112 0x67

17 0x0C 49 0x25 81 0x15 113 0x73

18 0x46 50 0x12 82 0x0A 114 0x79

19 0x23 51 0x49 83 0x45 115 0x7C

20 0x11 52 0x64 84 0x62 116 0x3E

21 0x08 53 0x32 85 0x31 117 0x5F

22 0x44 54 0x59 86 0x18 118 0x6F

23 0x22 55 0x6C 87 0x4C 119 0x77

24 0x51 56 0x36 88 0x26 120 0x7B

25 0x68 57 0x5B 89 0x53 121 0x7D

26 0x34 58 0x6D 90 0x69 122 0x7E

27 0x5A 59 0x76 91 0x74 123 0x3F

28 0x2D 60 0x3B 92 0x3A 124 0x1F

29 0x16 61 0x1D 93 0x5D 125 0x0F

30 0x4B 62 0x0E 94 0x6E 126 0x07

31 0x65 63 0x47 95 0x37 127 0x03

32 0x72 64 0x63 96 0x1B 128 0x01


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14

Table 3: SD Clock and Pixel Clock Division Factor

Divider r*ClkDiv Divider r*ClkDiv Divider r*ClkDiv Divider r*ClkDiv

1 0x7F 33 0x79 65 0x4E 97 0x51

2 0x3F 34 0x39 66 0x0E 98 0x11

3 0x40 35 0x5C 67 0x47 99 0x48

4 0x00 36 0x1C 68 0x07 100 0x08

5 0x60 37 0x6E 69 0x63 101 0x64

6 0x20 38 0x2E 70 0x23 102 0x24

7 0x70 39 0x57 71 0x71 103 0x72

8 0x30 40 0x17 72 0x31 104 0x32

9 0x78 41 0x6B 73 0x58 105 0x59

10 0x38 42 0x2B 74 0x18 106 0x19

11 0x7C 43 0x75 75 0x6C 107 0x4C

12 0x3C 44 0x35 76 0x2C 108 0x0C

13 0x7E 45 0x5A 77 0x76 109 0x66

14 0x3E 46 0x1A 78 0x36 110 0x26

15 0x5F 47 0x4D 79 0x5B 111 0x53

16 0x1F 48 0x0D 80 0x1B 112 0x13

17 0x6F 49 0x46 81 0x6D 113 0x69

18 0x2F 50 0x06 82 0x2D 114 0x29

19 0x77 51 0x43 83 0x56 115 0x54

20 0x37 52 0x03 84 0x16 116 0x14

21 0x7B 53 0x61 85 0x4B 117 0x6A

22 0x3B 54 0x21 86 0x0B 118 0x2A

23 0x7D 55 0x50 87 0x65 119 0x55

24 0x3D 56 0x10 88 0x25 120 0x15

25 0x5E 57 0x68 89 0x52 121 0x4A

26 0x1E 58 0x28 90 0x12 122 0x0A

27 0x4F 59 0x74 91 0x49 123 0x45

28 0x0F 60 0x34 92 0x09 124 0x05

29 0x67 61 0x7A 93 0x44 125 0x42

30 0x27 62 0x3A 94 0x04 126 0x02

31 0x73 63 0x5D 95 0x62 127 0x41

32 0x33 64 0x1D 96 0x22 128 0x01






Customizable LCD ControllerThe CSSP can enable OEMs and ODMs to adapt their system to a multitude of display types and interfaces. Currently, most displays used by OEMs and ODMs have varying color formats, resolutions, color depth, and control signals for the LCD module.

The LCD Controller can be used to support the following:

• RGB888, RGB666, and RGB565

• Programmable HSYNC/VSYNC timing

• Programmable viewing area and blanking/porch

• Programmable polarity on pixel clock

• Up to WXGA (1366x768 resolution)

• Refresh rates exceeding 60 frames per second

• Programmable PWM for controlling the backlight LEDs

• Support for dumb (RGB) display

• Support for secondary smart display or TV Encoder device.

As shown in Figure 9, the customizable LCD Controller is used to tailor the LCD controller to the exact requirements of the display. This includes resolution, viewable frame dimensions, and all control signaling.


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Figure 9: Customizable LCD Controller

I2CClient

Registers

Bus Controller

Frame Width

Frame Height

Blanking/Porch


IncomingRGB FIFO

Write AddrGenerator

Read AddrGenerator

OutgoingRGB FIFO

32 kHzOscillator

PL

L~ MHzOscillator

PL

L

LCD

RG

B’

HS

YN

C’

VS

YN

C’

DE

’

PIX

EL

_C

LK

’

RG

B

HS

YN

C

VS

YN

C

DE

PIX

EL

_C

LK

CustomizableLCD

Controller

DPO

PWM

MobileProcessor

SPIMaster

FrameBufferCTRL

Ce

llu

larR

AMAddress

Data

Controls

TimingController

(TCON)






I2C Client Device Address

The I2C interface is used to configure and control the internal registers and look-up tables. The QuickLogic CSSP requires an 8-bit device address word following a start condition to enable the device for a read or write operation (see Figure 10). Refer to the CSSP Registers and Descriptions on page 46 for detailed register descriptions.

I2C AC Timing

The QuickLogic CSSP meets all AC timing characteristics as detailed in The I2C-Bus Specification, Version 2.1.

Very Low Power ModeThe QuickLogic CSSP has a unique feature, referred to as VLP mode, which reduces power consumption by placing the device in standby or hibernate mode. Specifically, VLP mode can bring the programmable Fabric standby current down to less than 10 µA at room temperature when no incoming signals are toggled. This architecture feature was designed with the understanding that, most of the time, a handset is in standby mode – particularly the LCD – and every microWatt is crucial to maintaining a long battery life.

VLP mode is controlled by the VLP pin. The VLP pin is active low, so VLP mode is activated by pulling the VLP pin to Logic Low. Conversely, the VLP pin must be pulled to Logic High for normal operation. VLP allows for fine grain control of all elements of the ArcticLink II VX2 solution platform, with VLP registers allowing the CSSP to selectively apply VLP to each of the following:

• GPIO

• The fixed logic and fixed logic I/O

• PLL and CCM

When the ArcticLink II VX2 solution platform goes into VLP mode, the following occurs:

• All register values in the programmable Fabric and GPIO are preserved

• All RAM cell data is retained

• The outputs from all GPIO to the internal logic are tied to a ‘0’

• GPIO outputs drive the previous values

• GPIO output enables retain the previous values

• Clock pad inputs are gated

• The CCM is held in the reset state

Figure 10: Device Address

0 1 0 1 0 1 0 R/W

MSB LSB


17



18

The entire operation from normal mode to VLP mode requires 10 µs. As mentioned in the VLP behavioral description previously, the output of the GPIO to the internal logic is a ‘0’. Therefore, to preserve data retention GPIO should not be used for a set, reset, or clock signal.

As the ArcticLink II VX2 solution platform exits out of VLP mode, the data from the registers, RAM, and GPIO will be used to recover the functionality of the device. Furthermore, since the CCM is in a reset state during VLP mode, it will have to re-acquire the correct output signals before asserting lock_out. The time required to go from VLP mode to normal operation is 10 µs.

Figure 11 displays the delays associated with entering and exiting VLP mode.

Figure 11: Typical VLP Mode Timing

A VLP pin is used for setting the fixed logic region low power modes by the host. The actual low power modes are configured in a register of the fixed logic region by the host to put the fixed logic/Fabric core/IO, PLL, and/or transceivers into power-down modes.

Four GPIO pins (in Bank D) are used for event and interrupt, and are routed to the programmable Fabric from the fixed logic. These GPIOs have a programmable VLP disable bit (GPIO_VLP_CTRL). The logic in the programmable Fabric processes these signals and sends an interrupt to the host if needed through one of the GPIO. The programmable Fabric core is kept active before enabling these GPIOs. When an interrupt is received the host will determine whether to come out of VLP mode. The low power modes are enabled by clock gating in the fixed logic and core and/or I/O low power modes in the programmable Fabric.

Figure 12: Programmable Fabric Banks

VLP pin

VLP status VLP mode

NormalOperation

VLP inactive VLP inactive

250us 250us10 µs10 µs

Fabric Bank A

Bank BBank C

Bank D Bank E






Programmable Fabric VLP Modes

The programmable Fabric VLP modes (excluding the four special VLP GPIOs) are as follows:

• Both the programmable Fabric core and I/Os are in VLP mode

• The programmable Fabric core is active and the I/Os are in VLP mode – the programmable Fabric is used in conjunction with Bank D to monitor/control external events with the programmable Fabric core logic during VLP mode

• Both the programmable Fabric core and I/Os are active – for applications that utilize the VLP pin to put the fixed logic into low power without requiring programmable Fabric to be in low power

There are two programmable Fabric VLP control lines, which select one of the above modes. Table 4 shows the programmable Fabric VLP Modes.

Fixed Logic VLP Modes

The fixed logic VLP modes are as follows:

• The clock is gated out on fixed logic through registers (control on per block basis) – TCON, VEE, PWM, SPI, CellRAM, incoming FIFO and Write address generator, Outgoing FIFO and Read address generator

Fixed Logic Analog Block VLP Modes

The fixed logic analog block VLP modes are as follows:

• Analog blocks are disabled (different low power states) through PLL registers

There are three power down modes per clock for PLL – VCO off, Clock div off, Clock output off

Table 4: Programmable Fabric VLP Modes

FB_VLP_CTRL<1:0>

Programmable Fabric VLP Mode

Programmable Fabric Core

I/Os

00 VLP mode VLP mode

01 Active VLP mode

10 Active Active

11 Reserved


19



20

Implementation of VLP ModeFigure 13 shows how VLP control registers are programmed.

Figure 13: Programming VLP Control Registers

VLP_assp is a VLP enable indication from the programmable Fabric. This selects the VLP control register settings. When VLP_assp is not asserted, the ASSP global register setting is applied as a block level clock enables. When in VLP mode, one of the two available control register settings are applied to block level clock enables based on the VLP control select register setting.

Global Clock RegisterThe Global Clock register consists of the following bits and functions:

• Each block has a separate clock enable bit

• One bit for global low power

• Register reset state can be tied off to lowest power state

Table 5 shows the Global Clock register bits and their description.

Table 5: Global Clock Register

Bit No.Description

(Default: 0x00000000)

0 Global clock enable.

1 VEE enable.

2 CellRAM enable.

3 TCON enable.

4 PWM enable.

5 SPI enable.

6 Reserved.

7 Incoming FIFO and Write address generator enable.

Functional Block N

Functional Block 2

Functional Block 1

A2F Control Bus

Antifuse at Reset

Lowest Power Setting at Reset

Functional Block 0

VLP Control Register set 1

VLP Control Register set 2

VLP Control Select Register

Fixed Logic Global Registers

VLP _assp

Enables






VLP Control Register SetsTable 7 shows the VLP Control Register Set 1 bits and their description

Bit No.Description

(Default: 0x00000000)

8 Outgoing FIFO and Read address generator enable.

9

VLP control select register. Selects which register set is going to be used during VLP mode. See VLP Control Register Sets on page 21 for a detailed description of the VLP Control Register Sets 1/2. See also, rVLP_Ctrl_Sel in the Global Clock Register on page 57 for a definition of the VLP Control Register Sets 1/2 option.

10 FB_Clk enable for inFIFO_clk generation only.

11:31 Reserved.

Table 6: VLP Control Register Set 1

Bit No. Description (Default: Anti-fuse – Set 1)

1:0

00 – FB_core: VLP ModeIOs: VLP mode

01 – FB_core: ActiveIOs: VLP mode

10 – FB_core: ActiveIOs: Active

11 – Reserved

2 Used in conjunction with rFB_VLP_CTRL. To be gated and passed only if FB_VLP_Ctrl is 01 or 10.

3 This is the VLP mode enable for TCON block. If set VLP mode is disabled.

4 This is the VLP mode enable for PWM block. If set VLP mode is disabled.

5 This is the VLP mode enable for SPI block. If set VLP mode is disabled.

6 Reserved.

7 This is the VLP mode enable for Incoming FIFO block. If set VLP mode is disabled.

8 This is the VLP mode enable for Outgoing FIFO block. If set VLP mode is disabled.

9 If set will switch off Pixel clock.

10 If set will switch off the SD clock.

11 If set powers down the PLL.

15:12 Reserved.

Table 5: Global Clock Register (Continued)


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22

NOTE: GPIO_VLP_CTRL is gated and passed only if FB_VLP_CTRL is 01 or 10.

Table 8 shows the VLP Control Register Set 2 bits and their description

Clocks and ResetTable 9 describes the Clocks and Reset signals.


Bit No. Description (Default: Anti-fuse – Set 1)

1:0




11 – Reserved

2 Used in conjunction with rFB_VLP_CTRL. To be gated and passed only if FB_VLP_Ctrl is 01 or 10

3 This is the VLP mode enable for TCON block. If set VLP mode is disabled

4 This is the VLP mode enable for PWM block. If set VLP mode is disabled

5 This is the VLP mode enable for SPI block. If set VLP mode is disabled

6 Reserved

7 This is the VLP mode enable for Incoming FIFO block. If set VLP mode is disabled

8 This is the VLP mode enable for Outgoing FIFO block. If set VLP mode is disabled

9 If set will switch off Pixel clock

10 If set will switch off the SD clock

11 If set powers down the PLL

15:12 Reserved


Bit No. Description (Default: 0x0000_1E00 – Set 2)

16:31 Reserved

Table 9: ArcticLink II VX2 Solution Platform Clocks and Reset Signals

Clock Name Frequency Description

SYS_CLK32 kHz or 8 MHz to 20 MHz

System Clock. Input to internal PLL.

SYS_RST_n Not Applicable System Reset for CSSP.






Various Data Paths

RGB-In to RGB-Out with No Frame BufferFigure 14 shows the RGB-In to RGB-Out with no Frame Buffer data flow.

Figure 14: Data Flow – RGB-In to RGB-Out with No Frame Buffer

NOTE: The grey boxes showing part of the programmable fabric are indicative and part of the logic in the programmable fabric. Also, the interface shown through the programmable fabric is indicative and will be decided by a discussion between the customer and QuickLogic.

The following list describes the use case:

• I2C slave is used to access fixed logic registers

• A2F register bus is used with programmable fabric as a master through the F2A bus

• PLL is in BYPASS mode, pixel_clk_in from RGB-in is used as pixel_clk for RGB-out

• RGB-in and RGB-out are running at 60 fps

• Use VEE bypass when VEE clock is gated

• Fixed logic register bus clock is FB_clk

Fabric

Fixed Logic

VEE

reg bus ctrl

Timing Controller

Outgoing RGB FIFO

(2Kbytes)

Clock & Reset

Controller

SPI Master

Incoming RGB FIFO

(2Kbytes)

A2F Bus

Master

F2A bus

Register/External Memory Access from FB

F2A Control Bus from Fabric

RGB in from Fabric

PWM Controller

RGB in from Fabric

I2C Slave

I2C Master

master

CPU IF

Reg access to FB IPs

RGB in from Fabric

RG

B O

ut

SP

I

RGB888

Conver-sion

PW

M

RG

B In


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24

The following clocks are gated in this use case:

• sd_clk

• PLL_pixel_clk

The following multiplexed/divided clocks are inactive (due to other gated clocks) in this use case:

• inFIFO_clk

• Sd_clk_by_2_4_8

The following clocks are active in this use case:

• pixel_clk_in

• pixel_clk

• clk_in

• clk_in_FB

• FB_clk

• SPI_clk

• PWM_clk






RGB-In to RGB-Out with Frame BufferFigure 15 shows the RGB-In to RGB-Out with Frame Buffer data flow.

Figure 15: Data Flow – RGB-In to RGB-Out with Frame Buffer



• I2C slave used to access registers

• A2F register bus is used with FB as master through F2A

• RGB-in interface is running at =< 30 fps

• RGB-out is interface is running at 60 fps

• PLL is used to generate PLL_pixel_clk and sd_clk from clk_in


• Incoming FIFO push clock – pixel_clk_in; pop clock – sd_clk

• Outgoing FIFO push clock – sd_clk; pop clock – PLL_pixel_clk

• TCON, VEE clock – PLL_pixel_clk

• No clocks are gated

• Fixed logic register bus clock will be FB_clk

Fabric

Fixed Logic

VEE

reg bus ctrl write addr Generator

Timing Controller

read addr Generator

CellRAM Memory Control ler

Outgoing RGB FIFO

(2Kbytes)

Address

Data

Controls

Clock & Reset

Controller

SPI Master

Reg access to FB IPs

Incoming RGB FIFO

(2Kbytes)

A2F Bus

Master

F2A Bus

RGB in from Fabric

Register/External Memory Access

from FB

F2A control bus from Fabric

RGB in from Fabric

PWM Controller

RGB in from Fabric

I2C Slave

I2C Master

Master

CellRAM

CPU IF

RGB888

Conver-sion

RG

B In

RG

B O

ut

SP

I

PW

M


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26

EBI-Compatible Interface to RGB-out with Frame Buffer (Video though F2A Control Access)Figure 16 shows the EBI-Compatible Interface to RGB-Out with Frame Buffer data flow.

Figure 16: Data Flow – EBI-Compatible Interface to RGB-Out with Frame Buffer



• I2C slave is used to program registers

• A2F register bus is used with programmable fabric as a master through F2A

• EBI interface is running at =< 30 fps

• RGB-out is interface is running at 60 fps

• PLL is used to generate PLL_pixel_clk and sd_clk from clk_in


• Incoming FIFO push clock – FB_clk; pop clock – sd_clk

• Outgoing FIFO push clock – sd_clk; pop clock – PLL_pixel_clk

• TCON, VEE clock – PLL_pixel_clk

• No clocks are gated

• Fixed logic register bus clock is FB_clk

Fabric

Fixed Logic

VEE

write addr Generator

Timing Controller

read addr Generator

CellRAM Memory

Controller

Outgoing RGB FIFO

(2 Kbytes)

Address

Data

Controls

Clock & Reset

Controller

SPI Master

Reg

Access to FB IPs

Incoming RGB FIFO

A2F Vus

Master

F2

RGB in from Fabric

Register/External

F2A control bus from Fabric

RGB in from Fabric

PWM Controller

PW

M

RGB in

I2C I2C Master

CPU IF

A bus Master

Memory Access from FB

from Fabric

Kbytes)2 (

RGB888

Conver-sion

reg bus ctrl

Slave

CellRAM

SP

I

RG

B O

ut

RG

B In






Programmable Fabric Use Cases

The following subsections represent some of the possible functionality for the onboard programmable Fabric. While these are commonly used functions, it is not an exhaustive list. To see if other functionality you require can be implemented, contact a QuickLogic Customer Solutions Architect (CSA). See Contact Information on page 82.

Multiple 2-Wire Serial InterfacesBecause the 2-wire serial interface crosses the fixed logic/programmable Fabric domains, the programmable Fabric and programmable GPIOs can be used to map the 2-wire serial Master to any number of 2-wire serial Slave devices, as shown in Figure 17. Since the programmable Fabric is used to map the 2-wire serial interface to the Master in the fixed logic, multiple serial interfaces can be used for the peripherals including I2C, SPI, UARTs and others. Figure 17 illustrates this concept.


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28

Figure 17: Mapping a Single 2-Wire Serial Master to a Multiple 2-Wire Serial Slave Devices

Programmable Fabric

27 Customizable Building BlocksP

LL

PL

L I2CClient

Registers

Bus Controller

Frame Width

Frame Height

Blanking/Porch


IncomingRGB FIFO

Write AddrGenerator

Read AddrGenerator

OutgoingRGB FIFO

FrameBufferCTRL

Ce

llula

rRA

M

RG

BAddress

Data

Controls

Fixed Logic

32 kHzOscillator

~ MHzOscillator

Control

MobileDisplay

MobileProcessor

Proxi-mity

Sensor

Acceler-ometerS

AmbientLight

Sensor

TouchScreen

Ctrl

A

S

E-PaperCtrl

Temp.Sensor

Peripherals

SPIMaster

DPO

PWM

TimingController

(TCON)






Programmable Fabric Architectural Overview

The ArcticLink II VX2 solution platform contains an ultra-low power programmable logic based on the QuickLogic patented ViaLink technology, which provides for quick customization of the platform and implementing additional proven system blocks for OEMs and ODMs by the QuickLogic System Solution Group. The programmable Fabric is ideal for customization of the ArcticLink II VX2 solution platform, truly enabling the platform-based design methodology.

The programmable Fabric consists of 27 CBBs to implement combinations of different interfaces required by the customer design specifications, which results in much higher integration, more flexibility, lower system power consumption, and lower BOM costs. A CBB is a unit of measurement that represents the on-chip logic that can be used to implement a variety of proven system blocks (such as SD/MMC/SDIO, SPI, I2C, LCD Controller, and other serial peripheral interfaces), custom logic, or other system level functions (see Table 10 for a list of proven system blocks).

Table 10: Proven System Blocks Provided by QuickLogic

Proven System Blocks for Each Technology Segment

Storage Network

• IDE/P-ATA Host Controller • SDIO Client

• CE-ATA Host Controller • High-Speed SDIO Controller

• NAND Flash Controller • SPI Controller

• Secure Digital (SD) Card Host Controller • Bluetooth 2.x + EDR High-Speed UART

• Compact Flash (CF) Host Controller Video and Imaging

• Multimedia Card (MMC) Controller • X/Y Swap

• Memory Stick (MS) Controller • High-Definition LCD Controller

• Managed NAND Controller with Boot Capability • Visual Enhancement Engine (VEE)

• Optical Drive Controller (ATAPI)

Intelligence Security and Custom Options

• Direct Memory Access (DMA) • Content Protection for Recordable Media (CPRM)

• Smart Data Transfer (SDT) • Serial ID

• Data Aggregator (DA)


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RAM ModulesThe ArcticLink II VX2 solution platformhas four 4-kilobit (4,608 bits) and four 2-kilobit (2,304 bits) multiple RAM blocks which are used primarily as buffers and FIFOs to significantly improve system performance.

The RAM features include:

• Independently configurable read and write data bus widths

• Independent read and write clocks

• Horizontal and vertical concatenation

• Write byte enables

• Selectable pipelined or non-pipelined read data

• Ability to generate true dual-port RAMs through concatenation with completely independent read/write ports and clock domains

• Clock disabling during idle operation

Embedded FIFO ControllersEvery RAM block can be implemented as a synchronous or asynchronous FIFO. There are built-in FIFO controllers that allow for varying depths and widths without requiring programmable Fabric resources. The ArcticLink II VX2 solution platformFIFO Controller features include:

• x9, x18 and x36 data bus widths

• Independent PUSH and POP clocks

• Independent programmable data width on PUSH and POP sides

• Configurable synchronous or asynchronous FIFO operation

• 4-bit PUSH and POP level indicators to provide FIFO status outputs for each port

• Pipelined read data to improve timing

• Switchable clock domain between PUSH and POP side during asynchronous operation

• Clock disabling during idle operation

• Asynchronous reset (apart from the synchronous FLUSH) going to the pointers






Configurable Clock Manager – Onboard Clock Generation for the Programmable FabricThe CCM is used for generating the necessary clocks for the proven system blocks and other custom logic implemented in the programmable Fabric portion of the platform. The CCM accepts a higher frequency reference clock than the PLL in the fixed logic portion of the platform (in the MHz range) and is suitable for accepting the clock frequency typically used as the active clock in handsets, such as 26 MHz for UMTS handsets and 19.2 MHz for CDMA handsets.

The CCM includes a PLL component, a frequency multiplier, and phase modifier. The PLL is a closed loop frequency control system that detects the phase difference between the input and output signals and aligns them. The frequency multiplier adds the ability to multiply the input frequency by a configurable factor of two or four. Additionally, the phase modifier supports the ability to shift the output frequency phase and offset by a given time delay.

The QuickLogic ArcticLink II VX2 solution platformhas one CCM available to any function in the programmable Fabric area. The CCM features include:

• Input frequency range from 10 MHz to 200 MHz, depending on the CCM mode

• Output frequency range from 25 MHz to 200 MHz, depending on the CCM mode

• Output jitter is less than 200 ps peak-to-peak

• Two outputs: pullout0 (with 0° phase shift), and pullout1 (with an option of 0°, 90°, 180°, or 270° phase shift plus a programmable delay)

• Programmable delay allows delays up to 2.5 ns at 250 ps intervals

• Output frequency lock time in less than 10 µs

The reset signal can be routed from a clock pad or generated using internal logic. The lock_out signal can be routed to internal logic and/or an output pad. CCM clock outputs can drive the global clock networks, as well as any general purpose I/O pin. Once the CCM has synchronized the output clock to the incoming clock, the lock_out signal will be asserted to indicate that the output clock is valid. Lock detection requires at least 10 µs after reset to assert lock_out. The ArcticLink II VX2 solution platformCCM has three modes of operation, based on the input frequency and desired output frequency. Table 11 indicates the features of each mode.

Table 11: CCM PLL Mode Frequencies

Output Frequency

Input Frequency Range

Output Frequency Range

PLL Mode

x1 25 MHz to 200 MHz 25 MHz to 200 MHz PLL_MULT1




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Electrical Specifications

DC CharacteristicsThe DC Specifications are provided in Table 12 through Table 15.

Table 12: Absolute Maximum Ratings

Parameter Value Parameter Value

VCC Voltage -0.5 V to 2.2 V ESD Pad Protection 2 kV

VCCIO Voltage -0.5 V to 4.0 VLeaded Package

Storage Temperature-65° C to + 150° C

Input Voltage -0.5 V to 4.0 V Laminate Package (BGA)Storage Temperature

-55° C to + 125° CLatch-up Immunity ±100 mA

Table 13: Recommended Operating Range

Symbol ParameterCommercial

UnitMin. Max.

VCC Supply voltage 1.43 1.89 V

VINPUT I/O input tolerance voltage -0.2 VCCIO +0.2 V

VCC CCM1 and VCC CCM2 PLL and CCM voltage 1.43 1.89 V

VCC_CELLRAM Frame buffer voltage 1.71 1.89 V

TJ Junction temperature -20 100 °C

Table 14: DC Characteristics

Symbol Parameter Conditions Min. Typ. Max. Units

Il I or I/O Input Leakage Current VI = VCCIO or GND - - 1 µA

IOZ 3-State Output Leakage Current VI = VCCIO or GND - - 1 µA

CI I/O Input Capacitance VCCIO = 3.6 V - - 10 pF

CCLOCK Clock Input Capacitance VCCIO = 3.6 V - - 8 pF

IREF Quiescent Current on INREF - - - 5 µA

IPD Current on programmable pull-down

VCCIO = 3.6 V - - 159 µA

VCCIO = 2.75 V - - 100 µA

VCCIO = 1.89 V - - 50 µA

IVLP Quiescent Current on VLP pin VLP=3.3 - 1 10 µA

ICCM Quiescent Current on CCMVCC VCC=1.89 V - - 1 µA

IVCC Quiescent Current VLP=GND - 76 142 µA

IVCCIO Quiescent Current on VCCIO

VCCIO = 3.6 V - 2 10 µA

VCCIO = 2.75 V - 2 10 µA

VCCIO = 1.89 V - 2 10 µA






Package Thermal CharacteristicsThe ArcticLink II VX2 solution platform is available for the Commercial (-20°C to 85°C Ambient) temperature range.

Thermal Resistance Equations:

θJC = (TJ - TC)/P θJA = (TJ - TA)/PPMAX = (TJMAX - TAMAX)/θJA

Parameter Description:

θJC: Junction-to-case thermal resistance

θJA: Junction-to-ambient thermal resistance

TJ: Junction temperature

TA: Ambient temperature

P: Power dissipated by the device while operating

PMAX: The maximum power dissipation for the device

TJMAX: Maximum junction temperature

TAMAX: Maximum ambient temperature

NOTE: Maximum junction temperature (TJMAX) is 100°C. To calculate the maximum power dissipation for a device package look up θJA from Table 16, pick an appropriate TAMAX and use: PMAX = (125°C - TAMAX)/ θJA

Table 15: DC Input and Output Levelsa

a. The data provided in Table 15 represents the JEDEC and PCI specification. The ArcticLink II VX2 solution platform either meet or exceed these requirements.

SymbolINREF VIL VIH VOL VOH IOL IOH

VMINVMA

XVMIN VMAX VMIN VMAX VMAX VMIN mA mA

LVTTL n/a n/a -0.3 0.8 2.2 VCCIO + 0.3 0.4 2.4 2.0 -2.0

LVCMOS2 n/a n/a -0.3 0.7 1.7 VCCIO + 0.3 0.7 1.7 2.0 -2.0

LVCMOS18

n/a n/a -0.3 0.63 1.2 VCCIO + 0.3 0.7 1.7 2.0 -2.0

Table 16: Package Thermal Characteristicsa

a. Contact QuickLogic for θJA values.

Package Description θJA (°C/W) θJC (°C/W)Solution

PlatformPackage

CodePackage Type Pin Count 0 LFM 200 LFM 400 LFM

ArcticLink II VX2

PUTFBGA

(6 mm x 6 mm)121 TBD TBD TBD TBD


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Power Consumption

Programmable Fabric Power ConsumptionThe ultra low power programmable Fabric developed by QuickLogic is ideal for implementing customized display subsystem control and connectivity solutions, additional memory and peripheral subsystem functionality custom logic and processor interfaces. The standby current of the ArcticLink II VX2 solution platform Fabric in VLP mode is as low as 5 µA. The dynamic power consumption varies depending on the operating conditions and what functions are used in the Fabric.

Platform Power ConsumptionTable 17 shows the power consumption without a Frame Buffer for various operating modes. Table 18 shows the power consumption rates with a Frame Buffer for various operating modes. The following assumptions apply:

• RGB out Load = 10 pF

• RGB toggle rate = 20%

Table 17: Power Consumption without Frame Buffer

VCC (V)

Display Horizontal VerticalPixel Clock Max. MHz (VESA with

Margin)

VEE Power (mW)

1.5

VGA 640 480 25 40

WVGA 800 480 31 50

FWVGA 854 480 33 52

SVGA 800 600 40 61

W-SVGA 1024 600 51 75

XGA 1024 768 68 97

WXGA 1280 768 84 111

WXGA 1366 768 85 118

1.8

VGA 640 480 25 57

WVGA 800 480 31 70

FWVGA 854 480 33 74

SVGA 800 600 40 88

W-SVGA 1024 600 51 107

XGA 1024 768 68 139

WXGA 1280 768 84 160

WXGA 1366 768 85 171






Table 19 shows the VCCIO power consumption without a Frame Buffer. Table 20 shows the VCCIO power consumption with a Frame Buffer.

Table 18: Power Consumption with Frame Buffera,b,c

a. The PLL is on to generate the frame buffer clock as well as the RGB pixel out clock.

b. The frame buffer clock is estimated as 1.7 * pixel clock out. Pixel clock out is for 60 fps, + 0.5 x pixel clock out forpixel clock in at 30 fps + 20% overhead.

c. CellularRAM voltage is always 1.8 V.

VCC (V)

DisplayHorizontal

PixelsVertical Pixels

Pixel Clock Out

(MHz)

VEE + CellularRAM Ctrl

+ PLL Power (mW)

CellRAM Power (mW)

1.5

VGA 640 480 25 60 24

WVGA 800 480 31 65 27

FWVGA 854 480 33 69 29

SVGA 800 600 40 76 33

W-SVGA 1024 600 52 106 42

XGA 1024 768 68 Contact QuickLogic

WXGA 1280 768 85 Not Supported

1.8

VGA 640 480 25 89 24

WVGA 800 480 31 96 27

FWVGA 854 480 33 100 29

SVGA 800 600 40 110 33

W-SVGA 1024 600 52 134 42

XGA 1024 768 68 Contact QuickLogic

WXGA 1280 768 85 Not Supported

Table 19: VCCIO Power Consumption without Frame Buffer

ResolutionHorizontal

PixelsVerticalPixels

Pixel Clock (MHz)

Color Depth

I/O Power(mW)

VCCIO = 1.8 V

I/O Power(mW)

VCCIO = 2.5 V

I/O Power(mW)

VCCIO = 3.3 V

VGA 640 480 2518 7 10 16

24 8 12 19

WVGA 800 480 3118 8 12 19

24 9 14 23

FWVGA 854 480 3318 8 12 20

24 9 15 24

SVGA 800 600 4018 9 15 23

24 11 18 28

W-SVGA 1024 600 5218 11 18 29

24 13 22 36


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36

Moisture Sensitivity Level

All TFBGA devices are Moisture Sensitivity Level 3.

XGA 1024 768 6818 13 23 37

24 16 28 46

WXGA 1280 768 8418 16 27 46

24 19 34 57

WXGA 1366 768 8518 17 29 49

24 20 36 61

Table 20: VCCIO Power Consumption with Frame Buffer



Pixel Clock (MHz)

Color Depth

I/O Power(mW)

VCCIO = 1.8 V

I/O Power(mW)

VCCIO = 2.5 V

I/O Power(mW)

VCCIO = 3.3 V

VGA 640 480 2518 7 10 16

24 8 12 19

WVGA 800 480 3118 8 12 19

24 9 14 23

FWVGA 854 480 3318 8 12 20

24 9 15 24

SVGA 800 600 4018 9 15 23

24 11 18 28

W-SVGA 1024 600 5218 11 18 29

24 13 22 36

XGA 1024 768 6818

Contact QuickLogic24

WXGA 1280 768 8418

Not Supported24

WXGA 1366 768 8518

24

Table 21: Solder Composition

Package Type Pin Count Lead Type Pb-Free

TFBGA (6 mm x 6 mm)

121 BGA Solder Sn-3Ag-Cu (Sn4, Ag, Cua)

a. Sn-3Ag-Cu (Sn, 4Ag, Cu) means that Ag can range from 3% to 4%. Cu is always 0.5%.

Table 19: VCCIO Power Consumption without Frame Buffer (Continued)



Pixel Clock (MHz)

Color Depth

I/O Power(mW)

VCCIO = 1.8 V

I/O Power(mW)

VCCIO = 2.5 V

I/O Power(mW)

VCCIO = 3.3 V






Reflow ProfileQuickLogic follows JEDEC specification JESD97 for lead-free devices. Figure 18 shows the Pb-free component preconditioning reflow profile.

Figure 18: Pb-Free Component Preconditioning Reflow Profile

Table 22 shows the Pb-free component preconditioning reflow profile.

Table 22: Pb-Free Component Preconditioning Reflow Profilea,b

a. The above conditions are used for component qualifications. This should not be interpreted as the recommended profile for board mounting. Customers should optimize their board mounting reflow profile based on their specific conditions such as board design, solder paste, etc.

b. All temperatures are measured on the package body surface.

Profile Feature Profile Conditions

Ramp-up rate 3°C/sec. max. (2°C/sec. typical)

Preheat time (from 150°C to 200°C) 60 to 180 sec. (80 to 100 sec. typical)

Time maintained above 217°C 60 to 150 sec. (80 to 100 sec. typical)

Peak temperature 260°C

Time within 5°C of actual peak 20 to 40 sec. (23 to 29 sec. typical)

Ramp-down rate 6°C/sec. max. (3°C/sec. typical)

Time from 25°C to peak temperature 8 min. max. (6 min. typical)


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CSSP Boot Sequence

Figure 19 illustrates the power-up and boot sequence for the QuickLogic CSSP.

Figure 19: Power-Up and Boot Sequence

Power-UpVCC/VCCIO/

VLP

ToggleSYS_RST_N

Load VEERegisters

Load VEELUT Values

ConfigureLCD

Enable VEE Disable VEE

Use the power-up sequence as described in the following Power-Up Sequencing.

Toggle SYS_RST_N for at least 20 ns. After the SYS_RST_N signal is asserted, the CSSP will work in bypass mode, passing the display input data to the LCD, unchanged.

Send commands directly to the LCD to configure the screen as per the requirements of the corresponding LCD being used.

Load the VEE Look-Up Table parameters to configure the VEE data processing memory.

Load LCD characteristics and VEE algorithm settings into the VEE registers toconfigure the VEE engine.

To turn VEE on and off, write a ‘1’ or ‘0’ to the VideoEnhancement Enable Register bit ‘0’ as specified in the CSSP Registers and Descriptions section of this specification.






Power-Up Sequencing

Figure 20: Power-Up Sequencing

Figure 20 shows an example where all VCCIO = 3.3 V, VPUMP = 3.3 V and VLP = 1.8 V. When powering up a ArcticLink II VX4C solution platform, VCC, VCCIO rails must take 10 µs or longer to reach the maximum value (refer to Figure 20). Ramping VCC and VCCIO faster than 10 µs can cause the device to behave improperly.

It is also important to ensure VCCIO and VLP are within 500 mV of VCC when ramping up the power supplies. In the case where VCCIO or VLP are greater than VCC by more than 500 mV an additional current draw can occur as VCC passes its threshold voltage. In a case where VCC is greater than VCCIO by more than 500 mV the protection diodes between the power supplies become forward biased. If this occurs then there will be an additional current load on the power supply. Having the diodes on can cause a reliability problem, since it can wear out the diodes and subsequently damage the internal transistors.

Figure 20 shows an example where all VCCIO = 3.3 V, VPUMP = 3.3 V and VLP = 1.8 V. When powering up a ArcticLink II VX2 solution platform, VCC, VCCIO rails must take 10 µs or longer to reach the maximum value (refer to Figure 20). Ramping VCC and VCCIO faster than 10 µs can cause the device to behave improperly.

It is also important to ensure VCCIO and VLP are within 500 mV of VCC when ramping up the power supplies. In the case where VCCIO or VLP are greater than VCC by more than 500 mV an additional current draw can occur as VCC passes its threshold voltage. In a case where VCC is greater than VCCIO by more than 500 mV the protection diodes between the power supplies become forward biased. If this occurs then there will be an additional current load on the power supply. Having the diodes on can cause a reliability problem, since it can wear out the diodes and subsequently damage the internal transistors.

Vo

ltag

e

VCCIO ,VPUMP

VCC , VLP

|VCCIO - VCC| MAX

Time

10 us

VCC


39



40

Memory Maps

Conventions

Read/Write Registers

Read/Write registers are registers with a single address defined. The fields of these registers can be defined with one or more of the attributes given in Table 23.

Set and Clear Registers

A Set and Clear register has two addresses defined: “Set Address” and “Clear Address”. For write operations, these two addresses show different behavior. A “one” written to a bit position in the “Set Address” causes the corresponding bit position in the register to be set, while a “zero” leaves the corresponding bit position in the register unaffected. Alternately, a “one” written to a bit position in the “Clear Address” causes the corresponding bit position in the register to be cleared, while a “zero” leaves the corresponding bit position in the register unaffected. The fields of these registers can be defined with one or more of the attributes given in Table 24. For a read operation on any of these two addresses, the current value of the register is returned.

Reserved Fields

All reserved fields are ignored on read and set as zeros during write operations unless otherwise specified.

Reserved Registers

Addresses within the address space that are reserved return zeros on read and writes are ignored unless otherwise specified.

Register Field Notation

In descriptions that refer to specific register fields/bits, the notation RrRr.ffFf is used where RrRr refers to the register and ffFf refers to the referenced field/bit within that register.

In a 32-bit register, bit number 31 is the most significant bit (MSB) and bit number 0 the least significant bit (LSB).

Table 23: Read/Write Registers

Access Tag Name Meaning

r Read This field can be read by the user/sw.

w Write This field can be written by the user/sw.

u Update This field can be updated by hardware.

Table 24: Set and Clear Registers

Access Tag Name Meaning

r Read This field can be read by the user.

s Set This field can be set by the user.

c Clear This field can be cleared by the user.

u Update This field can be updated by hardware.






System Description

Register Interfaces and I/O Configurations

All register interfaces visible to software are 32-bits.

Address Maps

The register accesses are possible from the F2A. Table 25 gives the register maps for the interface of the peripherals.

NOTE: For F2A Packer, for single pixel update in 565 mode one 16-bit write must followed with one 16-bit dummy write from the F2A interface.

Table 25: F2A Address Map

Module 21:0

VEE 0x000000 to 0x00FFFF

SPI 0x010000 to 0x01FFFF

Clock and Reset 0x020000 to 0x02FFFF

Common Registers in Register control block 0x030000 to 0x03FFFF

Reserved 0x040000 to 0x0FFFFF

Cellular RAM 0x100000 to 0x1FFFFF

FB through A2F 0x200000 to 0x20FFFF

Reserved 0x300000 to 0x30FFFF


41



42

Register Maps

VEE Block Registers (Address: 0x000000)

Table 26: VEE Block Register Map

Address Offset

NameReset Value

Description

0x00000 VEE Control Register 0 0x07Turns the VEE processing ON and OFF. Also preserves local contrast in small areas.

0x00004 VEE Internal Debug Register 0x1F Reserved. Always set to 0x1F.

0x0000C Strength Register 0x60 Sets the magnitude of the VEE algorithm.

0x00010 Variance Register 0x22 Influences spatial and intensity filtering behavior.

0x00014 Slope Register 0x20Prevents small dark areas from becoming darker after the VEE processing.

0x0001C Sharpen Control Register 0 0x3AControl image sharpening intensity.

0x00020 Sharpen Control Register 1 0x1A

0x00024Upper Horizontal Position Register

0x00Sets up the back porch interval for the horizontal synchronization input signal.

0x00028Lower Horizontal Position Register

0x00

0x0002CUpper Vertical Position Register

0x00Sets up the back porch interval for the vertical synchronization input signal.

0x00030Lower Vertical Position Register

0x00

0x00034 Upper Frame Width Register 0x00Sets up the maximum boundary for the processed image width.

0x00038 Lower Frame Width Register 0xF0

0x0003C Upper Frame Height Register 0x02 Sets up the maximum boundary for the processed image height.0x00040 Lower Frame Height Register 0x80

0x00044 Control Register 0 0x03 Controls the data space.

0x00048 Control Register 1 0XE5Controls the behavior of the video control synchronization and data validation signals.

0x0004CVideo Enhancement Enable Register

0x0F Controls the video enhancement enable registers.

0x00050 Black Level Register 0x00 Controls the Black Level value.

0x00054 White Level Register 0xFF Controls the White Level value.

0x00060 Amplification Limits Register 0x66Restricts the luminance space in which the VEE processing can adaptively generate tone curves for each pixel

0x00064 Dithering Mode Register 0xX2 Sets the level of dithering.

0x00080 Upper Look-Up Data Register 0x00

Loads the RAM blocks internal to the QuickLogic CSSP with appropriate look-up tables for the VEE algorithm.

0x00084 Lower Look-Up Data Register 0x00

0x00088 Look-Up Address Register 0x00

0x0008CLook-Up Write Enable Register

0x00

0x003FC VEE ID Register 0x22 Contains the VEE version identification.






SPI Block Registers (Address: 0x010000)

0x000C0 m_11 0x40

Transforms overall colors. Color space conversion block.

0x000C4 m_12 0x00

0x000C8 m_13 0x00

0x000CC m _21 0x00

0x000D0 m_22 0x40

0c000D4 m_23 0x00

0x000D8 m_31 0x00

0x000DC m_32 0x00

0x000E0 m_33 0x40

0x000E8 offset_r 0x80

Transforms overall colors. Offset values for R, G and B.0x000EC offset_g 0x80

0x000F0 offset_b 0x80

Table 27: SPI Block Register Map

Register Offset

Register Name Reset Value Description

0x0000 SPI Rx0 Register 0x0000_0000 SPI data receive register 0.



0x000C SPI Rx3 Register 0x0000_0000 SPI data receive register 3.




0x001C SPI Rx7 Register 0x0000_0000 SPI data receive register 7.

0x0020 SPI Tx0 Register 0x0000_0000 SPI data transmit register 0.



0x002C SPI Tx3 Register 0x0000_0000 SPI data transmit register 3.




0x003C SPI Tx7 Register 0x0000_0000 SPI data transmit register 7.

0x0040 SPI Control Register 0x0000_0008SPI control and status register. Also used to select the slave.

0x0044 SPI Transfer Length Register 0x0000_00FF SPI Transfer Length register.

Table 26: VEE Block Register Map (Continued)

Address Offset

NameReset Value

Description


43



44

Clock and Reset Block Registers (Address: 0x020000)

Common Registers (Address: 0x030000)

Table 28: Clock and Reset Block Register Map

Register Offset


0x0000 Global Clock Register 0x0000_01FF Module-based clock enable control register.

0x0004 VLP Control1 Register From Anti-fuse VLP-related control1 register.

0x0008 VLP Control2 Register 0x0000_1E00 VLP-related control2 register.

0x000C Clock Selection Register0x0004_70nn (n – Anti-fuse)

Clock MUX selection and on/off control.

0x0010 PLL Control Register

0x0000_0000 (default value for bit-3 and bit-0 are from Anti-fuse)

PLL Control register used to program bypass mode and monitor lock.

0x0014 PLL Clock Ratio Register From Anti-fuse Multiplication and division factors for SD_Clk (M/N).

Table 29: Common Register Map

Register Offset


0x0000CellRAM Refresh Configuration Register (RCR)

0x0000_0010

Reset value for other CellRAM configuration is specified in Hardware/Software Interactions on page 71.

This is the CellRAM RCR used for configuring Deep Power-Down (DPD) mode and refresh cycles.

0x0004 Image Effect Register 0x0000_0000This is the Image Effect register used by Read address generator and outgoing FIFO block.

0x0008 Row Number Register 0x0000_0000This is the Row Number register updated by the Read address generator and outgoing FIFO block.

0x000CTCON Timing0 Register

From Anti-fuseThis is the Timing 0 register used by the ASSP core extracting X_Width and Y_Width parameters in units of pixels.

0x0010TCON Timing1 Register

From Anti-fuse

This is the Timing 1 register used by the VX2 core extracting Hsync front porch in units of pixel clocks and Vsync front porch in units of number of lines and Hsync back porch in units of pixel clocks and Vsync back porch in units of number of lines.

0x0014TCON Timing2 Register

From Anti-fuse

This is the Timing 2 register used by the TCON block for extracting Hsync pulse width in units of pixel clocks and Vsync pulse width in units of number of lines and for controlling polarity of HSync, Vsync and Data enable.






0x0018 PWM Control Register 0x0000_0000This is the control register used by the PWM block.

0x001C PWM Width Register From Anti-fuseThis is the PWM-related parameters to be used by the PWM block.

0x0020VEE Configuration Register

0x0000_0000/Anti-fuse This is the VEE configuration register.

0x0024CellRAM Bus Configuration Register (BCR)

0x0008_746F

Reset value for other CellRAM configuration is specified in Hardware/Software Interactions on page 71.

This is the CellRAM BCR which defines how the Pseudo SRAM (PSRAM) device interacts with the system memory bus.

0x0028CellRAM Configuration Control Register

0x0000_0000This is the CellRAM Configuration Control register.

0x0100 Use Case Register From Anti-fuseThis is the address for use case-related information register.

0x0104Video Parameter Register

From Anti-fuseThis is the Video Parameter register used for information such as RGB type, RGB data, etc.

0x010C Burst Length Register 0x0000_0000This is the Burst Length register used to indicate the burst length during video through F2A register interface.

0x0110Display Attributes Register

From Anti-fuseThis is the register used to decode information such as Windowless, end of media frame, frame buff storage method.

0x0114 Error Status Register 0x0000_0000This is the Error Status register used to indicate different error conditions.

0x0118 Error Mask Register 0x0000_0000Masks the Error Status register bits. Can be used to selectively enable error indications required.

0x0124Incoming RGB FIFO Overflow Address Register

0x0000_0000Indicates the address at which the Incoming RGB FIFO overflow occurred.

0x0128SPI Overflow Address Register

0x0000_0000Indicates the address at which SPI Tx register overflow happened.

0x012CPing Buffer Address Register

0x0000_0000Buffer-1 start address in Ping pong mode. (This address shall be used in case of single buffer mode.)

0x0130Pong Buffer Address Register

0x0000_0000 Buffer-2 start address in Ping Pong mode.

0x0134Configuration Done Register

0x0000_0000 Used for indicating configuration is done.

0x0138 FIFO Flush Register 0x0000_0000 Used for flushing the FIFOs.

Table 29: Common Register Map (Continued)

Register Offset



45



46

CSSP Registers and Descriptions

VEE Block Registers (Address: 0x000000)

VEE Control Register 0

This register turns the VEE processing ON and OFF. When the VEE is OFF, video data passes to the output without any changes. This register also preserves local contrast in small areas. There are two versions of customer implementation, weak and strong.

Register Offset: 0x00000Reset Value: 0x07

VEE Internal Debug Register

This register is used for internal debugging.

Register Offset: 0x00004Reset Value: 0x1f

VEE Strength Register

The VEE strength register allows the designer to set the magnitude of the VEE algorithm. If the value of the strength register is low, the VEE algorithm does very little image processing.

Register Offset: 0x0000CReset Value: 0x60

NameAccess

TagBit(s) Description

VEE_control_1_0 RW

0Switches the VEE functionality on and off: 1 – ON0 – OFF

2:1

Local contrast strength:0x0 – OFF0x1 or 0x2 – weak local contrast0x3 – strong local contrast

7:3 Reserved

NameAccess


Reserved RW 7:0 Always set to 0x1F.

NameAccess

TagBit Description

strength_reg RW2:0 Unused : “000”

7:3 Strength value






VEE Variance Register

The VEE Variance register influences spatial and intensity filtering behavior. Decreasing of the filtering passes will progressively increase the spatial sensitivity or intensity selectivity of the algorithm. The default value of 0x22 is generally suitable, so the variance can be left as 0x22.


VEE Slope

Slope restriction is a supplementary module preventing small dark areas from becoming darker after the VEE processing. The default value of 0x20 is generally suitable, so the slope can be left as 0x20.


Sharpen Control 0

The Sharpen Control registers control image sharpening intensity. This register (Sharpen Control 0) sets up the first coefficient of the filter and switches ON/OFF the filtering algorithm. The Sharpen Control 1 register sets up the second coefficient of the filter.

Register Offset: 0x0001CReset Value: 0x3A

NameAccess

TagBit Description

variance_reg

RO 0 Reserved (0x0)

RW 2:1 Spatial variance (0x1)

RO 4:3 Reserved (0x0)

RW 6:5 Intensity variance (0x1)

RO 7 Reserved (0x0)

NameAccess


slope_reg RW 7:0 Slope restriction value

NameAccess


sharpen_cntl_reg0 RW

4:0 Filter coef1

5 Sharpening filter on/off

7:6 "00"


47



48

Sharpen Control 1

The Sharpen Control registers control image sharpening intensity. The Sharpen Control 0 register sets up the first coefficient of the filter and switches ON/OFF the filtering algorithm. This register (Sharpen Control 1) sets up the second coefficient of the filter.

Register Offset: 0x00020Reset Value: 0x1A

Horizontal Position Register [11:8] (Upper)

The horizontal position registers set up the back porch interval for the horizontal synchronization input signal in pixel time units (i.e., pixel clock cycles).


Horizontal Position Register [7:0] (Lower)

See Horizontal Position Register [11:8] description.


Vertical Position Register [11:8] (Upper)

The vertical position registers set up the back porch interval for the vertical synchronization input signal in pixel time units (i.e., pixel clock cycles).


NameAccess


sharpen_cntl_reg1 RW4:0 Filter coef2

7:5 "000"

NameAccess


hs_pos_reg[11:8] RW 3:0 HS position upper

NameAccess


hs_pos_reg[7:0] RW 7:0 HS position lower

NameAccess


vs_pos_reg[11:8] RW 3:0 Vertical initial position, upper bits.






Vertical Position Register [7:0] (Lower)

See Vertical Position Register [11:8] description.


Frame Width Register [11:8] (Upper)

The frame width registers set up the maximum bounds for the processed image width. The value of this register depends upon the resolution of the LCD screen being used. For the frame width, find the pixel width of the screen, and divide this number by two. For example, a 640(H) x 480(W) screen has a width of 480 pixels. Divided by two gives the value 240, which is 0xF0 in hex.


Frame Width Register [7:0] (Lower)

See Frame Width Register [11:8] description.

Register Offset: 0x00038Reset Value: 0xF0

Frame Height Register [11:8] (Upper)

The frame height registers set up the maximum bounds for the processed image height. The value of this register depends upon the resolution of the LCD screen being used. For the frame height, use the pixel height of the screen. For example, a 640(H) x 480(W) screen has a height of 640 pixels, which is 0x280 in hex.


NameAccess


vs_pos_reg[7:0] RW 7:0 Vertical initial position, lower bits.

NameAccess


frame_width_reg[11:8] RW 3:0 Frame width, upper bits.

NameAccess


frame_width_reg[7:0] RW 7:0 Frame width, lower bits.

NameAccess


frame_height_reg[11:8] RW 3:0 Frame height, upper bits.


49



50

Frame Height Register [7:0] (Lower)

See Frame Height Register [11:8] description.


Control Register 0

This register controls the data space.


Control Register 1

This register controls the behavior of the video control synchronization and data validation signals. The Horizontal Polarity bit chooses the active edge of the RGB horizontal synchronization input signal. If Horizontal Polarity is equal to a logical one then the rising edge will be used to start measuring the horizontal time interval. If Horizontal Polarity is equal to a logical zero then the falling edge will be used. The Horizontal Phase register selects the phase of the RGB horizontal synchronization signal. This option may be useful when the horizontal sync active edge occurs in interleaved video streams. If this were the case then data and sync signals would not be aligned and a shift between the data and the horizontal sync might occur. To avoid this situation one can correct the condition by altering the value of the Horizontal Phase register. Both the field correction and field generation registers can be left at their default values.

Register Offset: 0x00048Reset Value: 0xE5

NameAccess


frame_height_reg[7:0] RW 7:0 Frame height, lower bits.

NameAccess


control_reg0 RW1:0

Data space:0x2 – YUV0x3 – RGB

7:2 Reserved

NameAccess


control_reg1 RW

0 hs_polarity – 1

1 vs_polarity – 1

2 field_generation – 1

3 hs_phase – 0

5:4 field_correction – 10

6 direct_active – 1

7dvi edge (rising/falling) – 0Bit 7 is for board verification only






Video Enhancement Enable Register

This register controls the video enhancement functional block enables.

Register Offset: 0x0004CReset Value: 0x0F

Black Level Register

The value in this register is represented in 6.2 format. In this format, a number with a fractional part is represented as follows: the upper 6 bits represent the integer part, and the least significant 2 bits represent the fractional part (such that bits “10” equal ½). Video data is considered to have maximum range from 0 to 255.

The value stored in the Black Level Register is used as zero level for the VEE processing in all unsigned data channels. In the case of YUV data, Black Level is used only for the Y channel. In the case of RGB data, the same Black Level is subtracted from all three R, G and B Channels. For example, normal ITU656 video data, according to the standard, should have Black Level = 16. For this type of video, write 40h into the Black Level Register. Data below the Black Level will not be processed and remains unchanged.


White Level Register

The value in this register is represented in 6.2 format. In this format, a number with a fractional part is represented as follows: the upper 6 bits represent the integer part, and the least significant 2 bits represent the fractional part (such that bits “10” equal ½). Video data is considered to have maximum range from 0 to 255.

NameAccess


pwd_reg RW

0VEE1 – enabled0 – disabled

1 Sharpen1 – enabled0 – disabled

2 Color matrix1 – enabled0 – disabled

3 Gamma1 – enabled0 – disabled

7:4 Reserved

NameAccess


black_level_reg RW 7:0 black_level_reg / 4 = Black Level


51



52

The value stored in the White Level Register is used as a White Point for the VEE processing in all unsigned data channels, the Black Level is used as a starting point. In the case of YUV data, the Black Level is used only for the Y channel. In the case of RGB data, the White Level is used for all three R, G and B Channels. For example, normal ITU656 video data, according to the standard, the White Level = 240 and the Black Level = 16. For this type of video, write C3h into the White Level Register. The formula for the White Level register value is:

White and Black level in formula have range 0 – 255.

Register Offset: 0x00054Reset Value: 0xFF

Amplification Limits Register

This register is used to restrict the luminance space in which the VEE processing can adaptively generate tone curves for each pixel.


Dithering Mode Register

This register sets the level of dithering. When the number of color gradations of a display device is small (for example 6 bit per color) a pixel dithering can make gradients look smother. There can be a situation when the VEE output signal is 10 bits but the signal needs to be compressed into 8 bits. The best way for this is to use dithering of the least significant bits and then truncate these bits. The dithering can be performed by the VEE processing. However, the truncation must be done by a hardware designer outside the VEE processing.

Two least significant bits (D1, D0) of this register are responsible for strength of dithering. Higher bits are not used. There are four possible levels of dithering.

Register Offset: 0x00064Reset Value: 0xX2

NameAccess


white_level_reg RW 7:0 255 - ((255 - white_level_reg) / 4) = White Level

NameAccess


ampl_limit_reg RW3:0 Dark limit

7:4 Bright limit

NameAccess


dither_reg RW1:0

Dithering mode:0x0 – No dithering0x1 – One least significant bit of the output signal is dithered0x2 – Two bits are dithered0x3 – Three bits are dithered

7:2 Reserved.






Look-Up Table Data Registers

The Look-Up Table Data Registers are used to load the RAM blocks internal to the QuickLogic CSSP with appropriate look-up tables (LUTs) for the VEE algorithm. For loading the LUT data, there are four registers; two data registers, one address register, and a write enable register.

The sequence to write a single word is:

1. Write the high byte to the high byte register.

2. Write the low byte to the low byte register.

3. Write the address to the address register.

4. Write to the write enable register

The addresses for the table are:

• 0x80 to load the high byte of data

• 0x84 to load the low byte of data

• 0x88 to load the address

• 0x8C to load the write enable

NOTE: The Look-Up Tables are pre-initialized. Do not changes these values without contacting QuickLogic for more information first. Changing these values can lead to improper VEE calibration.

Look-Up Table Data Register [15:8]

The required LUT values are included in the drivers supplied by QuickLogic.

This register contains the upper byte of data to be loaded into the LUTs.


Look-Up Table Data Register [7:0]

This register contains the lower byte of data to be loaded into the LUTs.


NameAccess


lut_data_reg[15:8] WO 7:0 Write only, reads 0x55

NameAccess


lut_data_reg[7:0] WO 7:0 Write only, reads 0x55


53



54

Look-Up Table Address Register

This register contains the local address where data is to be loaded.


Look-Up Table Write Enable Register

This register specifies which LUT is to be loaded.


VEE ID Register

This register contains the VEE version identification.

Register Offset: 0x003FCReset Value: 0x22

NameAccess


lut_addr_reg[7:0] WO 7:0 Write only, reads 0x55

NameAccess


lut_we_reg RW

0 Reserved

1 Asymmetry write enable

2 Sharpening write enable

3 Gamma write enable

7:4 Reserved

NameAccess


VEE_ID_rev RO 7:0 VEE version identification. Read only






Color Matrix Registers

These registers are used to transform overall colors. Color Matrix coefficient registers are in fixed point format 2.6.

Overall color transform can be defined as follows:

where offsets are signed integers with ‘zero point’ = 0x80. For example 0x7F = -1

Register Offset: 0x000C0, 0x000C4, 0x000C8, 0x000CC, 0x000D0, 0x000D4, 0x000D8, 0x000DC, 0x000E0

Reset Value: 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x40

Register Offset: 0x000E8, 0x000EC, 0x000F0Reset Value: 0x80,0x80, 0x80

NameAccess


m_11 RW 7:0

Color space conversion block.

m_12 RW 7:0

m_13 RW 7:0

m_21 RW 7:0

m_22 RW 7:0

m_23 RW 7:0

m_31 RW 7:0

m_32 RW 7:0

m_33 RW 7:0

NameAccess


offset_r RW 7:0

Offset values for R, G and B.offset_g RW 7:0

offset_b RW 7:0

=

333231

232221

131211

mmmmmmmmm

M

+

⋅=

boffsetgoffsetroffset

bgr

Mborvgorurory

___

______


55



56

SPI Block Registers (Address: 0x010000)

SPI Rx0-7 Register

NOTE: The offsets for SPI block registers are relative to the SPI base address.

Register Offset: 0x0000 - 0x001CReset Value: 0x0000_0000

SPI Tx0-7 Register

Register Offset: 0x0020 - 0x003CReset Value: 0x0000_0000

SPI Control Register

Register Offset: 0x0040Reset Value: 0x0000_0008

NameAccess

TagBit Description

rRxDatan (n is 0 to 7)

ru 31:0SPI Rx data register. The software on seeing the Rx done bit indication from hardware will read the data from the Rx data registers based on the transfer length.

NameAccess

TagBit Description

rTxDatan (n is 0 to 7)

rw 31:0SPI Tx data register. The software programs the data to be transmitted on the SPI interface to the Tx data register based on the transfer length.

NameAccess

TagBit Description

rSPIStart rw 0Software triggers the hardware to start the SPI transactions by setting this bit.

rCPHA rw 1Selects the Clock phase:0 – Clock phase 0 is enabled1 – Clock phase 1 is enabled

rCPOL rw 2Selects the Clock polarity:0 – Clock polarity 0 is enabled1 – Clock polarity 1 is enabled

rLSB rw 3Indicates endianness:0 – MSB1 - LSB

rSLVSEL rw 5:4

Selects one among the three slaves supported:00 – Slave 0 is selected01 – Slave 1 is selected10 – Slave 2 is selected11 – Reserved

Reserved r 7:6 Reserved






SPI Transfer Length Register

Register Offset: 0x0044Reset Value: 0x0000_00FF

Clock and Reset Block Registers (Address: 0x020000)

Global Clock Register

NOTE: All clock and reset block registers offset is relative to the Clock and Reset module base address.

Register Offset: 0x0000Reset Value: 0x0000_01ff

rTranIn Prg ru 8Updated by hardware. When set, indicates transaction is in progress.

rTxDone ru 9 If set, indicates current transfer is completed.


NameAccess

TagBit Description

rTransferLength rw 7:0

Indicates the transfer length in number of bits. ‘h00 – length = 1‘h01 – length = 2‘h02 – length = 3….‘hff – length = 256


NameAccess

TagBit Description

rGlobal_clock_enable rw 0 Global clock enable. If set, the clocks are enabled.

rVEE_enable rw 1 Clock enable for the VEE block. If set, clock is enabled.

rCellRAM_enable rw 2 Clock enable for the CellRAM block. If set, clock is enabled.

rTCON_enable rw 3 Clock enable for the TCON block. If set, clock is enabled.

rPWM_enable rw 4 Clock enable for the PWM block. If set, clock is enabled.

rSPI_enable rw 5 Clock enable for the SPI block. If set, clock is enabled.

Reserved rw 6 Reserved, must be set to ‘0’.

rIncomingFIFO_enable rw 7Clock enable for the Incoming FIFO block. If set, clock is enabled.

rOutgoingFIFO_enable rw 8Clock enable for the Outgoing FIFO block. If set, clock is enabled.

NameAccess

TagBit Description


57



58

VLP Control Set1/2 Register

Register Offset: 0x0004 (Set 1) and 0x0008 (Set 2)Reset Value: From Anti-fuse (Set 1) and 0x0000_1E00 (Set 2)

rVLP_Ctrl_Sel rw 9Selects the VLP control set register:0 – Ctrl Set2 is selected1 – Ctrl Set1 is selected

rDataOutPD rw 10 Power down signal for PHY.


NameAccess

TagBit Description

rFB_VLP_Ctrl rw 1:0




11 – Reserved

rGPIO_VLP_CTRL rw 2Used in conjunction with rFB_VLP_CTRL. To be gated and passed only if FB_VLP_Ctrl is 01 or 10.

rTCON_enable rw 3VLP mode enable for the TCON block. If set VLP mode is disabled.

rPWM_enable rw 4VLP mode enable for the PWM block. If set VLP mode is disabled.

rSPI_enable rw 5VLP mode enable for the SPI block. If set, VLP mode is disabled.

Reserved rw 6 Must always be set to ‘0’.

rIncomingFIFO_enable rw 7VLP mode enable for the Incoming FIFO block. If set, VLP mode is disabled.

rOutgoingFIFO_enable rw 8VLP mode enable for the Outgoing FIFO block. If set, VLP mode is disabled.

rPixelClk_OpOff rw 9 If set, switches off the Pixel clock.

rSdClk_OpOff rw 10 If set, switches off the SD clock.

rPll_PowerDown rw 11 If set, powers down the PLL.

Reserved rw 13:12 Must always be set to ‘1’.

Reserved r 31:14 Reserved.

NameAccess

TagBit Description






Clock Selection Register

Register Offset: 0x000CReset Value: 0x0004_70nn (n – Anti-fuse)

NameAccess

TagBit Description

Reserved r 0 Reserved.

rSdClkSel r 2:1

Indicates the division factor for sd_clk_by2/4/8:00 – /201 – /410 – /811 – Reserved

rSPIClkSel r 3Indicates the division factor for SPI clock: 0 – /41 – /8

rPWMClkSel r 7:4

Indicates the division factor for the PWM clock:0000 – /10001 – /20010 – /4 …………1010 – /10241011-1111 – Reserved

rInFIFOMuxGate rw 8If set, switches off the inFIFO clocks. This is used for changing the inFIFO MUX selection.

rSDClkEnaSW rw 9Enables sd_clk. To be used for CellRAM DPD for use_case=00.

rPllPixelClkStop rw 10 If set, stops pll_pixel_clk.

rPixelClkMuxGate rw 11If set, switches off the pixel_clk. This is used for changing the pixel_clk selection.

rSdClk_by248En rw 12 If set, the clock sd_clk_by_248 to Fabric is switched on.

rPixClkoutEn rw 13 If set, the clock pixel_clk_out to Fabric is switched on.

rClkinFbEn rw 14 If set, the PLL bypass clock to Fabric is switched on.

rPllSdClkStop rw 15 If set, stops pll_sd_clk.

ext_pix_clk_pll_sel rw 16 If set, selects external pixel clock instead of pll_pixel_clk.

invert_pixel_clk_out rw 17 If set, inverts the pixel_clk_out.

Reserved rw 18 Reserved, must be set to ‘0.



59



60

PLL Control Register

Register Offset: 0x0010Reset Value: 0x0000_0000 (Default value for bit-3 and bit-0 are from Anti-fuse)

PLL CLK Ratio Register

Register Offset: 0x0014Reset Value: From Anti fuse

NameAccess

TagBit Description

rPLLBypass rw 0 If set, enables the PLL Bypass path from SYS_CLK to Clk_in_FB.

rPixelBypass rw 1 If set, the Pixel clock output is bypassed with PLL input clock.

rSdBypass rw 2 If set, the SD clock output is bypassed with PLL input clock.

rIn_RNG_Sel rw 3

If set, the PLL enables an internal fixed multiply-by-128 to multiply up the input clock. This is used for applications that can only provide low input frequency clock. When set to '1', the overall PLL multiplier is M (as set by rVCOM) * 128.

Input clock range:'0' = 8 to 20 MHz'1' = 31 to 33 kHz

rPixelOpOff rw 4 If set, the pixel clock output is disabled.

rSdOpOff rw 5 If set, the SD clock output is disabled.

rPllPd rw 6 If set, the PLL powers down.

rPllLock r 7 Indicates the status of PLL lock. If set, indicates that PLL is locked.


NameAccess

TagBit Description

rVCOM rw 6:0VCO multiplication factor (see Table 2).

Note: The rVCOM VCO operating range is 400 MHz to 550 MHz.

rSdClkDiv rw 13:7 SD clock division factor (see Table 3).

rPixelClkDiv rw 20:14 Pixel clock Division factor (see Table 3).







Common Registers (Address 0x030000)

CellRAM Refresh Configuration Register


NOTE: Valid only when use case is with frame buffer.

Image Effect Register


NameAccess

TagBit Description

rRCRPAR rw 2:0Refresh Configuration Register Partial-Array Refresh (PAR) Field. Set to 000. Contact QuickLogic for possible combinations.

Reserved rw 3 Reserved

rDPD rw 4

Deep Power-Down. Enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the PSRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-enabled, the PSRAM device will require 150 µs to perform an initialization procedure before normal operations can resume.

Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD is maintained until RCR[4] is reconfigured. DPD can be enabled using CRE or the software sequence to access the RCR. BCR and RCR values (other than BCR[4]) are preserved during DPD.

Reserved rw 18:5 Reserved

rRCRSEL rw 19 Refresh Configuration Register Select. Always set this bit to ‘0’.


rRcrWriteEnable rwu 31The Refresh Configuration Register write valid is generated only when the bit is written with ‘1’. It is cleared after the write valid is generated by hardware.

NameAccess

TagBit Description

rImgEffect rw 1:0

Decodes the image effect to be used by read address generator block.00 – Normal01 – Horizontal flip10 – Vertical flip11 – Rotation



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Row Number Register


TCON Timing0 Register

Register Offset: 0x000CReset Value: From Anti-fuse


Register Offset: 0x0010Reset Value: From Anti-fuse

NameAccess

TagBit Description

rRowNumber ru 9:0This is the row number updated by the read address generator indicating the row that is being read by the read address generator.

rBufferInd ru 10 This indicates if the row number belongs to ping or pong buffer.


NameAccess

TagBit Description

rXWidth rw 9:0The number of pixels per line is (X_width + 1).(From Anti-fuse)


rYWidth rw 25:16The number of active lines per frame is (Y_Width + 1).(From Anti-fuse)


NameAccess

TagBit Description

rVS_FR_PORCH rw 4:0Vsync front porch in units of number of lines.Vsync front porch = (VS_FR_PORCH +1)(From Anti-fuse)

rHS_FR_PORCH rw 11:5Hsync front porch in units of pixel clocks. Hsync front porch = (HS_FR_PORCH +1)(From Anti-fuse)


rVS_BK_PORCH rw 20:16VSync back porch in units of number of lines.Vsync back porch = (VS_BK_PORCH +1)(From Anti-fuse)

rHS_BK_PORCH rw 27:21Hsync back porch in units of pixel clocks.Hsync back porch = (HS_BK_PORCH +1)(From Anti-fuse)









PWM Control Register


PWM Width Register

Register Offset: 0x001C Reset Value: From Anti-fuse

NameAccess

TagBit Description

rVSyncWidth rw 4:0VSYCNC pulse width in units of number of lines.VSYNC pulse width = (VSyncWidth +1)(From Anti-fuse)

rHSyncWidth rw 11:5HSYNC pulse width in units of pixel clocks.HSYNC pulse width = (HSyncWidth +1)(From Anti-fuse)


NameAccess

TagBit Description

rPWMEn rw 0 Enables the PWM block.


Name Access Tag Bit Description

rPWMWidth rw 15:0This is the 16-bit value to be used by the PWM module to calculate the pulse width (duty cycle).(From Anti-fuse)



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VEE Configuration Register

Register Offset: 0x0020 Reset Value: 0x0000_1FC0/Anti-Fuse

NOTE: The bits [1:0] and bits [5:3] have Anti-fuse values during reset.

CellRAM Bus Configuration Register

Register Offset: 0x0024Reset Value: 0x0008_746F

NOTE: Valid only when use case is with frame buffer.

NameAccess

TagBit Description

rVEEBypassMode rw 1:0

Decodes the VEE bypass mode.10 – RGB-in to RGB-out with the VEE bypass01 – Video from outgoing FIFO block with the VEE bypass00 – VEE data output11 – Reserved(From Anti-fuse)

Reserved r 2 Reserved

rINVDE rw 3

Controls polarity of RGB data enable.0 – Normal DE1 – Invert DE(From Anti-fuse)

rINVSync rw 4

Controls polarity of VSync.0 – Normal VSync1 – Invert VSync polarity(From Anti-fuse)

rINVHSync rw 5

Controls polarity of HSync.0 – Normal HSync1 – Invert HSync polarity(From Anti-fuse)

rVEE_Ena_Mask rw 12:6 Used for debugging purposes.


NameAccess

TagBit Description

rBurstLen rw 2:0

Burst lengths define the number of words the device outputs during burst READ operations.

Default = Continuous Burst

rBurst_Wrp rw 3

The burst-wrap option determines whether a 4-, 8-, or 16-word READ burst wraps within the burst length or whether it steps through sequential addresses.

Default = No Wrap







rOutImp rw 5

The output driver strength can be altered to be between full and one-quarter strength to adjust for different data bus loading scenarios.

Default = Outputs Use Full-Drive Strength


rWAITConf rw 8

The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus.

Default = WAIT Transitions One Clock Before Data Valid/Invalid


rWAITPol rw 10

The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW.

Default = WAIT Active HIGH

tLatCount rw 13:11

The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred.

Default = Three Clock Latency

rInitAccLat rw 14

Variable initial access latency outputs data after the number of clocks set by the latency counter.

Default = Variable

rOperMode rw 15

The operating mode bit either selects synchronous BURST operation or the default asynchronous mode of operation. The operating mode bit selects synchronous BURST operation or the default asynchronous mode of operation.

Default = Asynchronous Operation


rBCRSEL rw 19 Bus Configuration Register Select. Always set this bit to '1'.


rBcrWriteEnable rwu 31The Bus Configuration Register write valid is generated only when the bit is written with ‘1’. It is cleared by hardware after the write valid is generated.

NameAccess

TagBit Description


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CellRAM Configuration Control Register


NOTE: Valid only when use case is with frame buffer..

Use Case Register

Register Offset: 0x0100Reset Value: 0x0000_0000/Anti-fuse

NOTE: The bits [2:0] and bit [5] has Anti-fuse values during reset.

NameAccess

TagBit Description

rBurstNum rw 2:0Indicates the number of continuous bursts to be performed by the CellRAM Controller based on clock frequency.


rAsynSynDly rw 8:5Number of clock cycles required for the CellRAM to switch from Asynchronous to Synchronous mode. Set this register to 0x8. Contact QuickLogic for more details.


rCtrlWriteEnable rwu 31The Control write valid is generated only when the bit is written with ‘1’. It is cleared by hardware after the write valid is generated.

NameAccess

TagBit Description

rCellRamWidth r 0

Decodes CellRAM width:00 – 16-bits01 – 32-bits(From Anti-fuse)

rUSeCase rw 2:1

00 – RGB-In to RGB-Out w/o frame buffer01 – RGB-In to RGB-Out with frame buffer10 – Reserved11 – Video through F2A control interface(From Anti-fuse)


rCellRAMSize r 5Decodes CellRAM size:Should read 1(From Anti-fuse)

rInvVsyncPolarity rw 6Indicates the Polarity for Vsync:0 – Active high1 – Active low






Video Parameter Register


Burst Length Register

Register Offset: 0x010CReset Value: 0x0000_0000

rInvHsyncPolarity rw 7Indicates the Polarity for Hsync:0 – Active high1 – Active low

rInvDEPolarity rw 8Indicates the Polarity for Data enable:0 – Active high1 – Active low


NameAccess

TagBit Description

rRGBType rw 11:0

Decodes the type of RGB format.Number of bits for R component [11:8]Number of bits for G component [7:4]Number of bits for B component [3:0](From Anti-fuse)To be used by RGB and Video through register paths.


NameAccess

TagBit Description

rBurstLength rw 15:0Determines the burst length. This field is valid only for F2A video though register use case.

rF2aPackerEn rw 16Determines whether data is packed or unpacked. If ‘0’ packing is enabled, else it is unpacked. This field is valid only for F2A video through register use cases.


NameAccess

TagBit Description


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Display Attributes Register


Error Status Register

Register Offset: 0x0114 Reset Value: 0x0000_0000

NOTE: For the error output to Fabric to be generated, set the Error Status bit and the corresponding Error Mask register bit to ‘1’.

NameAccess

TagBit Description

rBuffStorage rw 1:0

Decodes type of buffer.00 – Single buffer01 – Ping pong buffer10 – Not supported11 – ReservedFor all use cases(Anti-fuse)

rEndOfFrame rwu 2Indicates if last row of F2A is full frame. It is cleared by hardware on ‘1’. This field is not valid for RGB related use cases.


NameAccess

TagBit Description

Reserved ru 8:0 Reserved.

rIncomingFIFOOverwrite

rcu 9Indicates overwrite in the Incoming RGB FIFO. A write of 1’b1 by software will clear this bit. Software must clear this bit only after reading the address at which the overwrite has occurred.

rSpiTxOverwrite rcu 10Indicates overwrite in the SPI Master Tx register. A write of 1’b1 by software will clear this bit. Software must clear this bit only after reading the address at which the overwrite has occurred.

rCellRamWait rcu 11Indicates wait interrupt condition from CellRAM. A write of 1’b1 by software will clear this bit. Valid with Frame Buffer only.

rPllLockInt rcu 12Indicates PLL Lock interrupt condition. A write of 1’b1 by software will clear this bit. Valid with PLL only.

rSpiTxDone rcu 13Indicates SPI Tx done. A write of 1’b1 by software will clear this bit.


rIntFb1 rcu 16Interrupt 1 from fabric. A write of 1’b1 by software will clear this bit.







Error Mask Register


Incoming RGB FIFO Overflow Address Register





NameAccess

TagBit Description

rCrcError rw 0Masks Cyclic Redundancy Check (CRC) error. If set error is masked.

rSkewCalibFailed rw 1 Masks skew calibration failed error. If set error is masked.

rSkewCalibData1AdjErr rw 2Masks skew calibration data adjust error. If set error is masked.

rSkewCalibDone rw 3Masks skew calibration done indication. If set error is masked.

Reserved r 8:4 Reserved. Should be set to ‘1’.

rIncomingFIFOOverwrite rw 9Masks overwrite in the Incoming RGB FIFO. If set overwrite is masked.

rSpiTxOverwrite rw 10Masks overwrite in the SPI Tx register. If set overwrite is masked.

rCellRamWait rcu 11Masks wait interrupt condition from CellRAM If set bit is masked.

rPllLockInt rcu 12 Masks PLL Lock interrupt condition. If set bit is masked.

rSpiTxDone rcu 13 Masks SPI Tx done. If set bit is masked.


rIntFb1 rcu 16 Interrupt 1 mask.





NameAccess

TagBit Description

rIncomingFIFOAddr ru 31:0Indicates the address at which the Incoming RGB FIFO overflow occurred.

NameAccess

TagBit Description


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SPI Overflow Address Register


Incoming RGB FIFO Ping Buffer Address Register

Register Offset: 0x012C Reset Value: 0x0000_0000

Incoming RGB FIFO Pong Buffer Address Register


Configuration Done Register


NameAccess

TagBit Description

rSpiOvAddr ru 31:0Indicates the address at which SPI Tx register overflow happened.

NameAccess

TagBit Description

rIncomingPingBuffAddr

ru 31:0Buffer-1 start address in Ping pong mode.(This address is used in case of single buffer mode.)

NameAccess

TagBit Description

rIncomingPingBuffAddr

ru 31:0 Buffer-2 start address in Ping Pong mode.

NameAccess

TagBit Description

rConfigDone rw 0

This bit is set by software only when the configuration of following registers is completed:- Use Case register- Video Parameter register- Display Attributes register- Xwidth and Ywidth registersSoftware ensures that before any of the above registers are programmed the configuration done bit is cleared by software.







FIFO Flush Register


Hardware/Software InteractionsThe following assumptions and sequencing flow are defined in the hardware design in relation to hardware/software interactions.

1. CellRAM Memory Interface Controller BCR - RCR configuration:

a. The initial CellRAM mode is asynchronous.

b. Configure the BCR before the RCR . This is an asynchronous CellRAM configuration to bring CellRAM in to synchronous mode.

c. Any synchronous request (read/write or RCR configuration) to CellRAM before initial BCR configuration will be blocked. This is to avoid unwanted logic switching inside MIC.

d. Asynchronous BCR configuration to CellRAM will take 16 (min.) clock cycles or 146.72 ns (min.).

e. Synchronous BCR/RCR configuration to CellRAM will take 10 clock (min.) cycles or 91.7 ns (min.), if the latency code is 6 (7 clocks) in idle condition (i.e., no read/write transaction is in progress).

f. Design supported BCR values:

16 Mb CellRAM: 20'h 8646F (latency code – 4) – for Sd_clk up to 66 MHz20'h 86C6F (latency code – 5) – for Sd_clk up to 75 MHz20'h 8746F (latency code – 6) default

g. Reserved bits not set to zero or unsupported values in the configuration register fields will affect device functionality.

h. All configuration writes (BCR/RCR) after the initial asynchronous BCR write will be synchronous writes to CellRAM.

2. For CellRAM DPD mode (entry and exit), software must use the following sequence:

a. To trigger DPD entry, program the DPD mode bit in the CellRAM Controller RCR.

b. Hardware will drive the CE pin high for 10 µs and a control signal to clock reset module for gating the CellRAM clock in DPD mode.

c. No requests to be triggered by the host for 17 µs period.tDPD (10 µs) + max. time for one burst at 20 MHz (7 µs) = 17 µs.The 7 µs delay is to take care of a current transaction going on when the DPD entry is programmed.

NameAccess

TagBit Description

rRagFifoFlush rw 0This bit indicates the flush input for flushing the incoming pixel FIFO.

rInFifoFlush rw 1 This bit indicates the flush input for flushing the IN FIFO.



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d. To trigger the DPD exit, the software will ungate the MIC clock and program the DPD exit bit in the CellRAM Controller RCR.

e. Hardware will drive the CE pin high for 10 µs (tDPDX) and a control signal to clock reset module for ungating the CellRAM clock.

f. No requests to be triggered by the host for a period of 160 µs (10 µs + 150 µs).

g. The 10 µs (min.) counter (1100 clock cycles at 109 MHz) for DPD entry and exit is implemented in hardware.

Figure 21: DPD Timing Diagram for Cell RAM

For DPD entry while in use case = RGBin-RGBout, set the bit rSDClkEnaSW in the clock selection register. This will enable the sd_clk to CellRAM Controller.

3. Software will program the number of bursts to be done by the hardware to the CellRAM based on the clock frequency. This is to take into account the CE# timings required by the CellRAM during continuous burst across the CellRAM clock frequency range of 20 MHz and 109 MHz.

The CellRAM memory has a pulse width requirement on the CE# during continuous bursts. The CE# can remain low for a maximum period of 8 µs continuously.

If we consider SD_clk (CellRAM clock) to be 109 MHz then:Sd_clk period = 9.17 nsTotal burst period is (128 + 7) clock cycles = 135 * 9.17 ns = 1.23 µsTotal bursts during period of 8 µs = 8/1.23 = 6.5So 6 bursts are possible keeping in mind the CE# requirements.

Similarly for SD_clk 20 MHz:Total burst period is (128 + 7) clock cycles = 6.7 µsSo only 1 burst is possible keeping in mind the CE# requirements.

Similarly for all other frequencies in the range of 20 MHz to 109 MHz the number of bursts will vary. To avoid this logic in hardware we are assuming that software knows the SD_clock frequency.

Table 30: DPD Timing Parameters

Parameter Symbol Min. Max. Units

Initialization period (required before normal operation)

tPU - 150 µs

Time from DPD entry to DPD exit tDPD 10 - µs

CE# LOW time to exit DPD tDPDX 10 - µs






This assumption is based on the fact that software knows the crystal clock frequency based on which it programs the PLL M and N values.

This way the software knows the value of SD_clk. Accordingly, does the above calculations and programs a register with the number of bursts that can be done.

A value of 0 is invalid for this field.

4. For the configuration registers, the software has to use the configuration done register. The configuration registers are:

– Use Case register

– Video Parameter register (used only for RGB-In to RGB-out path and F2A control interface)

– TCON registers

The sequence is defined as follows:

a. On reset this bit will be 1’b0.

b. Software will check if the configuration done bit is 1’b0 and only then program the new values.

c. The software will then set the configuration done bit.

d. The hardware can then use the configured values.

e. If software wants to change the configuration, it has to clear this bit and then change the configuration. After changing the configuration it will set the bit again.

f. Hardware will then use the new configured values.

5. Flush sequencing is as follows:

Flush and configuration change:

a. Software sets the flush bit.

b. Software clears the config done bit if configuration changes required.

c. Software gates the InFIFO clock. (Refer #9 in this section for more details about clock gating.)

d. Software changes the use case.

e. Software changes the configuration parameters.

f. Software ungates the InFIFO clock. (Refer #9 in this section for more details about clock ungating.)

g. Software sets the config done bit.

h. Software clears the flush bit.

Only Flush (No configuration change):

a. Software sets the flush bit

b. Inserts a delay of 15 host clock cycles to ensure all modules are synchronized to the flush register bit.

c. Software clears the flush bit.

No clearing of flush bit from hardware is supported. This is because multiple blocks use this flush bit in different clock domains. This is to ensure all modules working in different clock domains have seen the flush bit.


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A flush needs to be performed under the following conditions:

a. When a use case change occurs.

b. When an overwrite error interrupt occurs.

c. When a switch in the Vsync or HSync or DEN polarity happens in RGB with frame buffer use case.

d. When a switch in the buffer-storage mode happens; from ping-pong to single or vice-versa.

6. Restrictions/assumptions in the video through register path:

a. For 16-bit CellRAM burst-length is always even.

b. For 16-bit CellRAM start address always needs to be 32-bit aligned.

c. No logic in hardware to take care of byte enables. Host should provide byte-enables.

For example, if the F2A host wants to update only one pixel of RGB type 565, it must to program the burst length as 1 and initiate two writes to make sure the 32- bit write is complete. The burst length is in terms of 32-bit words. The byte enables should be set accordingly as shown in Table 31.

7. Clock control during use case change. To change the use case dynamically:

a. Set the bits rInFIFOMuxGate and rPixelClkMuxGate in the clock selection register.

b. Wait for a time period of 1 µs (recommended).

c. Change use case register value.

d. Clear the bits rInFIFOMuxGate and rPixelClkMuxGate in the clock selection register.

8. Clock control during PLL reconfiguration. To reconfigure the PLL:

a. Set the bits rPllSdClkStop and rPllPixelClkStop to stop the PLL clocks.


c. Change the PLL configuration values.

d. Wait for PLL to lock (poll for pll lock in the pll control register or enabling the pll lock interrupt).

e. Clear the bits rPllSdClkStop and rPllPixelClkStop to enable the PLL clocks.

9. The VEE bypass mode switching. To switch the VEE bypass mode:

a. Set the bit rPixelClkMuxGate in the clock selection register

b. Wait for a time period of 1 us (recommended)

c. Change the VEE bypass mode

d. Clear the bit rPixelClkMuxGate in the clock selection register.

Table 31: F2A Host Access Byte Enables

31:24 23:16 15:8 7:0

1 1 1 1

0 1 1 1

0 0 0 1

0 0 1 1






10. Clock selection between external pixel clock and PLL pixel clock. To select the pixel clock:

a. Set the bit rPixelClkMuxGate in the clock selection register.


c. Change the bit ext_pix_clk_pll_sel to select the pixel clock.


11. Pixel clock inversion. To change the output pixel clock polarity:

a. Set the bit rPixelClkMuxGate in the clock selection register.


c. Change the bit invert_pixel_clk_out in the clock selection register.



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Pin DescriptionsTable 32 describes the ArcticLink II VX2 solution platform pins.

Table 32: Pin Descriptions

Pin Direction Function Description

Dedicated Pin Descriptions

GPIO(E:A) I/O CSSP dependent CSSP dependent proven system block I/O.

CLK(E:B) IGlobal clock network pin low skew global clock

This pin provides Access to a distributed network capable of driving the CLOCK, SET, RESET, all inputs to the logic cell, Read and Write clocks, Read and Write enables of the embedded RAM blocks, and I/O inputs. Additionally, the clock networks can be Accessed from internal routing. Meaning, clock signals do not necessarily need to come into the device from a clock pin. The letter inside the parenthesis means that CLK(x) is powered through VCCIO(x) of the same letter.

SYS_CLK I System ClockSystem clock to PLL input. Recommended frequency is 32 kHz or 8 MHz to 20 MHz.

SYS_RST_n I Active low system reset

Resets the hard logic in the platform. This pin is also driven through VEE to other functional blocks. This pin is powered through VCCIO(D), and therefore must be pulled to the same voltage level as VCCIO(D) when it is high.

VDD_PLL IDigital core power for PLL block

Digital power to the Hard Logic PLL (not the CCM PLL). This Hard Logic PLL is used to provide the frame buffer clock and LCD Controller logic clock. This is a 1.8V signal.

VSS_PLL I Digital ground for PLL blockDigital ground to the Hard Logic PLL (not the CCM PLL). This signal must be connected to ground.

VDDA_PLL IAnalog core power for PLL block

Analog power to the Hard Logic PLL (not the CCM PLL). This Hard Logic PLL is used to provide the frame buffer clock and LCD Controller logic clock. This is a 1.8V signal.

VSSA_PLL I Analog ground for PLL blockAnalog ground to the Hard Logic PLL (not the CCM PLL). This signal must be connected to ground.

VLP I Very low power mode enableActive low. Therefore, when VLP is 0 V, the device will go into low power mode. Tie VLP to 1.8V or VCCIO(C) to disable low power mode.

VPUMP I Charge Pump Disable

VPUMP = 0 V or 3.3 V.

If VPUMP = 0 V, it will have up to an additional 100 µA of static ICC.

VCC I Power supply pinConnect to 1.8 V or 1.5 V supply. When VCC is 1.5 V, timing will be about 35% slower.

VCC_CELLRAM IDigital power supply to internal frame buffer memory

This signal must be connected to 1.8 V.






VCCQ IPower pin for CellularRAM Frame Buffer Controller

This signal must be connected to 1.8V.

VCCIO(E:A) I Input voltage tolerance pin

This pin provides the flexibility to interface the device with either a 3.3 V, 2.5 V, or 1.8 V device. The letter inside the parenthesis means that the VCCIO is located in the bank with that letter. Every I/O pin in the same bank will be tolerant of the same VCCIO input signals and will drive VCCIO level output signals. Even if certain VCCIO banks are not used, all VCCIO pins must be driven when the device is powered up.

GND I Ground pin Connect to ground.

DIF_H:A_N(A) I– input pins for comparators A through H

These inputs are dual function. They can be GPIO (see GPIO description), or input to analog comparators. The configuration is specified in the design file created by QuickLogic System Solution Group.

DIF_H:A_P(A) I+ input pins for comparators A through H

These inputs are dual function. They can be GPIO (see GPIO description), or input to analog comparators. The configuration is specified in the design file created by QuickLogic System Solution Group

NC N/A No connect Leave these signals as floating.

JTAG Pin Descriptions

TDI I Test data in for JTAGThe I/O standard for this pin is specified by VCCIO(C). Connect to GND if unused.

TRSTB I Active low reset for JTAGThe I/O standard for this pin is specified by VCCIO(C). Connect to GND if unused.

TMS I Test mode select for JTAG The I/O standard for this pin is specified by VCCIO(C). Connect to GND if unused.

TCK I Test clock for JTAG The I/O standard for this pin is specified by VCCIO(C). Connect to GND if unused.

TDO O Test data out for JTAGThe output level drive is specified by VCCIO(C). Must be left unconnected if not used for JTAG.

Table 32: Pin Descriptions (Continued)

Pin Direction Function Description


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Recommended Unused Pin Terminations for ArcticLink II VX2 Solution Platform

All unused, general purpose I/O pins can be tied to VCCIO, GND, or Hi-Z (high impedance) internally. By default, QuickLogic QuickWorks software ties unused I/Os to GND.

Terminate the rest of the pins at the board level as recommended in Table 33.

Table 33: Recommended Unused Pin Terminations

Signal Name Recommended Termination

CLK <x>a

a. x represents B, C, D, or E.

Connect to GND or VCCIO(x) if unused.

VLP Tie VLP to 1.8V or VCCIO(C) to disable low power mode.

TDI Connect to GND if not used for JTAG.

TRSTB Connect to GND if not used for JTAG.

TMS Connect to GND if not used for JTAG.

TCK Connect to GND if not used for JTAG.

TDO Must be left unconnected if not used for JTAG.






Packaging Pinout Diagrams

121 TFBGA Pinout Diagram

Top

Bottom


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Package Mechanical Drawings

121-Ball TFBGA Packaging Drawing with Frame Buffer






121-Ball TFBGA Packaging Drawing without Frame Buffer


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Ordering InformationThe ArcticLink II VX2 solution platform CSSPs have assigned part numbers, contact your local sales representative for your specific CSSP number.

Contact Information

Phone: (408) 990-4000 (US)

(647) 367-1014 (Canada)

+(44) 1932-21-3160 (Europe)

+(886) 2-2345-5600 (Taiwan)

+(86) 21-5116-0532 (China)

E-mail: [email protected]

Sales: [email protected]

[email protected]

[email protected]

[email protected]

Support: www.quicklogic.com/support

Internet: www.quicklogic.com

Revision History

Notice of Disclaimer

QuickLogic is providing this design, product or intellectual property "as is." By providing the design, product or intellectual property as one possible implementation of your desired system-level feature, application, or standard, QuickLogic makes no representation that this implementation is free from any claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. You are responsible for obtaining any rights you may require for your system implementation. QuickLogic shall not be liable for any damages arising out of or in connection with the use of the design, product or intellectual property including liability for lost profit, business interruption, or any other damages whatsoever. QuickLogic products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use QuickLogic products in these types of equipment or applications.

QuickLogic does not assume any liability for errors which may appear in this document. However, QuickLogic attempts to notify customers of such errors. QuickLogic retains the right to make changes to either the documentation, specification, or product without notice. Verify with QuickLogic that you have the latest specifications before finalizing a product design.

Revision Date Originator and Comments1.0 January 2013 Production Release





mailto:[email protected]





http://www.quicklogic.com/support

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Copyright and Trademark Information

Copyright © 2013 QuickLogic Corporation. All Rights Reserved.

The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited.

QuickLogic, ArcticLink and ViaLink are registered trademarks, and the QuickLogic logo is a trademark of QuickLogic.

iridix® is a registered trademark of Apical Ltd.

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