architecture of 8085

8085 MICRO PROCESSOR

Constructing an ALU

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New 32-bit ALU

Set

a31

0

ALU0 Result0

CarryIn

a0

Result1

a1

0

Result2

a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Binvert

CarryIn

Less

CarryIn

CarryOut

ALU1

Less

CarryIn

CarryOut

ALU2

Less

CarryIn

CarryOut

ALU31

Less

CarryIn

Figure 4.18

• Less input is 0 for all but the LS.

• Result of addition in the MS ALU is fed back to the Less input of the LS ALU

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Put it in a box and give it a name

ALU Result

Zero

Overflow

a

b

ALU operation

CarryOut

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Micro-Computer Block Diagram

Basic Processor Operation

All instructions (program steps) are stored in memory.

To run a program, the individual instructions must

be read from the memory in sequence, and executed.

Detailed sequence:

Instruction fetch (read from memory)

Decode instruction

Get operands

Execute operation

Save result

get

next

instruction

Architecture:

• Architecture is the logic design of the

microprocessor.

• The architecture determines the process of data

manipulation and communication.

• The CPU and microprocessor (MPU) are

synonymous

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8085 Functional Block Diagram

P

I

N

O

U

T

The 8085 Microprocessor

address

(8 bits)


address

and data

(8 bits)

dual - use

pins !!

The 8085 MP Clock Generator


De-multiplexing the

address / data bus

8

16

• RD’, WR’ & IO/ M’ – generate MEMR’, IOR’, MEMW’ and

IOW ‘signals.

• The below arrangement generates these signals.

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Generating Control Signal:

CPU operations:

• Memory Read: Read contents (instructions

& data) from memory

• Memory Write: Write contents (data) into

memory

• I/O Read: Accepts data from input devices

• I/O Write: Sends data to output devices

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CPU-to-peripheral communication:

This is done through the address bus, data bus

and control bus.

• Identify peripheral or memory location

(with its address) [Address Bus]

• Provide synchronization signals (Control

Bus)

• Transfer data (Data Bus)

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8085 bus structure:

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8085 System Bus:

• The address bus is Unidirectional and

has 16 lines.

• The data bus is Bidirectional

and has 8 lines.

• The control bus is Bidirectional

and only one line is active at a time.

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Address Bus:

• A0 - A15 ( 16 lines).

• Each peripheral or memory location is

identified by a binary number called an

address , and the address bus is used to

carry a 16-bit address.

• The 8085 can address 216= 65,536 (64K)

memory locations

• 1K = 1,024 .

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Facts:

• Most 8-bit microprocessors have 16 address lines.

• 8-bit microprocessors may have 64Kmemory; however, not every MP system has 64 K memory.

• Most single-board MC have memory less than the actual capacity.

• The number of address lines is arbitrary and depends on the design of the MP.

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Data bus:

• D0 - D7 ( 8 lines). It is Bidirectional

(unidirectional/bidirectional).

• Data bus determines the word length and the

register size of the uP.

• 8085 uP is called an 8-bit uP ( 8 lines).

• Intel 8086, Zilog Z800, Motorola 68000 have 16

data lines ( 16-bit uP).

• In the 8085 the data bus and 8 lines of the address

bus are multiplexed (share lines).

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Control bus:

• Single lines ( Bi-directional ).

• Signals in the form of requests reach CPU

from peripherals.

• HOLD, READY, INTA’, etc.

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• Read: CPU reads from memory

• Write: CPU writes to memory

Main Memory Access by CPU

Read Operation:Read contents of memory location 2050h = 2Ah

• The 16 address lines contain 0010 0000 0101 0000B = 2050h to identify the memory location

• The control bus sends the MEMR’ signal to read the contents of that location.

• The contents of memory location 2050 (2Ah) are placed on to the data bus and brought in to the CPU.

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Read Operation:(1): 0010 0000 0101 0000 = 2050H

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(2)

(3) 2AH goes in to CPU

Write Operation:

Write 6Dh into memory location 2052H.

• The 16 address lines contain 0010 0000 0101 0010B = 2052h to identify the memory location

• The control bus sends the MEMW’ signal to write in the bus contents in to that location.

• Data is placed on the data bus from the CPU and written into memory location 2052

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Write Operation:

(1): 0010 0000 0101 0010 = 2052H

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‘ (2)

(3): 6DH goes to mem loc 2052H

8085 Registers

• The 8085 CPU has 6 general-purpose registers:B, C, D, E, H, L . They store 8-bit data during a program execution.

• They can be combined as registers pairs BC, DE, HL to perform 16-bit operations.

• The accumulator (register A ) is the key register. It is used to store 8-bit data & accumulate results from ALU.

• It always forms one of the inputs to ALU.

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8085 registers:

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40

• The 8085 is an 8-bit microprocessor made by

Intel.

• It has:

– 6 general purpose registers

– An accumulator

– A flag register

– A stack pointer

– A program counter

Accumulator Flags

B C

D E

H L

Program Counter

Stack Pointer

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The 8085 Programming Model

41

The 8085 Programming Model• The Registers

– The 6 general purpose registers are 8-bits wide

each.

• They are to be used as needed.

• They are called B, C, D, E, H, and L.

• They can be used as 16-bit register pairs: BC, DE,

HL.

– The accumulator is technically part of the ALU.

• It is 8-bits wide.

• It is one of the inputs to every ALU operation.

• The result of any operation is always stored in it.

• It is known as Register A.

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The 8085 Programming Model

– The CPU includes five flag flip-flops that are

set or reset after an operation.

• They are Z (zero), CY (carry), S (sign), P (parity)

and AC (Auxiliary Carry).

• These flags are used when the microprocessor tests

for data conditions.

• These make up the Flags Register.

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D7 D6 D5 D4 D3 D2 D1 D0

Cy S - P - Ac - Z

Flags:

• They are FF's which are set or reset according to certain data conditions in the accumulator and other registers.

• Flags are used in testing for data conditions.

• The 8085 has 5 flags: Carry (CY), Zero (Z), Sign (S), Parity (P), and Auxiliary Carry (AC) .

• The most commonly used flags are: Carry (CY), Zero (Z), Sign (S).

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B3 B0B1B2B4B5B6B7

-- Cy--PAC--ZS

STATUS REGISTER (FLAGS):

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Accumulator:

• 8-bit register used as a GPR.

• It accumulates results an operation.

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ACCALU

Program Counter (PC):

• 16-bit register.

• Its function is to point to the memory

address from which the next byte is to be

fetched.

• When a byte (machine code) is being

fetched, the PC is incremented by one to

point to the next memory location.

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Stack Pointer (SP):

• 16-bit register used as a memory pointer.

• It points to a memory location(TOS) in R/W

memory, called the stack .

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Instruction Encoding:

0 1 2 3 4 7

op reg loc

op reg reg reg

0 1 2 3 4 5 6 7

op cond target

0 1 2 4 5 7

Load/Store

Add

Branch

Opcodes

Load

Store

Branch

Add

00

01

10

11

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Ex: MOV A,B == 78 0 1 2 3 4 7

op Dstn Src

0 1 1 1 1 0 0 0

Instruction Fetch Operation

I C = F C + E C

Ex: Instruction Fetch Operation Timing


Ex: MOV A,B

MOV A,M

MVI A,32h

MVI M,32h

LXI H,1234h

STA 2040h

LHLD 2040h

DIFFERENT M/C CYCLES IN 8085:

• OF Cycle: Fetch the OP-Code of an instruction to

be executed, from memory (4T).

• MR Cycle: Reads information (other than OP-

Code) from the memory (3T).

• MW Cycle: Writes information into the memory

(3T).

• IOR Cycle: Reads information (data) from the

input device (3T).

• IOW Cycle: writes information on to an output

port (3T).

• INA Cycle: This is CPU’s acknowledgement to an

interrupt request from peripheral (12T-3MC).

Ex: Timing Status

IO / M’ S1 S0 Machine cycle

0 1 1 Op-code fetch

0 1 0 Memory Read

0 0 1 Memory write

1 1 0 I O Read

1 0 1 IO Write

1 1 1 INT ACK

0 1 0 BI-Cycle

0 0 0 HLT


Instruction

(opcode)

reaches the

instruction

decoder now !

It takes four

clock cycles

to get one

instruction

into the CPU.


• OF Cycle is the first m/c cycle of any

instruction.

•OF cycle will be normally of 4 T-states.

•Multiplexed Address / Data bus –

-low order address during T1,

-data between T2 & T3 depend on RD’/WR’

•ALE serves two purposes

(i) It enables buffers to latch low order

address (for further use).

(ii) It helps in identifying the beginning of

an m/c cycle.

Execution of an Instruction:Execution of a simple instruction:

Instruction 3E (hex) means: Load a data byte

into the accumulator MVI A, __

The instruction is followed by the data byte 32

(hex). Two-byte instruction !

The instruction timing is in next slide.

Execution of an Instruction: MVI A, 32h


Put the first

Memory

address on

the address

bus (2000 h)


Get the

instruction

(opcode)

byte from

memory


Interpret

the

instruction:

Wait for the

data byte !

Execution of an Instruction:MVI A, 32h

Put the next

Memory

address on

the address

bus (2001 h)


Get the data

byte from the

memory

Put into

accumulator

Execution of an Instruction:

How long does it take to execute this two-byte

instruction (op-code) ?

It is quite possible to accurately predict the time

that is required to run each instruction, and to

run the entire program !

Execution of STA Instruction:

WAIT States:

Execution of an INA cycle:

Execution of an BI cycle:

Instruction types

Requirements of an instruction set

① should be complete

② should be efficient in that frequently required functions can be preformed

rapidly using relatively few instructions.

③ should be regular

④ should be compatible to reduce hardware & software design cost

No standard machine

Five main types of instructions

① Data-transfer instructions, which copy information from one location to

another either in the processor’s internal register set or in the external main

memory.

② Arithmetic instructions, which perform operations on numerical data.

③ Logical instructions, which include Boolean and other non-numerical

operations.

④ Program-control instructions, such as branch instructions, which change

the sequence in which programs are executed.

⑤ Input-output( IO ) instructions, which cause information to be transferred

between the processor or its main memory and external IO devices.

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3.3.3 Programming Consideration

Assembly language programming

Assembler : translation of assembly language instruction into the equivalent

machine instructions.

Pseudo instruction : not part of object code

Macro instruction(macro) not part of object code

Subroutine : part of object code

Tools to simplify

the program

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8085 Instruction Set:

The 8085 instructions can be classified as follows:

Data transfer Group

Arithmetic Group (ADD, SUB, INR, DCR)

Logic Group

Branching Group (JMP, CALL, RET)

Stack I/O, Machine Control, I/O Group

• Between registers

• Between memory location and a register

• Direct write to a register / memory

• Between I/O device and accumulator

8085 Instruction Types:

One Byte Instructions

Ex: MOV A,B, ADD B, etc.

8085 Instruction Types:

76

The 8085 Instructions– Since the 8085 is an 8-bit device it can have up to 28

(256) instructions.

• However, the 8085 only uses 246 combinations that

represent a total of 74 instructions.

– Most of the instructions have more than one format.

– These instructions can be grouped into five

different groups:

• Data Transfer Operations

• Arithmetic Operations

• Logic Operations

• Branch Operations

• Machine Control Operations

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Instruction and Data Formats• Each instruction has two parts.

– The first part is the task or operation to be

performed.

• This part is called the “opcode” (operation code).

– The second part is the data to be operated on

• Called the “operand/s”.

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Op-Code Opd1 Opd2 Opd3 - - - -

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Operand Types• There are different ways for specifying the

operand:

– There may not be an operand (implied operand)

• CMA

– The operand may be an 8-bit number (immediate

data) ADI 4FH

– The operand may be an internal register (register)

• SUB B

– The operand may be a 16-bit address (memory

address)

• LDA 4000H

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Instruction Size• Depending on the operand type, the instruction

may have different sizes. It will occupy a different

number of memory bytes.

– Typically, all instructions occupy one byte

only.

– The exception is any instruction that contains

immediate data or a memory address.

• Instructions that include immediate data use two

bytes.

– One for the opcode and the other for the 8-bit data.

• Instructions that include a memory address occupy

three bytes.

– One for the opcode, and the other two for the 16-bit address.

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Instruction with Immediate Date• Operation: Load an 8-bit number into the

accumulator.

– MVI A, 32

• Operation: MVI A

• Operand: The number 32

• Binary Code:

0011 1110 3E 1st byte.

0011 0010 32 2nd byte.

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Instruction with a Memory Address

• Operation: go to address 2085.

– Instruction: JMP 2085

• Opcode: JMP

• Operand: 2085

• Binary code:

1100 0011 C3 1st byte.

1000 0101 85 2nd byte

0010 0000 20 3rd byte

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Addressing Modes• The microprocessor has different ways of

specifying the data for the instruction.

These are called “addressing modes”.

• The 8085 has four addressing modes:

– Implied CMA

– Immediate MVI B, 45

– Direct LDA 4000

– Indirect LDAX B

• Load the accumulator with the contents of the

memory location whose address is stored in the

register pair BC).

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Data Formats• In an 8-bit microprocessor, data can be

represented in one of four formats:• ASCII

• BCD

• Signed Integer

• Unsigned Integer.

– It is important to recognize that the

microprocessor deals with 0’s and 1’s.

• It deals with values as strings of bits.

• It is the job of the user to add a meaning to these

strings.

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Data Formats• Assume the accumulator contains the

following value: 0100 0001.

– There are four ways of reading this value:

• It is an unsigned integer expressed in binary, the

equivalent decimal number would be 65.

• It is a number expressed in BCD (Binary Coded

Decimal) format. That would make it, 41.

• It is an ASCII representation of a letter. That would

make it the letter A.

• It is a string of 0’s and 1’s where the 0th and the 6th

bits are set to 1 while all other bits are set to 0.ASCII stands for American Standard Code for Information Interchange.

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Busy/Wait Processing

• The CPU is focused only on the I/O activity

of the system

• All other pending activities are on hold until

the I/O activities are concluded

86

Register Pairs:• The 8085 is an 8-bit microprocessor. So, its

general purpose registers are 8-bits wide.

– But, it uses 16-bit addresses.

• To allow manipulation of the 16-bit addresses, the

8085 allows its registers to be paired.

– In other words, it is possible to combine two 8-bit

registers together into a 16-bit super register or a

register pair.

• The 8085 recognizes only 3 register pairs: B and

C, D and E and H and L.

– It is not possible to pair B and E for example.

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Identifying Register Pairs:

• A register pair is identified with the name of

the first register in the pair.

• Therefore, the three register pairs are called:

– B for the B,C pair

– D for the D,E pair

– H for the H,L pair

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Placing 16-bit Data into a Register Pair:

• To place a 16-bit number into a register

pair, we can place an 8-bit number in each

of the two registers.MVI L 00H

MVI H 32H

– But, in what order?MVI L 00H or MVI L 32H

MVI H 32H MVI H 00H

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The LXI instruction:

• The 8085 provides an instruction to place

the 16-bit data into the register pair in one

step.

• LXI Rp, <16-bit address>

(Load eXtended Immediate)

– The instruction LXI B 4000H will place the

16-bit number 4000 into the register pair B, C.

• The upper two digits are placed in the 1st register of

the pair and the lower two digits in the 2nd .

B C40 00LXI B 40 00H

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The Memory “Register”:• Most of the instructions of the 8085 can use

a memory location in place of a register.– The memory location will become the “memory” register M.

• MOV M, B

– copy the data from register B into a memory location.

– Which memory location?

• The memory location is identified by the

contents of the HL register pair.

– The 16-bit contents of the HL register pair are

treated as a 16-bit address and used to identify

the memory location.Madan H R

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Indirect Addressing Mode:• Using data in memory directly (without

loading first into a Microprocessor’s

register) is called Indirect Addressing.

• Indirect addressing uses the data in a

register pair as a 16-bit address to identify

the memory location being accessed.

– The HL register pair is always used in

conjunction with the memory register “M”.

– The BC and DE register pairs can be used to

load data into the Accumultor using indirect

addressing.

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Using the Other Register Pairs:– There is also an instruction for moving data

from memory to the accumulator without

disturbing the contents of the H and L

register.

• LDAX Rp (LoaD Accumulator eXtended)

– Copy the 8-bit contents of the memory location identified

by the Rp register pair into the Accumulator.

– This instruction only uses the BC or DE pair.

– It does not accept the HL pair.

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Manipulating Addresses

• Now that we have a 16-bit address in a

register pair, how do we manipulate it?

– It is possible to manipulate a 16-bit address

stored in a register pair as one entity using

some special instructions.• INX Rp (Increment the 16-bit number in the register pair)

• DCX Rp (Decrement the 16-bit number in the register pair)

– The register pair is incremented or decremented

as one entity. No need to worry about a carry

from the lower 8-bits to the upper. It is taken

care of automatically.

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Memory Related Arithmetic Operations :

• These instructions perform an arithmetic operation

using the contents of a memory location while

they are still in memory.

– ADD M

• Add the contents of M to the Accumulator

– SUB M

• Sub the contents of M from the Accumulator

– INR M / DCR M

• Increment/decrement the contents of the memory location in

place.

– All of these use the contents of the HL register pair to

identify the memory location being used.Madan H R

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Additional Logic Operations:

• Rotate

– Rotate the contents of the accumulator one

position to the left or right.– RLC Rotate the accumulator left.

Bit 7 goes to bit 0 AND the Carry flag.

– RAL Rotate the accumulator left through the carry.

Bit 7 goes to the carry and carry goes to bit 0.

– RRC Rotate the accumulator right.

Bit 0 goes to bit 7 AND the Carry flag.

– RAR Rotate the accumulator right through the carry.

Bit 0 goes to the carry and carry goes to bit 7.

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RLC vs. RAL:

• RLC

• RAL

Accumulator

C Carry Flag

7 6 5 4 3 2 1 0

C

Accumulator

Carry Flag

7 6 5 4 3 2 1 0

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Logical Operations:• Compare

• Compare the contents of a register or memory

location with the contents of the accumulator.

– CMP R/M Compare the contents of the register

or memory location to the contents of

the accumulator.

– CPI # Compare the 8-bit number to the

contents of the accumulator.

• The compare instruction sets the flags (Z, Cy, and S).

• The compare is done using an internal subtraction

that does not change the contents of the accumulator.

A – (R / M / #)

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A VERY Simple Program:

Add two hexadecimal numbers:

Load register A (accumulator) with 32 (hex)

Load register B with 48 (hex)

Add the two numbers and save the sum in A

Display accumulator (A) contents at port (01)

End

A VERY Simple Program:

Write a program to move a block of N

bytes starting from location X to

locations starting from Y without

overlap. [Destination locations are

independent of Source locations.]

a) Assumptions:[i] Let the value of X be C100

[ii] Let the value of Y be C200

[iii] Let block length N be equal to 10.

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Initialize HL as source pointer to loc X.

Initialize DE as destination pointer to loc Y.

Initialize C as counter with value N.

Load from loc pointed by HL in to A register. Store the same at a loc pointed by DE.

Modify both source & destination pointers.

Decrement counter to reflect the transfer.

Is [C] = 0 ?

Stop

Start

N

Y

b) Flow Chart:

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ADDRES

S

OP-CODE LABE

L

MNEMONICS COMMENTS

LXI H, C100 ; Initialize HL as source

pointer to

; locX.

LXI D, C200 ; Initialize DE as destination

; pointer to locY.

MVI C, 0AH ; Initialize C as counter with

block

; length N.

REP:

MOV A, M ; Read the element from loc

; pointed to by HL in to reg A.

STAX D ; Store that element to the loc

; pointed to by destn pointer

DE.INX H ; Update source pointer to

next

; location.INX D ; Update destn pointer to next

; location.

DCR C ; Decrement Counter C to

reflect

; the transferJNZ REP ; If all data elements are not

; moved, go to label REP &

repeat

; the transfer process,

RST1 ; else, stop.

c) Program:

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Write a program to move a block of N bytes starting

from location X to locations starting from Y with an

overlap. [ A part of destination locations will be a

part of Source locations.]


[ii] Let the value of Y be C105, five locations (say) of

source overlapping with the destn .


[iv] If destn address is greater than source address, then

both the pointers are made to point to the end of array

& transfer is done from end.

[v] If destn address is less than source address, then

normal transfer can be used.

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Initialize HL as source pointer to loc X.

Initialize DE as destination pointer to loc Y.

[ Modify the pointers if needed to point to end of arrays so as to transfer

from end.]

Initialize C as counter with N value

Load from loc pointed by HL in to A register. Store the same at a loc pointed

by DE.



Is [C] = 0 ?

Stop

Start

N

Y

b) Flow Chart:

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ADDRESS OP-CODE LABEL MNEMONICS COMMENTS

LXI H, C100 ; Initialize HL as source pointer

; to locX.LXI D, C105 ; Initialize DE as destination

; pointer to locY.MVI C, 0A ; Initialize C as counter with

; block length N.MVI B, 00 ; Modify the pointers to point to

; the last locations in both source DCX B ; & destn so that tranfer takes

DAD B ; place the end of array to the

XCHG ; beginning. NOTE: If destn add

DAD B ; is smaller than source add this

; modification is not needed,XCHG ; normal transfer can be done.

INX B

REP: MOV A, M ; Read the element from loc

; pointed to by HL in to reg A. STAX D ; Store that element in to the loc

; pointed toby destn pointer DE.DCX H ; Update source pointer to

previous

; location.DCX D ; Update destn pointer to

previous

; location.DCR C ; Update the counter to reflect the

; transfer.JNZ REP ; If all the elements are not moved

; go to label REP & repeat theRST1 ; transfer, else, stop.

c) Prog

ram:

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Write a program to interchange N bytes

of data stored from location X and

location Y.


[ii] Let the value of Y be C200


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b) Flow Chart:

Initialize HL as source-1 pointer to loc X.

Initialize DE as source-2 pointer to loc Y.

Initialize C as counter with value N.

Load from loc pointed by HL in to B reg. Load from loc pointed by DE in to A reg. Store from A reg to a loc pointed by HL. Store from B reg to a loc pointed by DE.



Is [C] = 0 ?

Stop

Start

N

Y

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c) Prog

ram:ADDRESS OP-CODE LABEL MNEMONICS COMMENTS

LXI H, C100 ; Initialize HL as a pointer to locX.

LXI D, C200 ; Initialize DE as a pointer to locY.

MVI C, 0A ; Initialize C as counter with block

; length N

LOOP: MOV B, M ; Read the element from loc pointed

;to by HL in to reg B.

LDAX D ; Read the element from loc pointed

; to by DE in to reg A.

MOV M, A ; Store element from array2[already

; in A] into array1.

MOV A,B ; Store the element from array1

STAX D ; ; [already in B] into array2.

INX H ; Update HL pointer to next location.

INX D ; Update DE pointer to next location.

DCR C ; Decrement Counter C to reflect the

; exchange

JNZ LOOP ; If all data elements are not

; interchanged, go to label LOOP &

RST1 ; repeat the process, else, stop

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Write a program to add an array of N one byte

elements stored from location X+1, where N is

stored in loc X. Display the result in address

field.

a) Assumptions:

[i] Let the value of X be C100.

[ii] Let the result be a 16 bit number.

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b) Flow Chart:

Initialize HL pointer with loc X value. Initialize C

with N value from loc X. Increment HL to point to

first element.

Initialize RESULT register to zero& clear carry flag.

Add the element pointed by HL to the RESULT register

Stop

Start

Is [C] = 0 ?

Display the result in address field.

Modify HL pointer. Decrement the counter to

reflect the addition.

N

Y

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c) Prog

ram:ADDRESS OP-CODE LABEL MNEMONICS COMMENTS

LXI H, C100 ; Initialize HL with loc X as pointer

; to loc X.

MOV C, M ; Transfer the count N to C reg.

INX H ; Increment HL to point first elemt.

XRA A ; Clear A & B [RESULT]registers.

; Clear CY flag.

MOV B, A ;

REP: ADD M ; Add the element to RESULT

; register & Update.

JNC SKIP ;

INR B

SKIP: INX H ; Modify the pointer to point to the

; next element.

DCR C ; Decrement counter to reflect the

; addition.

JNZ REP ; Check whether all N bytes are

; added, if no REP.

MOV L, A ; else, display the result.

MOV H, B

SHLD FFF7

MVI B, 00

CALL UPDAD

HLT ; End

Madan H R111

Write a program to add two multi-byte

numbers stored from location X & loc

Y. Display the result in data field.

a) Assumptions:[i] Let the value of X be C100.

[ii] Let the value of Y be C200.

[iii] Let the value of Z be C300.

Madan H R112

b) Flow Chart:

Initialize HL pointer with loc Z value & store it in a

memory location. Initialize C with N value. Initialize

HL pointer with loc X value Initialize DE pointer

with loc Y. Clear CY flag.

Add the element pointed by HL to the element pointed by DE with carry & store the result.

Stop

Start

Is [C] = 0 ?

Display the result in data field.

Modify HL pointer. Modify DE pointer.

Decrement the counter to reflect the addition.

N

Y

Madan H R113

c) Prog

ram:

ADDRESS OP-CODE LABEL MNEMONICS COMMENTS

LXI H, C300 ; Initialize HL with loc Z as pointer to loc Z.

SHLD C500 ; Preserve it in memory loc C500 & C501.

LXI H, C100 ; Initialize HL with loc X to point to loc X.

LXI D, C200 ; Initialize DE with loc Y to point to loc Y.

MVI C, NUM ; Initialize C with No of bytes to be added.

XRA A ; Clear CY flag.

REP: LDAX D ; Add the element pointed by HL with

ADC M ; the element pointed by DE including CY bit.

PUSH H ; Store the result in result locations.

LHLD C500

MOV M, A

INX H

SHLD C500

POP H

INX D ; Modify the pointers to point to the

INX H ; next elements.

DCR C ; Decrement counter to reflect the addition.

JNZ REP ; Check whether all N bytes are added, if noREP.

DISP: LXI H, C300 ; else, display the result in the address

MVI C, NUM+1 ; field one element after the other with

RESLT MOV A, M ; delay in-between successive displays.

PUSH H

PUSH B

STA FFF9

CALL UPDDT

LXI D, FFFF

CALL DELAY

POP B

POP H

INX H

DCR C

JNZ RESLT

HLT ; End

Madan H R114

Memory:

• Memory is an essential component of a uC

system; it stores binary instructions and data for

the uP.

• Prime memory: R/WM and ROM .

• The R/W memory is made of registers , and

each register has a group of FFs .

• The user uses this type of memory to hold

programs and store data.

• ROM stores data permanently.

115 Madan H R

Memory:

To communicate with memory, the CPU

should be able to:

• Select the chip

• Identify the register

• Read from or write into the register

116 Madan H R

Latch with Two Tri-state Buffers:

• When WR is active (WR=0) data (Din) can be

written into the FF.

• When RD is active (RD=0) data (Dout) can be read

from the FF

• WR and RD cannot be active simultaneously.117 Madan H R

1 x 4-bit register:

RD control input signals. WR control

output signals

118 Madan H R

4 x 8-bit register:

• Four registers

• Each register can store 8 bits119 Madan H R

8 x 8-bit register:

To make I/O lines inputs, RD = 0 and WR = 1

To make I/O lines outputs, RD = 1 and WR = 0

120 Madan H R

Memory Map:

• A memory map is a pictorial representation in

which memory devices are located in the entire

range of addresses.

• Typically, in an 8-bit uC system, 16 address lines

are available for memory.

• 216 = 65,536 memory registers can be

identified. Each register with a 16-bit address.

• The entire memory address can range from

0000 to FFFF in Hex.

121 Madan H R

Memory Map:

• Memory addresses provide the locations of various

memory devices in the system, and the interfacing

logic defines the range of memory addresses for each

memory device.

• The SDK-85 uC has 256 registers and 16

address lines.

• 256 registers require only 8 address lines

(28 = 256). What should we do with the remaining

8 address lines?

• Answer: They are used to select the chip

122 Madan H R

(a) RAM (b) ROM:

123 Madan H R

See Figure & Identify the memory map:

• To activate the device,

CS = 0

• CS = 0 when all inputs

are 1

• A0 – A7 can have up to

256 (28) combinations:

• Minimum: 0000 0000

• Maximum: 1111 1111

• Address range – FF00 h

to FFFF h

124 Madan H R

See Figure & Identify the memory map:

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 00FFh

Memory map:

0000H to 00FFH

125 Madan H R

See Figure & Identify the memory map

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000h

1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 80FFh

126 Madan H R

Memorymap:

8000H to 80FFH

Determine the Memory Map

127 Madan H R

• The chip select address are determined by thehardware (hardware/software).

• Therefore, the memory map of the chip can be changed by modifying the hardware .

• The lines used for chip select are called high-order (high-order/low-order) address lines and the lines connected to memory addresslines are called low-order (high-order/low-order) address lines.

128 Madan H R

Input and Output (I/O) Devices

• I/O devices are the means through which

the CPU communicates with the outside

world .

• There are two different methods by which

I/O devices can be identified

– Peripheral Mapped I/O

– Memory Mapped I/O

129 Madan H R

I/O with 8-bit Addresses

(Peripheral-Mapped I/O)

• The CPU uses 8 address lines to identify

an input or an output device.

• With 8-address lines (28 = 256) input

devices and 256 output devices can be

identified.

• The input and output devices are

differentiated by the control signals.

130 Madan H R



• The CPU uses the I/O Read control

signal for input devices.

• The CPU uses the I/O Write control

signal for output devices.

• The entire range of I/O addresses from 00H

to FFH is knows as an I/O Map .

• Individual addresses are refereed to as I/O

Device Addresses or I/O Port .131 Madan H R



The steps in communicating with an I/O

device are similar to those in

communicating with memory.

• The CPU places an 8-bit address on the

address bus

• The CPU sends a control signal (I/O Read

or I/O Write) and enables the I/O device

• Data are transferred using the Data Bus132 Madan H R

I/O with 16-bit Addresses (Memory-

Mapped I/O)

• The CPU uses 16 address lines to identify

an I/O device.

• An I/O device is connected as if it is a

memory register.

• The CPU follows the same steps as if it is

accessing a memory register.

133 Madan H R

Buffer

• The buffer is a logic circuit that amplifies current or power

• It has one input line and one output line

• The buffer is used primarily to increase the driving capability of a logic circuit

• It is also known as a driver

• The buffer is commonly used to increase the driving capability of the data bus and the address lines

134 Madan H R

Buffer

135 Madan H R

Bidirectional Buffer

• The data bus of a microcomputer system is

bidirectional; therefore, it requires a buffer

that allows data to flow in both directions

• The 74LS245, also called an Octal Bus

Transceiver, has 16 bus drivers, eight for

each direction, with tri-state output

136 Madan H R

Bidirectional Buffer

137 Madan H R

Decoder

• The decoder is a logic circuit that identifies

each combination of the signals present at

its input

• Only one output line is active at the decoder

• A decoder is a commonly used device in

interfacing I/O peripherals and memory

138 Madan H R

Decoder

139 Madan H R

Decoder

140 Madan H R

Encoder• The encoder is a logic circuit that provides the

appropriate code (binary, BCD, etc.) as output for each input signal

• The process is the reverse of decoding

• In an encoder only one input should be active at a time

• Priority encoders resolve the problem of simultaneous inputs

• Encoders are used with keyboards. For each key pressed, the corresponding binary code is placed on the data bus

141 Madan H R

Encoder

142 Madan H R

Encoder

143 Madan H R

D Flip-Flops

• A latch is used commonly to interface

output devices

• When the CPU sends an output, data are

available on the data bus for only a few

microseconds; therefore, a latch is used to

hold data for display

144 Madan H R

D Flip-Flops

145 Madan H R

D Flip-Flops

146 Madan H R

Interrupts and Interrupt Procesing

Madan H R148

Generic interrupt mechanism

intr?N

Y

Assume priority selection is handled before this point.

N

ignore

Y

ack

vector?

Y

Y

Ntimeout?

Ybus error

call table[vector]

intr priority >

current priority?

continue

execution

Madan H R149

Interrupt sequence

• CPU acknowledges request.

• Device sends vector.

• CPU calls handler.

• Software processes request.

• CPU restores state to foreground program.

Madan H R150

Sources of interrupt overhead

• Handler execution time.

• Interrupt mechanism overhead.

• Register save/restore.

• Pipeline-related penalties.

• Cache-related penalties.

151 Madan H R

• Sources-

– There are three sources:

• Hard ware Interrupts.

• Soft ware Interrupts.

• Internally generated.

In 8085 five H/W interrupts & 8 S/W interrupts.8085 Contains only first 2 types

SIM FORMAT:

RIM FORMAT:

Interrupt System:

SOD SOE X R7.5 MSE M7.5 M6.5 M5.5

SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5

152 Madan H R

INTERRUPTS

R 7.5

FF

R 6.5

MASK

R 7.5

MASK

R 5.5

MASK

TRAPFF

R

E

Q

10

9

8

7

6

INTE

FF

EI DI

RESETIN’ INTA’

S

R

S

R

S

R

D

D 1

1

CLR

CLR

TRAP

RST7.5

RST6.5

RST5.5

INTRMSE(SIM)

M7.5(SIM)

M5.5(SIM)

M6.5(SIM)

R7.5ACKRESETIN’

R7.5(SIM)

RESETIN’TRAP ACK

Madan H R153

Interrupt I/O

• Busy/wait is very inefficient.

– CPU can’t do other work while testing device.

– Hard to do simultaneous I/O.

• Interrupts allow a device to change the flow

of control in the CPU.

– Causes subroutine call to handle device.

Madan H R154

Interrupt interface

CPU

status

reg

data

reg mech

an

ism

PC

intr request

intr ack

data/address

IR

Madan H R155

Interrupt behavior

• Based on subroutine call mechanism.

• Interrupt forces next instruction to be a

subroutine call to a predetermined location.

– Return address is saved to resume executing

foreground program.

Madan H R156

Interrupt physical interface

• CPU and device are connected by CPU bus.

• CPU and device handshake:

– device asserts interrupt request;

– CPU asserts interrupt acknowledge when it can

handle the interrupt.

Madan H R157

Example: character I/O handlers

void input_handler() {

achar = peek(IN_DATA);

gotchar = TRUE;

poke(IN_STATUS,0);

}

void output_handler() {

}

Madan H R158

Example: interrupt-driven main

program

main() {

while (TRUE) {

if (gotchar) {

poke(OUT_DATA,achar);

poke(OUT_STATUS,1);

gotchar = FALSE;

}

}

}

Madan H R159

Example: interrupt I/O with

buffers

• Queue for characters:

headtailhead tail

a

Madan H R160

Buffer-based input handler

void input_handler() {

char achar;

if (full_buffer()) error = 1;

else { achar = peek(IN_DATA); add_char(achar); }

poke(IN_STATUS,0);

if (nchars == 1)

{ poke(OUT_DATA,remove_char();

poke(OUT_STATUS,1); }

}

Madan H R161

I/O sequence diagram

:foreground :input :output :queue

empty

a

empty

b

bc

c

Madan H R162

Debugging interrupt code

• What if you forget to change registers?

– Foreground program can exhibit mysterious

bugs.

– Bugs will be hard to repeat---depend on

interrupt timing.

Madan H R163

Priorities and vectors

• Two mechanisms allow us to make

interrupts more specific:

– Priorities determine what interrupt gets CPU

first.

– Vectors determine what code is called for each

type of interrupt.

• Mechanisms are orthogonal: most CPUs

provide both.

Madan H R164

Prioritized interrupts

CPU

device 1 device 2 device n

L1 L2 .. Ln

interrupt

acknowledge

Madan H R165

Interrupt prioritization

• Masking: interrupt with priority lower than

current priority is not recognized until

pending interrupt is complete.

• Non-maskable interrupt (NMI): highest-

priority, never masked.

– Often used for power-down.

Madan H R166

Example: Prioritized I/O

:interrupts :foreground :A :B :C

B

A,B

C

A

Madan H R167

Interrupt vectors

• Allow different devices to be handled by

different code.

• Interrupt vector table:

handler 0

handler 1

handler 2

handler 3

Interrupt

vector

table head

Madan H R168

Interrupt vector acquisition

:CPU :device

receive

request

receive

ack

receive

vector

169

THANK YOU

Madan H R

RISC versus CISC

With cheaper hardware, instructions tend to increase both in number and

complexity.

Suppose that a particular complex operation F can be implemented either by

a single complex instruction IF or by a multi-instruction routine PF composed of

single instruction.

Execution of PF will be slower than that of IF due to fetching time.

PF occupies more memory space than IF.

IF address to the complexity of control unit, thus increasing the size of the

processor and design time.

Madan H R170

RISC versus CISC

Assembly language : simple by using IF

High-level language

: The improvement in the execution speed for IF may not fully realizable.

A compiler will translate F into the corresponding instruction IF which uses

fixed CPU registers and has a fixed execution time. If IF is not available, an

efficient “optimizing” compiler may be able to generate object code OF

corresponding to PF that exploits information known at compilation time, to

reduce the execution time for F.

The speed gap between IF and PF can be narrowed by designing the small

instruction set required for PF, to reduce the instruction fetch and execution

cycle times as far as possible. Another speed advantage of PF over IF is that

PF can be interrupted in mid-operation, whereas IF must proceed to termination

before CPU can respond to an interrupt.

Madan H R171

RISC versus CISC

The main features of RISC(Reduced Instruction Set Computer)

1. Relatively few instruction types and addressing modes.

2. Fixed and easily decoded instruction formats.

3. Fast single-cycle instruction execution. /* Main point */

4. Hardwired rather than microprogrammed control.

5. Memory access limited mainly to load and store instruction.

Large # of registers in CPU. Most RISC instructions involve only

register-to- register operation internal to CPU

6. Use of compilers to optimize object code performance.

Key points : efficient compilation cooperation of the machine

architects and compiler

In scientific computing application with lots of floating-point arithmetic, CISC

is better.Madan H R172

RISC versus CISC

RISC I microprocessor( by Patterson )

A single-chip 32 bit CPU, 32 bit 138 general purpose registers

- to achieve single cycle execution with instructions of fixed size (all

instructions are 32 bit long)

- to access main memory with load and store only.

- to provide some support for high level language.

Instruction format of RISC I

0 6 7 8 12 13 18 19 31

set condition

code

set immediate

address

Opcod

e

Source1

RS

Destination

RD

Source2 S2

Relative address

YMadan H R173

architecture of 8085

Devices & Hardware