application note avs / dvs and margining circuits for ... · avs / dvs and margining circuits for...

V I S H A Y S I L I C O N I X

ICs Application Note

AVS / DVS and Margining Circuits forVishay Power ICs SiC40X Series SMPS Regulators

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Revision: 18-Jul-16 1 Document Number: 65304

For technical questions, contact: [email protected] DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

www.vishay.com

by Ronald Vinsant

ABSTRACTThere are many applications that require that a voltage rail within a system be capable of being adjusted by a digital or analog control signal. These circuits may only need to do a margining function in a test mode, vary the output voltage from the regulator by only a small amount to optimize specific performance parameters, or perhaps the voltage must be widely scalable to allow for the use of different sensors in an industrial application. This application note will show a number of different solutions to these design challenges by utilizing the Vishay SiC40X series of synchronous buck regulators. A key aspect of this design is the COT architecture of this family of products, which allows adaptability of the control system to the different operating points of the regulator without any iterative compensation design.

A spreadsheet tool and simulation schematic will be introduced that enable the user to quickly derive a solution with knowledge of only a few required parameters. Confirmation of the validity of these two tools will be shown by use of the SiC401DB, SiC402DB, and SiC403DB reference board, with the addition of only two resistors, a capacitor, and a user-supplied voltage source. This source could be an existing rail with an analog switch, a GPIO or PWM on an FPGA or processor, or a DAC.

SiC40X DESCRIPTIONThe Vishay Siliconix SiC401A/B, SiC402A/B, and SiC403A/B are advanced stand-alone synchronous buck regulators, featuring integrated power MOSFETs, a bootstrap switch, and a programmable LDO in space-saving PowerPAK® MLP55-32L pin packages.

The SiC401A/B, SiC402A/B, and SiC403A/B are capable of operating with all ceramic solutions and switching frequencies up to 1 MHz. The programmable frequency, synchronous operation, and selectable power-save feature allow operation at high efficiency across the full range of load current. See www.vishay.com/doc?62768.

THE REFERENCE BOARDThis reference board allows the end user to evaluate the SiC401A/B, SiC402A/B, and SiC403A/B for their features and all functionalities. It can also be a reference design for a user's application. See www.vishay.com/doc?62923.

CALCULATION TOOLSThe designer can start their design by using the reference board mentioned above. If the reference board does not meet the goals of the designer’s application, then a design tool is available online at www.vishay.com/doc?62923.

Once a regulator design has been chosen, there is an Excel tool, an AVS calculator, located at www.vishay.com/doc?77389.

This tool allows the designer to add to the existing regulator circuit adjustability of the output voltage through an external signal from a DAC or other voltage source. In addition, this spreadsheet has some programmer’s tools to make the writing of software to drive the DAC easier.

http://www.vishay.com


Application Notewww.vishay.com Vishay Siliconix




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HOW IT WORKS

Theory

To describe the theory of operation, a design from Vishay’s AVS calculator tool has been chosen that extends to the boundaries of operation of the SiC40X family of regulators (Fig. 1). The yellow cells indicate the only parameters required from a user to generate a design. Details of the calculator will be covered later in this application note.

Fig. 1 - Calculation Results for Theory of Operation

Fig. 2 shows a schematic of the reference board. The area circled in black is where a signal will be injected to alter the output voltage. R53, R54, and C38 have been added to the original schematic. In all the simulations below, the op-amps that are used are very close to ideal, thus the calculations are very exacting.

Fig. 2 - Reference Board Schematic (Modified)

The circled area in Fig. 2 provides a simplified view of DC operation.

Step 1: Calculate RTOP and RDAC

VREF (V)

RBOT (R23above)

(Ω)

IRBOT

(A)SiC4XX VOUT

max. (V)

SiC4XX VOUT min.

(V)

DetermineDAC gain (DAC V / output V)

(ratio)

Determinezero RDAC

currentpoint for

VOUT(VDAC = VREF)

(V)

Calculate

RTOP(Ω)

Calculate

RDAC(Ω)

0.6 5110 0.000117 5 0.25 -1.9 3.86 27764.33 14612.81

DAC max.VOUT(V)

DAC bits (number)

DAC LSB(V)

1 DAC LSBadjust in

SiC4XX VOUT(V)

Total count(theoreticalnumber of

voltage steps fromDAC)

(number)

2.5 16 3.81-5 7.24792-5

Step 2: Input DAC parameters

65536

R54VDAC input

11/2 RDAC 1/2 RDAC

C38R30

69.8K

P2EN_PSV

1

C60.1 μF

C280.1uF

C2922 nF

R235.11K

R105.11K

R52 31K6

C3710 nF

t ON

+

C1068 μF

C27open

R1510K

lxb

st

SOFT

U1

SiC401/2/3

FB1

FBL5

VDD

3

AG

ND

30V

OU

T

2

VIN

6

SOFT7

BS

T8

VIN

9

VIN

10

VIN

11

NC

14

LX23

NC

12

PG

ND

22P

GN

D

21

LX25

LX24

PG

ND

20P

GN

D

19P

GN

D

18

PGND17

PGND

16PGND

15

EN

L32

TON31

AG

ND

35

EN

/PS

V29

LXB

ST

13

ILIM27

PGD26

LXS28

LX33

VIN

34

AG

ND

4

VDD

L1

R9 *

C19

C24

R7 0R

C25open

LX

R6 100K

P3

Step_I_Sense

1

C14

0.1 μF

Vo

C422 μF

C322 μF

C15+

C18

BS

T

VDD

+

+

C17

C110.1 μF

C130.01 μF

J5probe test pin

12

5

3 4

P1VDD

1

R1300K

R2100K

VDD

P4

LDTRG

1

R39 0R

ENL

PGD

FBILIM

R1257.6K

VIN

R2910K

FBL

R513R3

C36560 pF

B3 Vo

1

EN

_PS

V

P5

VCTL

1

C50.1 μF

R13 100

R14 100

C3068 pF

C264.7 μF

C222 μF

R5100K

C70.1 μF

C122 μF

Q1Si4812BDY

R4 1R01

C21

VOUT

R8 10K

P7PGOOD

1

B4 VO_GND

1

P8VIN

1

P6ENL

1

P10VOUT

1

P11VO_GND

1P9VIN_GND

1

RTOP

RBOT

+

C2068 μF

+

C22B1VIN

1

B2

VIN_GND

1+ C16

R53

150 μFC12








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Fig. 3 - Operation at “Zero RDAC Current Point”

In Fig. 3 it can be observed that the SiC40X control loop will maintain the reference voltage, V2, at “FB, pin 1” under normal operation. It can be assumed then that the current in R23, RBOT, will always be 117 μA. It can be further observed using Kirchhoff’s Current Law that the sum of the currents at node 4 from RDAC and RTOP must be equal to the current in RBOT. The case shown in Fig. 3 is the “zero RDAC current point” from the calculator in Fig. 1, where the voltage at probe 4, node 8 is equal to the voltage at probe 2, node 4. At this operating point, all current to RBOT has to be supplied by RTOP. The DAC has no effect on VOUT. Thus: VOUT = 0.6 x (1 + R10/R23) + VRIPPLE/2 (see SiC40X datasheets for further information).

Now let’s examine lowering the voltage at probe 4, VDAC.

Fig. 4 - Operation at VDAC Lower than VREF

Probe 5

R235110 Ω

R1027 764 Ω

R3

14 613 Ω

V14 V

V20.6 V

V30.6 V

RTOP

RDAC

RBOTVREF in SC402A

DAC simulation DC simulation of SC402A

V46 V

AGND, pins 4, 30, 35

GND

9

16

3

8

VOUT (pin 10) 5

FB, (pin 1)4

GND

Probe 4 Probe 2

Probe 1

Probe 3

VDC: 3.8600 VIDC: 117.42 μA

VDC: 600 mVIDC: -101 pA

VDC: 600 mVIDC: -103 pA

VDC: 600 mVIDC: 117.42 μA

VDC: 600 mVIDC:

R235110 Ω

R1027 764 Ω

R3

14613 Ω

V14 V

V20.6 V

V30.13157 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V


GND

9

16

3

8

VOUT (pin 10) 5

FB, (pin 1)4

GND

Probe5

VDC: 4.7500 VIDC: 149.47 μA

DAC simulation

Probe 2Probe 4 Probe 5

Probe 1

Probe 3

VDC: 132 mVIDC: -32.1 μA



VDC: 600 mVIDC:

DC simulation of SC402A








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As the DAC voltage is changed below the reference voltage (VREF at node 6 in Fig. 4), the current through RDAC, R3, goes negative. To make up for current being drawn out of node 4, the output voltage has had to rise so that there is more current from RTOP to make up for the current drawn out through RDAC, as can be observed in probes 2, 4, and 3. Notice that the voltage across RBOT, R23, is still 0.6 V, thus the current in R23 is constant at 117 μA.

The next step is to raise the voltage at probe 4, VDAC.

Fig. 5 - Operation at VDAC Higher than VREF

Fig. 5 simulates a rise in the DAC voltage above VREF, node 6, and the current through RDAC, R3, has gone positive. To make up for this current being forced into node 4, the output voltage has had to fall so that current has to be pulled out of node 4 through RTOP to make up for the current being sourced through RDAC, as can be observed in probes 2, 3, and 4. Notice that the voltage across RBOT, R23, is still 0.6 V, thus the current is constant at 117 μA. In this case VOUT from the SiC40X is actually below VREF, V2.

CONTROL LIMITS OF VOUT

There is a sacrifice in performance that is made though when VOUT goes too far below VREF and the current from RDAC becomes positive; as this current forces VOUT lower, the effective open loop gain of the regulator declines. Put simply, the output voltage regulation gets worse. This is due to the inability of the SiC40X control system to work close to a zero duty cycle and its circuitry to operate near to or at zero volts.

The values shown in the circuit in Fig. 5 were used in the reference board in Fig. 2, which was constructed and tested for output voltage regulation at three operating points: 5 V (Fig. 6), 0.25 V, and the “zero RDAC current point” of 3.9 V with a fixed 12 V input to demonstrate this point.

Probe 5

R235110 Ω

R1027 764 Ω

R3

14 613 Ω

V14 V

V20.6 V

V32.3684 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V


GND

9

16

3

8

VOUT (pin 10) 5

FB, (pin 1)4

GND

DAC simulation DC simulation of SC402AVDC: 500.09 mVIDC: -3.5984 μA

VDC: 2.37 VIDC: 121 μA

VDC: 600 mVIDC: 121 μA


VDC: 600 mVIDC:

Probe 4 Probe 2

Probe 1

Probe 3








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Fig. 6 - 5 V Output Load Regulation

Fig. 7 - 3.9 V Output Load Regulation

Fig. 8 - 0.25 V Output Load Regulation

5.089

5.087

5.085

5.081

5.0795.078

5.0775.0775.076

5.0755.074

5.076

5.078

5.080

5.082

5.084

5.086

5.088

5.090

0

SiC

40X

Out

put

(V)

Load Current (A)54321

VOUT

dV = 14 mVdI = 4.5 ALoadline = 3.1 mΩ

3.913

3.911

3.905

3.9033.902

3.9013.9013.900

3.8993.898

3.900

3.902

3.904

3.906

3.908

3.910

3.912

3.914

0 54321

VOUT3.908

SiC

40X

Out

put

(V)

Load Current (A)

dV = 14 mVdI = 4.5 ALoadline = 3.1 mΩ

0.2877

0.2395

0.2249

0.21530.2080

0.20250.1982

0.19180.18

0.20

0.22

0.24

0.26

0.28

0.30

0 54321

VOUT

0.1918

SiC

40X

Out

put

(V)

Load Current (A)

dV = 95.9 mVdI = 4.5 ALoadline = 21.3 mΩ








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There is no difference in the regulation of the 5 V and 3.9 V outputs, but the 0.25 V output regulation is substantially worse, as expected. Practical limits for wide output range designs are from 1.5 V to 5 V for reasonable output regulation. See circuit 3 as an example.

Key point: Optimal performance occurs with VOUT at levels from 1.5 V to 5 V.

ADDITIONAL DESIGN CONSIDERATIONSBesides the obvious error terms of resistor and VREF tolerance (see “How to Obtain Exacting Resistor Values”), there are a number of other issues that can affect the output voltage tolerance. Let’s look at the boundary conditions of the control system.

Fig. 9 - DAC Limitation at Zero Volt Output

If VDAC is brought to zero volts, as in Fig. 9, VDAC, probe 4 is at 57.8 mV, not zero. That is due to the inability of most DACs to actually get to zero volts, even “rail-to-rail” designs.

Key point: these designs are based on an “ideal” voltage source.

Allowances may need to be made for deviations from the ideal.

Probe 5

R235110 Ω

R1027 764 Ω

R3

14 613 Ω

V14 V

V20.6 V

V30 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V


GND

9

16

3

8

VOUT (pin 10) 5

FB (pin 1)4

GND

VDC: 4.8901 VIDC: 154.52 μA


VDC: 57.8 mVIDC: -37.1 μA



VDC: 600 mVIDC:

Probe 2Probe 4

Probe 1

Probe 3








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Fig. 10 - Addition of Negative Rail to DAC Buffer

In Fig. 10 a negative voltage, V5, is added to the DAC circuit and now the output of the DAC simulation at node 8 actually goes to zero volts and the regulator output voltage matches that of the calculator spreadsheet. A DAC with a buffer can have a negative supply to allow VDAC to go to zero.

Key point: watch for non-linearity in the DAC (voltage source), both at the lower and upper ends of its output range.

Fig. 11 - Simulation Showing Effect of Input Bias Currents

R235110 Ω

R1027 764 Ω

R3

14 613 Ω

V14 V

V20.6 V

V30 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V


GND

9

16

3

8

VOUT (pin 10) 5

FB (pin 1)4

V5

0.6 V

2

GND


Probe 2

Probe 3

Probe 1

Probe 4 Probe 5

VDC: 600 mVIDC:



VDC: -667 nVIDC: -41.1 μA

VDC: 4.9999 VIDC: 158.48 μA

R235110 Ω

R1027 764 Ω

R3

14 613 Ω

V14 V

V20.6 V

V30 V

RTOP

RDAC

RBOTVREF in SC402A


V46 V


GND

9

16

3

8

VOUT (pin 10) 5

FB (pin 1)

V5

0.6 V

2

R1500 kΩ

GND

4

Probe1

VDC: 600.00 mV IDC: 117.42 μA

Probe 2

VDC: 600 mV IDC: -41.1 μA

Probe 4

VDC: -667 nV IDC: -41.1 μA

Probe 3

VDC: 5.0333 V IDC: 159.68 μA

Probe5

VDC: 600 mV IDC: 1.20 uA








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If there is an input current required on the “FB, (pin 1),” then this current will subtract from RBOT, R23. In the simulation in Fig. 11, R1, a 500 k resistor, was added from “FB, (pin 1)” to ground. This requires that an additional 1.2 μA be supplied by RTOP so the output voltage, observed at probe 3, rises by 33 mV to add the required current to keep node 4 at 0.6 V.

Key point: watch for input offset currents.

Fig. 12 - Effect on VOUT Setting Due to Influence of Ripple

Referring to Fig. 12, let us look at the effects of ripple on VOUT. Since most switching regulators have some output ripple, one has to consider that this is a noise component whose average value can affect the feedback of the regulator.

Referring back to Fig. 5, it can be seen that when we set the DAC voltage in our simulation of this design to 2.3684 V (shown as 2.37 V at probe 4), we get an output of 500.09 mV.

If we then add a 20 mV peak-to-peak 500 kHz “ripple” to the output and R1 (as shown in Fig. 11) is removed so that the offset current will not influence the result, we can observe the effect of the injected ripple signal.

The output voltage has dropped about 2 mV, demonstrating that ripple and noise can affect VOUT also. In an actual application where the bandwidth of the control loop is less than the op-amps in the simulation model, the effect will be greater; typical values are 5 mV to 10 mV.

CALCULATORThe calculator requires that users know five different parameters:

1. VREF

2. RBOT

3. SiC40X output voltage range (the minimum voltage and the maximum voltage)

4. The maximum output voltage of the DAC

5. The number of DAC bits

All other parameters are calculated for users.

There is a section that is useful for programmers that allows the translation of DAC counts in decimal and hex format to VOUTand VDAC.

R235110 Ω

R1027 764 Ω

R3

14 613 Ω

V14 V

V20.6 V

V32.3694 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V


GND

9

16

3

8

VOUT (pin 10)

FB (pin 1)

V5

0.6 V

2

V60.02 V to 0 V500 kHz

7

5

4

GND

Probe 1


Probe 2

Probe 3

Probe 4 Probe 5

VDC: 498.30 mVIDC: -3.6677 μA

VDC: 2.37 VIDC: 121 μA


VDC: 600 mVIDC: -14.2 pA

VDC: 600.16 mVIDC: 117.45 μA








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EXAMPLE DESIGNS

Circuit 1: AVS Design

This is a circuit that would be useful to most AVS and margining applications that are in the 1 V region. Fig. 13 shows the results from the spreadsheet design tool.

Fig. 13 - Design Tool Calculations for Circuit 1

Fig. 14 - Simulation Schematic (Refer to Fig. 2 for Actual Schematic)


VREF (V)


(ratio)

Determinezero RDAC

current pointfor VOUT

(VDAC = VREF)(V)

RDAC /2 (Ω)

2.5 3.45110 0.000489237

Step

DAC LSB

(V)

1 DAC LSBadjust in

SiC4XX VOUT(V)

-0.12 3.1 1226.4 10 220 5110

2.5 0.000610352 7.32422-5 409612

3.1

2: Input DAC or voltage source parameters

RBOT (R23above)

(Ω) IRBOT(A)

SiC4XX VOUTmax. (V)

SiC4XX VOUT min.(V)

DAC max.VOUT(V)

DAC bits (number)

Total count(theoretical

number of voltage steps)

(number)

CalculatedRTOP(Ω)

CalculatedRDAC(Ω)

R235110 Ω

R103850 Ω

R100

48 119 Ω

V35 V

V20.6 V

6

V12.5 V

RTOPRDAC

RBOT

VREF in SC402A

9

V413 V

31

8FB pin 1

5


GND

VOUT (test point P10)

V5

0.6 V

V6

0 V

27

GND

4

Probe 1

Probe 2

Probe 3Probe 4Probe 5


VDC: 2.50 VIDC: 39.5 μA



VDC: 600 mVIDC: -819 nA









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Shaping VOUT Response

Fig. 2 shows how RDAC has been cut in half so that there are two resistors, R53 and R54, allowing a capacitor to be added in between them. This capacitor will shape the response of VOUT to a transition command from the VDAC.

If the response time, tr, is set at five time constants so it is close to 20 μs, this will result in the best response time of the regulator. This time can be determined from:

tr = 1/(fsw x 0.1) and tr = (Rtotal) x C38 x 5,

where: for fsw = 500 kHz, then:

1/(0.1 x 500 000) = 20 x 10-6 s, or 20 μs. Divide by five and something close to 5 μs is required.

Since R54 has been set equal to R53, then = 0.5 x R53 or 12 k. Thus:

12 k x 470 pF = 5.64 μs x 5 is 28.2 μs. 470 pF was chosen as it is a standard value.

In a simulator it looks like this, where the reference values (R54, C38, and R53) refer to Fig. 2:

Fig. 15 - Transient Simulation Circuit

These are the simulation results.

Fig. 16 - Transient Step Simulation Result(Note: V1 and V2 Refer to the Voltages at the Nodes 1 and 2, not to the Sources V1 and V2)

Rtotal = R54 R53

R54 R53

C38

470 pF

R54

24 kΩ

R53

24 kΩ V1

0.6 V

V3

0 V to 2.50 V 0.5 ms to 10 ms

13

VREF

1/2 RDAC

VDAC

0

2

1/2 RDAC

2.6

0

2.2

1.7

1.2

0.7770

0.3096

-0.6252

-0.1578

19.96

Volta

ge (V

)

20.0620.0420.0220.0019.98Time (ms)

(20.0282, 2.5000)

(20.0000, 0.0000)

1 2Transient analysis

V(1)

V(2)

V(1)








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Here is what the output voltage transition of the regulator looks like (showing a 10 % to 90 % rise time):

Fig. 17 - VOUT Transition at no Load

Referring to Fig. 2, channel 1 is a regulator VOUT at P10 (yellow) with 1 V offset, channel 2 is VDAC, and channel 3 is the LX node at J5. Conditions are no load on VOUT, 12 V input.

Here is the same transition but with a 6 A load (all scope settings the same as Fig. 17):

Fig. 18 - VOUT Transition at 6 A Load

Key point: loading does not substantially affect the VOUT transition speed.








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Transient Response of Circuit 1

Again, referring to Fig. 2, let us look at how the COT architecture of the SiC40X results in a fast response to both load and VDACcommands.

Fig. 19 - Increasing Transient Load with Static DAC Setting

Fig. 20 - Load Release with Static DAC Setting

Whenever two parameters change at one time, there might be unwanted effects. Let us look at what happens when both VOUTand load current are changed together.








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Fig. 21 - Increasing Load from 2 A to 6 A, VOUT Increase from 0.95 V to 1.05 V Driven by a DAC

Let us examine the extremes; where VDAC is driven from a function generator so that the VDAC transition is 30 ns.

Fig. 22 - IOUT Changes from 6 A to 2 A while VOUT is Adjusted from 1.1 V to 0.96 V








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Excellent transient performance is observed even under the worst case conditions due to the COT architecture of the SiC403A.

DC Load Regulation of Circuit 1

Fig. 26 - 0.9 V Load Regulation

0.904

0.905

0.906

0.907

0.908

0.909

0.910

0

SiC

40X

Out

put

(V)

Load Current (A)74321

0.9 VOUT

5 6

dV = 14 mVdI = 6.0 ALoadline = 683 μΩ








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Fig. 27 - 1.1 V Load Regulation

Circuit 2: Using a Tri-State Buffer for a Voltage Margining Circuit

With a slight modification to circuit 1, a tri-state buffer can be used in place of the DAC as a three-output voltage source; VOUT is selected by the state of the buffer. For purposes of the calculator, the buffer is a “0” bit DAC.

Fig. 28 - Tri-State Voltage Margining Circuit Calculation Result

If the buffer’s output is active and is set to logic low, then there will be a 1.1 V output. If it is set at logic high, there will be a 1.1 V output. If at tri-state (not active), the VOUT will be at the “zero RDAC current point,” or 1.03 V output. Any tri-state output could be used from an ASIC, FPGA, etc.

1.100

1.102

1.104

1.106

1.108

1.110

0 74321

1.1 VOUT

5 6

SiC

40X

Out

put

(V)

Load Current (A)

dV = 3 mVdI = 6.0 ALoadline = 500 μΩ


RDAC /2

(Ω)

0.6

1.8 0 1.8 0.2 1

5110 0.000117 1.1 0.9 -0.1111111 1.03333333 3691 33 215 16 608

Step 2: Input DAC or voltage source parameters


number of voltage steps)

(number)

1 DAC LSBadjust in

SiC4XX VOUT(V)

DAC LSB(V)

DAC max.VOUT(V)

DAC bits (number)

VREF (V)

RBOT (R23above)

(Ω) IRBOT(A)

SiC4XX VOUTmax. (V)

SiC4XX VOUT min.(V)


(ratio)

Determinezero RDAC

current pointfor VOUT

(VDAC = VREF)(V)

CalculatedRTOP(Ω)

CalculatedRDAC(Ω)








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Here are the simulations:

Fig. 29 - Tri-State Example with U3 at Tri-State

Fig. 30 - Tri-State Example with Tri-State not Active and Logic Output at Zero Volts

R235110 Ω

R103691 Ω

R54

16 608 Ω

V20.6 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V

FB pin 1

VOUT (P10)


GND

7

3

11

U3NC7SZ126_2V

VCC

1.8 V

V10 V 1.8 V 0.5 ms 1 ms

2

9 R53

16 608 Ω

C1220 pF

4 1

GND

VDC: 1.0324 VIDC: 117.32 μA

Probe 1

Probe 2

Probe 3

Probe 4 Probe 5

VDC: 599 mVIDC: 3.99 nAVDC: 600 mV

IDC: 4.00 nA

VDC: 599.44 mVIDC: 117.31 μA

VDC: 599.44 mVIDC: -17.903 pA

DC simulation of SC402ATri-state simulation

R235110 Ω

R103691 Ω

R54

16 608 Ω

V20.6 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V

FB pin 1

VOUT (P10)


GND

7

3

11

U3NC7SZ126_2V

VCC

1.8 V

9 R53

16 608 Ω

C1220 pF

14

VCC

GND

VDC: 1.1001 VIDC: 135.48 μA

Probe 1

Probe 2

Probe 3

Probe 4 Probe 5

DC simulation of SC402ATri-state simulation

VDC: 18.1 μVIDC: -18.1 μA VDC: 600 mV

IDC: -18.1 μA










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Fig. 31 - Tri-State Example with Tri-State not Active and Logic Output at 2 V

In Fig. 31 the simulation shows a VOUT of 0.877 V rather than the 0.9 V designed for. This is due to an artifact of the simulation, as the model for the buffer assumes a 2 V power rail as opposed to the intended 1.8 V rail.

Circuit 3: Wide Range Output

This is a wide range output example. It would be useful for a designer that needs to set the rail for output buffers at different voltages such as 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V.

Fig. 32 - Circuit 3 Calculator Result

R235110 Ω

R103691 Ω

R54

16 608 Ω

V20.6 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V

FB pin 1

VOUT (P10)


GND

7

3

11

U3NC7SZ126_2V

VCC

1.8 V

9 R53

16 608 Ω

C1220 pF

14

GND

VCC

Probe 1

Probe 2

Probe 3

Probe 4 Probe 5

DC simulation of SC402ATri-state simulationVDC: 877.82 mVIDC: 75.270 μA


VDC: 2.00 VIDC: 42.1 μA





(ratio)

Determinezero RDAC

current point for VOUT

(VDAC = VREF)(V)

RDAC/2 (Ω)

0.6 5110 0.000117 5.25 1.45 -1.52 4.338 31835 20944 10472

Step 2: Input DAC or voltage source parameters

DAC max.VOUT(V)

DAC bits(number)

DAC LSB(V)

1 DAC LSBadjust in

SiC4XX VOUT(V)


number of voltagesteps from DAC)

(number)

2.5 10 0.002441 0.003710938 1024

VREF (V)

RBOT (R23above)

(Ω) IRBOT(A)

SiC4XX VOUTmax. (V)

SiC4XX VOUT min.(V)

CalculatedRTOP(Ω)

CalculatedRDAC(Ω)








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Fig. 33 - 1.5 V to 5.25 V Simulation

The calculator can be used to determine what the register settings are for the DAC. In this case, a 10-bit DAC allows a 3.7 mV per LSB adjustment of VOUT.

Using the programmer’s tool, the desired VOUT values can be entered and the proper register values can be determined:

Fig. 34 - Determining Register Settings for the DAC

Using the same circuit as above, a power rail for a bridge-based sensor can also be set up. In this case bits would be added to the DAC based on calibration needs.

Fig. 35 - More DAC Bits Yields Increased Resolution in VOUT Adjustability

In this circuit regulation is 1.480 V at 0 A and 1.459 V at 6 A; 5.309 V at 0 A and 5.288 V at 6 A.

R235110 Ω

R1031 835 Ω

R54

10 472 Ω

V20.6 V

RTOP

RDAC

RBOTVREF in SC402A

V46 V

FB pin 1

VOUT (P10)


GND

7

3

11

R53

10 472 Ω

C11000 pF

14

V14 V

V32.5 V

V5

0.6 V

9

62

GND

8

VDC: 1.4500 VIDC: 26.699 μA

Probe 1

Probe 2

Probe 3

Probe 4 Probe 5

DC simulation of SC402ADAC simulation


VDC: 2.50 VIDC: 90.7 μA



Convertregulatoroutput voltage to DAC count

RegulatorVOUT

2.5 741

Count Hex

2E5

Input DAC or voltage source parameters

DACbits(number)

DAC LSB(V)

1 DAC LSB adjust in

SiC4XX VOUT(V)

Total count(theoreticalnumber of voltage steps from DAC)(number)

14 0.000153 0.000231934 16384








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How to Obtain Exacting Resistor Values

In each of these designs it is critical that the resistor values for RTOP, RBOT, and RDAC be quite precise. The ohmic value requirements of these resistors can vary greatly over the design possibilities. 0.1 % resistors may not meet the designer’s requirements.

In these instances, there is a useful tool by which a parallel or series combination of 1 % resistors can be determined that will meet the design goal.

It is located at jansson.us/resistors.html.

Here is an example of the calculation of RTOP, R10, from circuit 3 in Fig. 33, using the URL above:

Fig. 36 - Precision Resistor Calculator

In this case RTOP would consist of a 33 k, 1 % resistor in parallel with an 820 k, 1 % resistor. If both resistors were exactly at their stated values, the final parallel value would be off by -0.35 %.

There are also highly precise 0.01 % resistors with very low temperature coefficients that come in non-standard values and are made to order, such as the PLT series from Vishay (see www.vishay.com/doc?60030).

THE PROTOTYPE

Fig. 37 - Prototype Photograph

DAC

RTOP

Reference board

RDAC andC38 area

Alternate SiC403A demoboard



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