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Wind River SystemsTornado Device Driver Workshop © Copyright Wind River Systems E-1

Appendix

E

VME Basics

• Introduction to the VMEbus

• Accessing boards across the VMEbus

• VMEbus interrupt handling


VME Basics

8.6 VMEbus Addressing

VMEbus Interrupts

• VMEbus address spaces (Address Modifiers)

• CPU memory maps

• Converting a VMEbus address to a local address

• Creating a virtual to physical map to access (unmapped) VMEbus

address


VMEbus Terminology

Master A board which can initiate data transfer

Slave A board which responds to requestsgenerated by a master

Arbiter A board that grants masters control ofthe bus

• Only the system controller in the first slot can be thearbiter.

• Most I/O boards are slaves.

• Some I/O boards are masters. Most masters are also

slaves.

• VMEbus is called a “multimaster bus,” since multiple boards may

initiate data transfers.

• Whether a board can be a master, slave, or arbiter is hardware

determined.

The Matrix DAADIO is an example of a slave. CPU cards are typically masters and slaves. I/O boards withmicroprocessors on-board may be masters. The Matrix MS-SCSIFD (SCSI & floppy controller) is an example of anI/O master.Since most I/O boards are slaves only, the driver writer needs to know how the master (CPU card)accesses the I/O board, but does not have to concern themselves with the I/O board accessing the master (since itonly responds to the master’s requests). If the I/O board is also a master, then the driver needs to be aware howaccess can be made in both directions.Note that while most masters are slaves, not all slaves are masters.


VME Backplane

The VMEbus is designed for flexibility to accommodatevarying needs:

P1/J1 24 bit addressing, 16 bit data, pluscontrol lines

P2/J2 Expands capability to 32 bit addressingand 32 bit data

VME Chassis

P1

P2backplaneconnectors

• The most common cards are double height (6U), which connect into

both P1 and P2.

• Single height (3U) cards are also common.

• Do NOT leave empty slots between boards (unless the backplane is

correctly jumpered for it).

The Matrix DAADIO is an example of a slave. CPU cards are typically masters and slaves. I/O boards withmicroprocessors on-board may be masters. The Matrix MS-SCSIFD (SCSI & floppy controller) is an example of anI/O master.Since most I/O boards are slaves only, the driver writer needs to know how the master (CPU card)accesses the I/O board, but does not have to concern themselves with the I/O board accessing the master (since itonly responds to the master’s requests). If the I/O board is also a master, then the driver needs to be aware howaccess can be made in both directions. Note that while most masters are slaves, not all slaves are masters.


VMEbus Address Spaces

Name AddressLength Size

Short I/O(A16) 16-bit 64 Kbytes

Standard(A24) 24-bit 16 Mbytes

Extended(A32) 32-bit 4 Gbytes

The VMEbus was designed with these different addressing modes to permit a wide range of applications: lessdemanding applications can use Short I/O (A16) addressing which requires less hardware (e.g. address decodinglogic) while more complex applications can use the full 32-bit addressing.


Typical CPU Board Memory Map

0

0xffffffff

0xffff0000

0xfe000000

Short I/O

St

Extended

LocalDevices

Local RAM0x00400000

0xff000000

• The addresses and ordering will differ between boards.

• Note that picture above is not to scale. Short I/O space (64K) is less than

4/1000 of the 32-bit address space.

The map above shows an 1 Mbyte local RAM, 3 Gbytes 991 Mbytes extended space, 16 Mbytes standard space, 15Mbytes 1008 Kbytes for local devices, and 64 Kbytes for short I/O.


Map To VMEbus Address Space

Short I/O

Standard

Extended

Short I/O

Standard

Extended

VMEbus Address SpaceMemory Map

• The diagram above is an example. Your board will differ.

• It is common for a CPU to have non-contiguous regions that map to

VMEbus extended address space.

• Typically, all of VME short I/O and standard address space is accessible.

• Only a subset of VME extended address space is accessible.


Address Modifiers

Address modifiers specify the VMEbus address space.

/ 32

/ 32

/ 6

Address Lines

Data Lines

Address Modifier

CPU I/O

• Boards typically have jumpers to specify where registers or memory

reside in a given address space. For example, if a board has one Mbyte

of memory in standard space, it will typically have jumpers to select

where in the 16 Mbyte Standard address space it is mapped.


Address Modifiers

• Privilege Level

● Supervisor

● Supervisor or User

• Type of access

● Data

● Program

● Block Transfer

• Address Size

● Extended

● Standard

● Short I/O

• For VxWorks privilege level is irrelevant, since VxWorks runs in

supervisor mode.

• Typically, I/O boards select Privilege Level with jumpers.

• Not all combinations above are used.

• Symbolic constants for Address Modifiers are defined in wind/target/h/vme.h.

“Program” is text or code. “Block transfer” (sometimes called “burst mode”) allows transferring up to 256 bytes withonly one address cycle (like DMA).


Accessing a Board on the VMEbus

• You must know:

● The address modifier to which the board responds

● The addresses to which it responds

● The CPU address mapping

• Example:

● Address Modifier is VME_AM_SUP_SHORT_IO (ShortI/0 supervisor)

● Address is 0x100

● CPU maps Short I/O space to 0xffff0000.

• What address would be used on the CPU to access the board described

above?

The address to use would be 0xffff0100 (0xffff0000 + 0x100).In this example, the address put on the bus is 0x100 (address lines A01-A15). The most significant 16-bits (0xffff) isused to indicate to the CPU that this is a VMEbus address and the address modifier should be set to 0x2d (AM0-AM5).


Converting a VMEbus Address

STATUS sysBusToLocalAdrs (addrSpace,busAddr, pLocalAddr)

addrSpace The VMEbus address modifier

busAddr The VMEbus address to be accessed

pLocalAddr A pointer to store the convertedaddress

• Returns OK on success, else ERROR.

• To enhance portability, use this routine in lieu of hard-

coding the local address.

• Typically, called once in driver initialization routine.

• Use the symbolic constants defined in wind/target/h/vme.h for the

addrSpace parameter.

• Example:

#include "vxWorks.h"#include "vme.h"...char * pBoard;...if (sysBusToLocalAdrs (VME_AM_SUP_SHORT_IO, (char *)0x100,

&pBoard) == ERROR)return (ERROR);

Assuming that your board only uses one address space, the routine above need only be called once. This may not beobvious to all students.


Probing A Bus Address

STATUS vxMemProbe (addr, mode, len, pVal)

addr Address to test.

mode Test for reading, VX_READ(0), or writingVX_WRITE (1).

len Length in bytes to probe--must be 1, 2, or4.

pVal Address of data to write (VX_WRITE) oraddress to store value read (VX_READ).

• Traps bus errors.

• Useful in initialization code when unsure of location of

hardware.

• Include vxLib.h.


Boards with MMUs

0

0xffffffff

0xffff0000

0xfe000000

0x00400000

0xff000000

VMEbusShort I/O➠LocalDevices

VMEbusStandard

➠

➠

➠

➠

VMEbus

Local RAM

Extended

0

0xffffffff

0xffff0000

0xfe000000

0x00400000

0xff000000

➠➠

➠

➠

➠

PH

YS

ICA

L

VIR

TU

AL

not mapped

0x01400000

• By default, boards with Memory Mapping Units map virtual to physical

addresses one-to-one.

• Not all virtual addresses are mapped.

• As in the example above, BSP’s typically map all of VMEbus short I/Oand standard addresses, but do not map all the extended addresses.

• This is in addition to the earlier limitation already discussed:

● In the example above, most of the 4Gb VMEbus Extended space(0x00400000 to 0xfe000000) is “mapped” by the address decode logicon the CPU board.

● Of these addresses only a subset have virtual address mapping(0x00400000 to 0x01400000).

• To access an unmapped VMEbus extended address requires adding amapping.


Mapping VMEbus Addresses

• This is only an issue for boards with MMU’s that do not

map addresses needed by an application.

• Writing to an unmapped address causes a bus error.

• To map an (unmapped) VMEbus address:

❍ Convert the bus address to a local address — usingsysBusToLocalAdrs( ).

❍ Create a virtual address mapping for these addresses— using one of two methods which will bedescribed:

● Modify sysLib.c● Use VxVMI routines

• VxVMI is an optional product.

• There may be architecture-dependent constraints on how much

memory may be mapped. For example, the MC68K requires 512 bytes

for each megabyte mapped (to store translation table information)


Method 1: Modifying sysLib.c

• Modify the sysPhysMemDesc initialized in sysLib.c.

• It is as an array of PHYS_MEM_DESC structures:

virtualAddr Starting virtual address

physicalAddr Starting physical address

len Number of bytes to map

initialStateMask Initial state mask, e.g.:VM_STATE_MASK_VALIDVM_STATE_MASK_WRITABLEVM_STATE_MASK_CACHEABLE

initialState Initial state, e.g.:VM_STATE_VALID / VM_STATE_VALID_NOTVM_STATE_WRITABLE / VM_STATE_WRITABLE_NOTVM_STATE_CACHEABLE /VM_STATE_CACHEABLE_NOT

• The virtualAddr and physicalAddr must be on page boundaries. The lenmust be a multiple of page size. To get page size, use

vmBasePageSizeGet ( ) or vmPageSizeGet ( ).

• The state and state mask values above are generic, architecture

independent. Different architectures may have provided additional,

architecture dependent, states.

• The state mask is a generic tool to allow modifying a state flag without

knowing the current state values. It must be provided here for

consistency purposes.

• The sysPhysMemDesc may be modified by:

● Changing an existing PHYS_MEM_DESC element

● Adding one or more PHYS_MEM_DESC elements


Modifying Mapping Example1 PHYS_MEM_DESC sysPhysMemDesc [] = {

...2 { /* some A32 vme */3 (void *) 0x1000000, /* address 0 */ ❶4 (void *) 0x1000000, ❷5 0x1000000 0x2000000 /* 16 32 Mbytes */ ❸6 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |

VM_STATE_MASK_CACHEABLE, ❹7 VM_STATE_VALID | VM_STATE_WRITABLE |

VM_STATE_CACHEABLE_NOT➎8 },

...9 { /* add some A32 vme */10 (void *) 0x8000000, ❶11 (void *) 0x8000000, ❷12 0x1000000, /* 16 Mbytes */ ❸13 VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |

VM_STATE_MASK_CACHEABLE,❹14 VM_STATE_VALID | VM_STATE_WRITABLE |

VM_STATE_CACHEABLE_NOT➎15 }, ...

The example above shows how to modify sysPhysMemDesc by:

● Modifying an existing PHYS_MEM_DESC element (in this case, byincreasing the size of the existing extended (A32) address space from16 to 32Mb.), or

● Adding a new PHYS_MEM_DESC element (in this case, to mapadditional, non-contiguous VMEbus extended addresses).

❶ Starting virtual address to map

❷ Starting physical address to map

❸ Size in bytes

❹ State mask

➎ Initial state. Note that the VMEbus addresses are set toVM_STATE_CACHEABLE_NOT.


Method 2: Mapping AddressesUsing VxVMI

• Allows building application initialization code to mapaddresses without having to modify sysLib.c.

• First map the memory:

STATUS vmGlobalMap (virtualAddr,physicalAddr, len)

● Call before creating any virtual memory contexts.

● Address and length must be on page boundaries.

• Next call:

STATUS vmStateSet (NULL, virtualAddr, len,stateMask, state)

• Requires optional VxVMI product.

• The NULL argument in vmStateSet( ) indicates that the current virtual

context is to be used.

• The values and meaning for stateMask and state are identical to those

previously described for modifying sysPhysMemDesc.

• Must define INCLUDE_MMU_FULL in config.h in the target directory.


VME Basics

VMEbus Addressing

8.7 VMEbus Interrupts

• VMEbus interrupt acknowledge cycle

• Enabling a CPU board to respond to VMEbus interrupts

• Managing multiple I/O boards

• Vectored interrupts and autovectored interrupts


Interrupts and Priorities

Interrupt

Interrupt

Interrupt

.

..

Task

Task

Task

.

..

Execution Order Controlled

Ab

solu

te S

yste

m-W

ide

Prio

rity

Execution Order Controlled

Task Priority

Interrupt Level

(Programmable)

(Hard Wired)

by Hardware

by Kernel

• Interrupts preempt even highest priority task.


Interrupt Terminology

• Interrupt Level

● Seven VMEbus levels available: IRQ1 - IRQ7

● IRQ7 is the highest priority

● Only one CPU can respond to a given IRQ

• Interrupt Number

● 256 available (Motorola)

● Index into the interrupt vector table

• Interrupt Vector

● The byte offset of an entry in the interrupt vectortable

• Any board (with the appropriate hardware) can generate interrupts

(does not have to be a master).

• The interrupt number is selected by programming (or setting jumpers)

on the interrupting board.

• The usage “interrupt number” and “interrupt vector” are WRS specific.

In the industry, interrupt vector typically refers to the index into the

interrupt table.


VMEbus Interrupts

IRQ1 - IRQ7

CPU I/O

• To generate an interrupt, the I/O board asserts one of the seven

interrupt lines. The line it asserts is the interrupt level.

• The CPU board recognizes the assertion of the interrupt line (if enabled)

and begins the interrupt acknowledge cycle.

The enabling of interrupts is done by sysIntEnable() -- some (usually older) boards can not enable interrupts throughsoftware but require the setting of jumpers.Only one board should be programmed to handle a given interrupt level. With multiple CPUs and I/O boards on thesame backplane, different I/O boards can generate different interrupt levels which could then be handled bydifferent CPUs.


VMEbus Interrupts

IACK

A01-A03

CPU I/O

• The acknowledging CPU places the interrupt level number on the lower

order address lines and asserts the Interrupt Acknowledge (IACK ) line.

• The IACK line is daisy-chained through the backplane. Starting with the

card in slot 0, each board determines if the interrupt being

acknowledged is one that it generated. If not, it passes the signal down.

If it is, the board continues the interrupt acknowledge cycle and does

not pass the signal on.

• The daisy-chaining of IACK allows multiple boards to use the same IRQ

line (only one will be acknowledged at a time).

• The interrupting board may be in a lower numbered slot then the

acknowledging CPU.


VME Interrupts

DTACK

D00-D31

CPU I/O

• The I/O card places the STATUS/ID on the data bus and asserts DTACK.

• The CPU card (typically) reads the STATUS/ID and uses it as the

interrupt number, i.e. an index into the Interrupt Vector Table.

• The Interrupt Vector Table holds the addresses of interrupt service

routines.

DTACK is used by interrupting board to terminate cycle.


VME Interrupts

• Multiple boards may generate interrupts using the

same interrupt level.

• A CPU card must be programmed to respond to the

specified interrupt level:

STATUS sysIntEnable (intLevel)

Only one CPU card can handle a given IRQ line.

• If more than one interrupt of the same level occurs at the same time, the

board closest to slot 0 will be processed first.

• Boards typically assert an IRQ line until they are acknowledged.

• If two boards assert the same IRQ:

● The responsible CPU card begins the interrupt acknowledge cycle.

● The first board serviced releases the IRQ line after acknowledgment.

● The second board still has the IRQ line asserted, so the CPU begins asecond interrupt acknowledge cycle.

● The second board serviced releases the IRQ line afteracknowledgment.


Managing Multiple Boards

Multiple I/O boards can be managed by one or moreCPU’s.

IRQ4

IRQ3

CPU#0

CPU#1

I/O#0

I/O#1

IACK

• To have separate CPU’s control multiple I/O boards:

● CPU #0 calls sysIntEnable( ) for IRQ3, but not IRQ4● CPU #1 calls sysIntEnable( ) for IRQ4, but not IRQ3● I/O #0 generates interrupts on IRQ3● I/O #1 generates interrupts on IRQ4

• One CPU may control multiple I/O boards using the same interrupt

level:

● CPU #0 calls sysIntEnable( ) for IRQ3● I/O #0 and #1 generate interrupts on IRQ3● If both boards generate interrupts at the same time, I/O #0 is serviced

first (board closest to slot 0).


Interrupt Acknowledge Cycle

• Most CPU boards perform the interrupt acknowledge

cycle automatically.

• If a CPU board does not do so, it will autovector, i.e.,

use the interrupt level as an index into the vector table

to obtain the address of an ISR.

• In the event of autovectoring, the interrupt

acknowledge cycle must be completed by executing the

following call:

int sysBusIntAck (intLevel)

which returns the STATUS/ID read from the bus.

• Boards that perform the interrupt acknowledge cycle in hardware have

a null sysBusIntAck( ) routine.


Interrupt Vector Table

01

255

.

.

.

04

1020

.

.

.

Interrupt VectorInterrupt Number

InterruptServiceRoutine (ISR)

• The size of the Interrupt Vector Table is architecture dependent.

• The table holds pointers to Interrupt Service Routines (ISRs).

• The Interrupt Vector Table is normally (but not always) located at

address 0.

• The Interrupt Vector is the address of a specific entry in the Interrupt

Vector Table.

• Use the INUM_TO_IVEC(intNumber) macro to convert interrupt

number to interrupt vector.

• The above example is for a typical Motorola 68K board.


VMEbus Interrupt Handling

• Vectored interrupts

● Most common

● STATUS/ID from interrupt acknowledge cycle isused as index into interrupt table to select ISR

• Autovectored interrupts

● Interrupt level indexes ISR entry

● Interrupt acknowledge cycle must still be completed

• For most architectures, ISRs use a separate interrupt

stack.

• The size of the interrupt stack is determined by the ISR_STACK_SIZE in

wind/target/config/all/configAll.h. The default stack size is architecture

dependent.

• ISRs for the following architectures use the current task’s stack:

Motorola CPU32

Motorola MC68000, MC68010 and MC68060

Intel 80386, 80486 and Pentium

RAD 6000

appendix e - pudn.comread.pudn.com/downloads9/.../32524/ddvme_appe.f.pdf · vme chassis p1 p2...

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