Appendix A Process Information

In this appendix SPICE model cards are given for the technologies used in chapter 6. Information on passive components is also provided. For the MOS transistors SPICE level 2 model parameters are given because this model and its extraction process are optimized for analog. More information on the different model parameters and its equations can be found in [Laker 1994]. Special attention must be given to the model parameter LAMBDA in the level 2 model. It is each time given for a transistor with a 3 {LID gate length/. For a different gate length/, LAMBDA must be recalculated according to the equations as given in [Laker 1994].

The 1.2 fLm CMOS Process

nMOS, SPICE level 2 parameters

.MODEL NA NMOS LEVEL=2 + VTO =700E-3 NSUB =3.50E16 + NFS =1.1Ell TOX =22.5E-9 + UCRIT=1.50E5 UEXP =0.15 + XJ =1E-7 CGSO =1.3E-10 + RSH =500 JS =1E-3 + FC =0.5 CJ =1.8E-4 + CJSW =2.9E-10 MJSW =0.23 + KF =1E-28 AF =1

Low VT pMOS, SPICE level 2 parameters

MODEL PLA PMOS LEVEL=2

DELTA=1.8 uo =550 LD =1.25E-7 CGDO =1.3E-10 PB =0.60 MJ =0.46 LAMBDA=7. OE-3

221

222 CMOS WIRELESS TRANSCEIVER DESIGN

+ VTO =-0.70 NSUB =1.97E16 DELTA=3.76 + NFS =4.0E10 TOX =22.5E-9 uo =195 + UCRIT=1.5E5 UEXP =0.23 LD =0.75E-7 + XJ =50E-9 CGSO =1.2E-10 CGDO =1.2E-10 + RSH =490 JS =1E-3 PB =0.60 + FC =0.5 CJ =5.1E-4 MJ =0.51 + CJSW =3.4E-10 MJSW =0.51 LAMBDA=5.0E-3 + KF =4E-30 AF =1

Passive devices

• High ohmic polysilicon resistors (HIPO) : Ro = 2 kQ/D, Matching= 0.5 %

• Polysilicon to implant capacitors : C,JX = 0.750 lF/{Lm2, Ro,hottomplute = 11.5 Q/0, Chottomplute::::::; 1/3 ·Cox

The 0. 7 f-Lm CMOS Process

nMOS, SPICE level2 parameters

.MODEL NA NMOS LEVEL=2 + VTO =750E-3 NSUB =7.0E16 + NFS =1. 2Ell TOX =17E-9 + UCRIT=1.08E5 UEXP =0.124 + DELL =0.2E-6 WD =0.12E-6 + XJ =SOE-9 CGSO =2.1E-10 + RSH =480 JS =1E-3 + FC =0.5 CJ =5.0E-4 + CJSW =2.8E-10 MJSW =0.214 + KF =1E-28 AF =1 + GAMMA=0.75 KP =95E-6 + ACM = 2 HDIF = 2e-6

Low VT pMOS, SPICE leve12 parameters

.MODEL PLA PMOS LEVEL=2 + VTO =-0.70 NSUB =3.5E16 + NFS =3.7E10 + UCRIT=1. 3E5

TOX =17E-9 UEXP =0.252

DELTA=2.0 uo =470 LD =O.lE-6 DELW =0 CGDO =2.1E-10 PB =0.65 MJ =0.33 LAMBDA=8. 5E-3 NLEV =3 PHI=0.795

DELTA=2.6 uo =173 LD =0.06E-6

APPENDIX A: PROCESS INFORMATION

+ DELL =0.15E-6 WD =0.2E-6 DELW =0 + XJ =50E-9 CGSO =1.2E-10 CGDO =1.2E-10 + RSH =900 JS =lE-3 PB =0.78 + FC =0.5 CJ =6.0E-4 MJ =0.468 + CJSW =3.6E-10 MJSW =0.302 LAMBDA=llE-3 + KF =4E-30 AF =1 NLEV =3 + GAMMA=0.53 KP =35E-6 PHI =0.760 + ACM = 2 HDIF = 2e-6

Passive devic(!s

• High ohmic polysilicon resistors (HIPO) : R0 = 2 kQ/0, Matching= 9.18/(w ·/) + 0.0073 %2

• Polysilicon to implant capacitors : Cox = 0.750 fF/ f-Lm 2 , Ro,hottomplate = 17 Q/0, Chottomplate ~ 1/3 · Cox,

Matching = 0.11 %

223

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Index

AID-converter, 17, 22, 61, 65, 74, 78, 87, 118, 127 AC simulation, 94 Active-RC, 51, 86, 197 Adjacent channel, 63, 109, 118, 124, 128, 197 Aliasing, 74, 94, 96, 138 Amplifier, 30, 78

complex, 33, 39 inductor loaded, 152 resistor loaded, 152, 181

Amplitude error, 18, 47, 51, 117, 125, 172, 181, 185,188,193

Analog signal processing, 4, 63, 216 Antenna input spectrum, 93 Antenna multiplexer, 114 Antenna signal, II, 17, 20, 71, 87-88, 92, 140, 145,

175 Anti-aliasing filter, 126 Automatic gain control, 93, 98, 118-119, 129, 181 Back-end, II, 29

transmitter, 23 Balun, 148

on-chip, 191 Bandpass filter, 17, 25, 38, 51, 79, 123, 154 Behavioral model library, I 00 Behavioral modeling, 73 BiCMOS, 4, 135,218 Bipolar,4, 135,137,151,167,206,218 Bit-error-rate, 72, 108

simulations, 117 Blocking filter, 114, 122 Building block

discription, 77 Bulk effect, 139 Capacitors, 137

Cell based, I 07 Channel fading, I 08 CMOS, 135, 166,218

deep sub-micron, 5, 136, !52, 169, 219 mixer, 138 sub-micron, 4 transceiver, 205, 211

Combined IF zero- IF receiver, 22, I 0 I Communication channel, I 0 Commutating mixer, 137 Complex amplifier, 33, 39 Complex conjugate, 31, 40, 195 Complex filter, 36

bandpass, 40 direct synthesis, 39

Complex multiplication, 33, 35 implementation, 35

Complex notation, 33 Complex pole, 40 Complex signal technique, 31 Complex signal, 32-34 Component matching, 45 Conversion gain, 84, 143, 148, 185 Convolution, 19, 33, 97 CORDIC, 17 Correlation, 24, 96 Cost, 4, 135 Crosstalk, 18-20, 66, 120, 142, 209 Current conveyor, 209 Dl A-converter, 126 D/A-convertor, 52 DC-offset, 18 DCS 1800, I 06 DCS 1900, I 06

237

238 CMOS WIRELESS TRANSCEIVER DESIGN

DECT, 9, 106 Demodulation, 10 Detuning, 26 Differential to single-ended conversion, 209 Digital correction algorithm, 52 Digital data communication, 12 Digital modem, 126 Digital signal processing, 2, 4, 12, 17-18,24,31,

52, 61, 97, 108, 114, 127,135, 181,215 Digital switching noise, 4 Direct digital synthesis, 24 Direct downconversion, 22, 30, 53, 115 Direct synthesis, 195 Direct upconversion, 30, 117, 125, 188 Distortion, 18, 73, 75, 94,96-97, 109, 123, 140,

168, 183, 200 Double quadrature downconversion, 61, 65, 179 Double quadrature upconversion, 66, 188 Down conversion mixer, 138, 208 Downconversion, 11, 150 Duplexer, 135 Dynamic range, 61, 63, 75, 87, 90, 92, 118, 127,

147, 197-198 Eddy-currents, !57 Electro-magnetic simulation, !55, 160 ERMES, 106 Error correction, 12 External components, 4, 181, 216 External nodes, 116 Feed-back,34 Feedthrough, 140

local oscillator, 1 17 Filter, 30, 78

active, 79 anti-aliasing, 126 bandpass, 17, 25, 38, 51, 79, 123, !54 blocking, 114, 122 complex, 51, 197 high frequency, 15, 25 high Q, 88, 91, 121, 145 higher order, 80 highpass, 18 integrated, 15 intermediate frequency, 16 lowQ, 200 low-IF, 200 lowpass, 38, 79, 118, 128, !54, 197 passive, 79 quadrature, 188 real, 36

Filtering, 71 Fixed frequency oscillator, 63

Folded-cascode, 143, 200 Fractional-N synthesis, 125 Frame, 2, 52, 126 Frame-error-rate, I 08 Frequency crosstalk, 47, 49, 51, 178-179, 197, 202 Frequency mirroring, 47 Frequency performance, 136 Frequency shifting, 71 Frequency translation, 7 4, 97 Front-end, 4, 11, 29, 71, 105, 137, 178

receiver, 1 1 transmitter, 23

GaAs, 4, 135, 137, 155,218 Gilbert mixer, 137,151 GSM, 3, 9, 11, 51, 105-107, 197,206, 211 Harmonic balance simulation, 96 Heterodyne, 24

receiver, 14, 30 transmitter, 30

High frequency filter, 15, 25 High-level design, 72, 88, I 05

receiver, 91 transmitter, 88

Highpass filter, 18 Inductor

off-chip, !55 on-chip, 154, 190, 206 planar, !55 spiral, 152

Input conditions, 93, 98 probability, 93

Input spectrum, 93 Integratability, 4, 26, 56, 63, 88, 135, 193, 217 Interference, 11, 26 Intermodulation, 98, Ill, 123, 126, 137, 150, 185 Internal nodes, 116 ISM, 106 LC oscillator, 206 Linear frequency transformation, 38 Linear transfer function, 74 Linearity, 137-138 Local oscillator feed through, 117 Low noise amplifier, 122, 135, 145, 167 Low-IF receiver, 54, 114, 143, 178,193 Low-level design, 73 Lower sideband, 53, 66 Lowpass filter, 38, 79, 118, 128, !54, 197 Marconi, 1 Matching, 53,137,139,169, 181,190 Memory consumption, 96, 101 Microprocessor, 2 Mirrorfrequency, 15-18, 35

Mirror signal suppression, 17, 23, 53, 56, 61, 63, 116,125, 177-178, 193, 197,202

Mirror signal, 53, 128 Mismatch, 19,44,141-142,172,175,179,188,

197 Mixer, 30, 78

CMOS, 138 commutating, 137 complex, 33, 35 efficiency, 83 quadrature, 84

Modeling, 78 power consumption, 78

Modem, 126 Modulation, 10, 23 MOSFET-C, 198 Multi-media, 3, 9 Multi-path architecture, 216 Multi-path operators, 74 Multi-path signal processing, 31 Multi-path topologies, 169,216

compact representation, 40 Multiplication, 33 NADC, 106 Negative frequency, 31-32, 42, 45, 172, 197 Noise figure, 121, 123, 145, !50, 167 Noise, 73, 90,93-94, 109, 122,138,168, 185 Off-chip inductors, !55 On-chip inductors, !54, 190, 206 On-chip signals, !55 Opamp, 142-143, 147,200 Operations, 30 ORCA, 100 Oscillator

fixed frequency, 63 LC, 206 relaxation, 206 variable frequency, 63 voltage controlled, 63, 124-125,206

OTA, 85 OTA-C, 51, 80, 86, 198 Out-of-band blocking signals, 53 Out-of-band signals, 53, 68, 80, 113, 121, 125 Parasitic effects, 73 Performance, 71, 73,147,217

calculation, 96 Phase error, 18, 47, 51, 117,125, 172, 178, 181,

185, 188, 193 Phase information, 96 Phaselockedloop,63, 125 Phase modulation, 17 Phase noise, 124-125, 206

Planar inductors, !55 model, 156 series resistance, 160

Pole mismatch, 49 Pole, 143, 172,195

INDEX 239

Polyphase filter, 65-66, 175, 181, 183, 188, 190, 207

active, 42 passive, 40

Polyphase signal, 32 Positive frequency, 31-32, 42, 45, 172, 197 Power amplifier, 114, 126, 135, 190, 206,219 Power consumption, 3-4, 65, 75, 88, 91, 93, I 00,

116, 123, 135, 138, 154,207 efficiency, 78 modeling, 78 theoretical minimum, 77

Power efficiency, 87, 136, 147 Power spectral density, 19, 53, 87, 92, 94, 96 Power supply, 77, 87, 126, !54 Preamplifier, 126,209 Prescaler, 125, 206 Quadrature accuracy, 49, 52, 126, 171-172, 207 Quadrature down conversion, 17, 22, 30, 53, 56, 61,

63,84,97, 124,178,208 Quadrature error, 18 8 Quadrature filter, 188 Quadrature generator, 117, 125, 171, 175, 181, 188,

207 digital, 171

Quadrature IF upconversion, 68 Quadrature mixer

efficiency, 84 Quadrature noise, 85 Quadrature signal, 97 Quadrature upconversion, 24, 30 Radio, I Rational complex polynomial, 36 Rational polynomial, 36, 96, 195 RC-CR, 42, 56, 171 Real filter, 36 Real signal, 31 Receiver, II

combined IF zero-IF, 22, 101 front-end, II heterodyne, 14, 30 high-level design, 91 low-IF, 54, 114, 143, 178, 193 optimization, 89, 91 trade-offs, 91 widebandiR 63,93 zero-IF, 16, 22, 30, 36, 52, 116, 143,171, 177

240 CMOS WIRELESS TRANSCEIVER DESIGN

Reception conditions, 93 Reference sensitivity, I 09 Relaxation oscillator, 206 Resistors, 137 Self-correlation, 20 Self-mixing, 142, 209 Self-modulation, 66 Sideband, 17, 25 Signal regeneration, 12 Signal swing, 89, 92, 98 Simulated annealing, I 00 Simulation technique, 94 Simulation

electro-magnetic, 155, 160 harmonic balance, 96 transient, 94

Single-ended to differential conversion, 181, 190, 208

Skin effect, 160-161 Slew-rate, 147 Spiral inductors, !52 Spurious emissions, 114 Spurious signals, 138 Subsampling, 138 Substrate coupling, 219 Substrate etching, !57 Switched-capacitor, 138, 198 Synthesizer, 206

TDMA, 107 Television, I Transceiver architecture, 71 Transceiver, 10,205,211 Transient simulation, 94 Transient switching, 113 Transimpedance amplifier, !52 Transmitter, I 0, 23

front-end, 23 heterodyne, 30 high-level design, 88 trade-offs, 88

Trimming, 52, 172, 175,181 Tuning, 52, 125, 172,175, 181,200 Upconversion mixer, 209 Upconversion, 23, !50 Upper sideband, 53, 66 User-end, II, 23 Variable frequency oscillator, 63 Variable gain amplifier, 51 Virtual ground, 138,142-143,208-209 Voltage controlled oscillator, 63, 124--125,206 Volume, 3 Weight, 3-4, 135 Wide band IF receiver, 63, 93 Wireless communication, I, 215 Wireless network, 2 Zero-IF receiver, 16, 22, 30, 36, 52, 116, 143,171,

177