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Appendix A Binary and hexadecimal number systems

In order to understand how information is stored in the memory of a computer we need to know about binary and hexadecimal numbers. In everyday life we normally use decimal numbers. However, computers store information in binary, and hexadecimal is a compact way of representing binary.

Put simply, decimal is counting in tens, binary is counting in twos and hexadecimal is counting in sixteens.

A.1 BINARY AND HEXADECIMAL NUMBERS

A decimal number, say 453 may be expressed in the following way

Similarly, a hexadecimal number, say 974, is expressed as

and the binary number 101 is expressed as

The H at the end of the hexadecimal number 974 is there to indicate that that number is, in fact, hexadecimal rather than decimal or binary. Similarly, a binary number is postfixed by the letter B.

Looking at the three numbers above you can see that decimal numbers are expressed in terms of the powers of tens, hexadecimal numbers are expressed in terms of the powers of sixteens and binary numbers are expressed in terms of the powers of two. The ten, sixteen and two are said to be the base or radix, of the numbers. Decimal numbers have a base of ten, hexadecimal numbers a base of sixteen and binary numbers a base of two. Any number can be used as a base, but in computing, and particularly for microprocessors, the most common bases are sixteen and two.

Exercise A.1 By working out the expressions above, what are 974H and 101B equivalent to as decimal numbers?

89

You know already that decimal numbers use the digits 0 to 9, that is, zero through to one less than the base value.

Exercise A.2 Which digits do binary numbers use?

Hexadecimal numbers need to use sixteen, that is 0 to something. We can use the same digits as are used for decimal numbers up to 9 but for the remaining six digits we need single-character symbols. The chosen symbols are the letters A, 8, C, D, E and F, so that hexadecimal A is equivalent to decimal 10 and hexadecimal F is equivalent to decimal 15.

Look now at Figure A.l which shows the equivalent hexadecimal and binary numbers of the decimal numbers 0 to 15.

decimal

0 1 2 3 4 5 6 7 8 9

10 11 12 13 14 15

hexadecimal

0 1 2 3 4 5 6 7 8 9 A B C D E F

Figure A.l

binary

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

You will need to know the hexadecimal and binary numbers in Figure A.l by heart, so spend a short time making sure that you know them without having to think about it - especially the binary numbers.

Exercise A.3 What is the decimal equivalent of E8A5H?

A.2 BINARY AND HEXADECIMAL ARITHMETIC

Addi tion and subtraction can be done using any base. The technique is the same as for decimal numbers except that any reference to ten is replaced by a reference to the base. For example, when adding two hexadecimal numbers, a carry is produced when the addition of two of the digits result in a number greater than FH, (or decimal 15).

Examples of addition and subtraction using hexadecimal and binary

90

numbers are

3A7FH + 10BBH

4B3AH

10110110B - 01011010B

01011100B

Exercise A.4 Do the following arithmetic

C7BAH 9FF8H

01101101B + 01011110B

A.3 DECIMAL TO HEXADECIMAL CONVERSION

To convert a decimal number to a hexadecimal number, repeatedly divide the decimal number by 16 until a 0 quotient is obtained. The remainders from the divisions constitute the equivalent hexadecimal number, the last remainder so obtained being the most significant digi t of the hexadecimal number. For example, the conversion of 745 to hexadecimal looks like

:: I':: ,,~inde, 9

16 2 remainder E

o remainder 2

the equivalent hexadecimal number being 2E9H.

Exercise A.5 Convert the decimal number 1582 to hexadecimal.

A.4 HEXADECIMAL TO DECIMAL CONVERSION

To convert a hexadecimal number to a decimal number just expand the hexadecimal number in powers of 16, and then add the terms. For example, the conversion of 3AB2H to its equivalent decimal number would look like

3AB2H = (3 x 163) (10 x 162 ) + (11 x 161) + (2 x 160)

= (3 x 4096) + (10 x 256) + (11 x 16) + (2 x 1)

= 12288 + 2560 + 176 + 2

= 15026

the equivalent decimal number being 15026.

91

A quicker way to convert a hexadecimal number to a decimal number (and vice-versa) is to use a conversion table, assuming that one is readily available.

Exercise A.6 Using the converion tables in Appendix B, convert FBH and A3B2H to decimal and 142 and 9467 to hexadecimal.

A.5 BINARY-HEXADECIMAL CONVERSION

Binary to hexadecimal conversion and hexadecimal to binary ~onversion is based on the fact that one hexadecimal digit can be replaced by four binary digits and vice-versa.

So to convert a hexadecimal number, say 6BH, to binary, just replace each hexadecimal digit by its four digit binary equivalent - according to the values in Figure A.l. Hence,

6BH = 0110 1011

which is equal to 1101011B

with the leading zero removed and the two sets of binary digits joined together.

To convert a binary number to a hexdecimal number, the binary number is separated into groups of four binary digi ts from the right. For example, the binary number 1111100111 would look like

11 1110 0111

~ach group of bits is then converted to its equivalent 1exadecimal digit, so the binary number above would look like

3 E 7

Hence, 1111100111B is equivalent to 3E7H.

Exercise A.7 Convert 9AB3H to binary and 110011101111B to hexadecimal.

A.6 DECIMAL-BINARY CONVERSIONS

Conversions between decimal and binary numbers can be done in the same way as we did decimal and hexadecimal number conversions, except that 2 is used wherever we used 16.

However, those methods of conversion are rather tedious for decimal/binary conversions so, either

use hexadecimal as an intermediary, so that, for example, to convert from decimal to binary first convert from decimal to hexadecimal and then to binary,

92

or use a conversion table.

Exercise A.S Convert 1290 to binary and 101110111101B to decimal using both sugg~sted methods.

A.7 BYTES

The basic unit of data in the ZSO microprocessor is a byte, which contains eight binary digits (bits, for short) or two hexadecimal digits. The contents (O's and 1's) of a byte may represent any one of several entities, such as

a character, a number (unsigned),

or a signed number.

Representation of characers is dealt with in Chapter 3.

Representation of a number in a byte refers to the contents of a byte being considered to be the value of the binary number contained in the byte. For example, a byte containing 01100110B represents the number 11100110B, 66H or 102 decimal. The range of numbers which can be contained in a byte is 0 to 11111111B (FFHand 255 decimal). When it is necessary to do so, this representation is distinguished from another representation by referring to it as the unsigned number representation.

Exercise A.9 What range of unsigned numbers can be represented in two bytes (that is, 16 bits)?

A.S SIGNED (2's COMPLEMENT) NUMBERS

Numbers which may have negative values as well as positive values are held in computers in what is called '2'5 complement form'. This form of representation depends on numbers consisting of a fixed number of digits. As we are concerned with the Z80 microprocessor we will consider 2's complement numbers consisting of eight binary digits.

In the 2's complement system, a negative number is represented by taking the 2's complement of its equivalent positive value; this is done by converting all O's to 1's and 1's to O's, and then adding 1. For example,

+5 is

so -5 is

00000101B

11111010B + 1

111110118

93

Hence, -5 is held as 11111011B in a register or memory byte. The mechanism for producing a negative number in 2's complement form is equivalent to subtracting the equivalent positive value from 2.

Exercise A.l0 Calculate the binary equivalent of -1, -2 and -126 and the decimal equivalent of 10000000B and 10000001B, assuming an 8-bit 2's complement system.

When performing arithmetic with numbers within a 2's complement system, numbers are added bi t by bi t as normal but any carry out of the most significant bit is ignored. For example, adding +5 and -5 looks like

00000101B +5 + 11111011B +-5

[1] OOOOOOOOB 0

The one carry out of the addition of the eight two bits is ignored and the result is contained in the 8 bits - that is, zero, which you would expect to obtain when adding -5 to +5.

Exercise A.ll Calculate -60 + 70, -23 + -46, 85 - 96 and 5 - -121, in binary using an 8-bit 2's complement system.

The range of numbers which can be held in a byte, using 2's complement, goes from -128 to +127 as follows

-128 10000000 -127 10000001

-2 11111110 -1 11111111

0 00000000 +1 00000001 +2 00000010

+126 01111110 +127 01111111

There are other ways of representing negative numbers in computers, but the 2's complement method is the most common and the one used by the Z80 microprocessor. However, rather than using the inelegant phrase '2's complement' we shall' refer to 'signed numbers' rather than 2's complement numbers from now on.

It may help you in your understanding of signed numbers and unsigned numbers to look at the weighting of the bi ts in a byte for each of the representations. They are

94

unsigned numbers 128 64 32 16 8 4 2

signed numbers -128 64 32 16 8 4 2

so that, for example, the unsigned number 10010001B is equivalent to

1 x 128 + 1 x 16 + 1 x 1 which equals 145

whereas, the signed number 10010001B is equivalent to

1 x -128 + 1 x 16 +1 x 1 which equals -111.

95

Appendix B Hexadecimaldecimal . conversion tables

The table below provides for direct conversion between hexadecimal numbers in the range 0 to FF and decimal numbers in the range 0 to 255.

o 2 3 4 567 8 9 ABC D E F

00 000 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 10 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 20 032 Q33 034 035 036 037 038 039 040 041 042 043 044 045 046 047 30 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 40 064 065 066 067 068 069 070 071 072 073 074 075 076 077 078 079 50 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 60 096 097 098 099 100 101 102 103 104 105 106 107 108 109 110 111 70 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 80 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 90 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 AO 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 BO 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 CO 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 DO 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 EO 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 FO 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255

For conversion of larger numbers use the following in oonjuction with the table above.

96

Hexadecimal

100 200 300 400 500 600 700 800 900 AOO BOO COO DOO EOO Foa

1000 2000 3000 4000 5000 6000 7000 8000 9000 AOOO BOOO COOO DOOO EOOO FOOO

97

Decimal

256 512 768

1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 8192

12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440

Appendix C Summary of zao instructions

This appendix contains a summary of the complete Z80 instruction set.

The first table, C.l, gives a summary of the flag operations.

In tables C.2 to C.12, the instructions are logically arranged into functional groups. Each table shows the assembly language mnemonic OP code, the numeric OP code, the symbolic operation, the content of the flag register following the execution of each instruction, the number of bytes required for each instruction as well as the number of memory cycles and the total number of T states (external clock periods) required for the fetching and execution of each instruction. Care has been taken to make each table self-explanatory without requiring any cross reference with the text or other tables.

The following pages have been reproduced by permission of Zilog, Inc. 1977. This material shall not be reproduced without the written consent of Zilog, Inc.

98

Instruction C Z~S NH Comments

ADD A, s: ADC A,s t t V t o t S-bit add or add with carry SUB s: SBC A, s, CP s, NEG t t V t t S-bit subtract, subtract with carry, compare and

negate accumulator ANDs 0 t P t 0 1 Logical operations OR s: XOR s 0 t P t 0 0 And set's different flags INC s • t V t 0 t S-bit increment DECm • t V t t S-bit decrement ADDDD,ss t • • • o X 16-bit add ADC HL, ss t t V o X 16-bit add with carry SBC HL, ss t V t I X 16-bit subtract with carry RLA;RLCA,RRA,RRCA t • • • 0 0 Rotate accumulator RL m; RLC m; RR m; RRC m t t P 0 0 Rotate and shift location m

SLA m; SRA m; SRL m

RLD, RRD • t P 0 0 Rotate digit left and right DAA t P • t Decimal adjust accumulator CPL • • • • I Complement accumulator SCF • • • 0 0 Set carry CCF • • • 0 X Complement carry IN r, (C) • t P t 0 0 Input register indirect INI; IND; OUTI; OUTD • t XXI X Block input and output INIR; INDR; OTIR; OTDR • I XXI X Z = 0 if B "" 0 otherwise Z = I LDI, LDD

• X t X 0 0 Block transfer instructions

LDIR,LDDR .X o X 0 0 P/V = I if BC "" 0, otherwise P/V = 0 CPI, CPIR, CPD, CPDR • t t t I X Block search instructions

Z = I if A = (HL), otherwise Z = 0 P/V = I if BC "" 0, otherwise P/V = 0

LDA,I;LDA,R • t FFt 0 0 The content of the interrupt enable flip-flop (IFF) is copied into the P/V flag

BIT b,s • t xix 0 I The state of bit b of location s is copied into the Z flag

NEG t t V t 1 t Negate accumulator

The following notation is used in this table:

Operation Symbol

C

Z

Carry/link flag. C= 1 if the operation produced a carry from the MSB of the operand or result.

Zero flag. Z= 1 if the result of the operation is zero.

S

P/V

H

N

Sign flag. S=l if the MSB of the result is one.

Parity or overflow flag. Parity (P) and overflow (V) share the same flag. Logical operations affect this flag with the parity of the result while arithmetic operations affect this flag with the overflow of the result. If P/V holds parity, PN=l if the result of the operation is even, PN=O if result is odd. If PIV holds overflow, P/V=] if the result of the operation produced an overflow.

Half-cany flag. H=1 if the add or subtract operation produced a carry into or borrow from into bit 4 of the accumulator.

Add/Subtract flag. N=l if the previous operation was a subtract.

Hand N flags are used in conjunction with the decimal adjust instruction (DAA) to properly correct the result into packed DeD fonnat following addition or subtraction using operands with packed BCD format.

The flag is affected according to the result of the operation. • The flag is unchanged by the operation. o The flag is reset by the operation. 1 The flag is set by the operation. X The flag is a "don't care." V P/V flag affected according to the overflow result of the operation. P PjV flag affected according to the parity result of the operation.

Anyone of the CPU registers A, B, C, D. E, H. L. s Any 8-bit location for all the addressing modes allowed for the particular instruction .. • 1 Any 16-bit location for all the addressing modes allowed for that instruction. ii Anyone of the two index registers IX or IY. R Refresh oounteL n &obit value in ta",. <ll, 255> on 16-bit value in t .... <0, 65535>

m Any 8-bit location for all the addressing modes allowed for the particular instruction.

Summary of flag operation Table C.l Courtesy Zilog, Inc.

99

Flap OP-Cod. No. No. Symbolic of ofM

Mnemonic Operation C ZP/V S N H 76 543 210 Dytes Cycles

LD" r' r +- r' · · · · · · 01 , " I I

LD r, n ,-n · · · · · · 00 , 110 2 2 - n -LD',{HL) ,-(HL) · · · · · · 01 , 110 I 2 LD" (IX+d) ,-(IX+d) · · · · .. • II 011 101 3 5

01 , 110 - d -LD" (IY+d) ,-(IY+d) · · · · · · 11 111 101 3 5

01 , 110 - d -LD (HL),' (HL)-, · · · · · · 01 110 , 1 2

LD (IX+d),' (IX+d) -, · · · · · · 11 011 101 3 5

01 110 , - d -LD (IY+d),, (IY+d)-, · · · · · · 11 111 101 3 5

01 110 , - d -

LD (HL), n (HL)-n · · · · · · 00 110 110 2 3 - n -LD {IX+d),n (IX+d) -n · · · · · · 11 011 101 4 5

00 110 110 - d -- n -LD (IY+d),n (IY+d) _n · · · · · · 11 111 101 4 5

00 110 110 - d -- n -LD A, (DC) A-(BC) · · · · · · 00 001 010 1 2

LD A,{DE) A-{DE) · · · · · · 00 011 010 1 2

LD A, (nn) A-{nn) · · · · · · 00 111 010 3 4 - n -- n -LD (DC), A {DC)-A · · · · · · 00 000 010 1 2 LD (DE), A (DE)-A · · · · · · 00 010 010 1 2 LD (nn), A (nn) +- A · · · · · · 00 110 010 3 4

- n -- n -LDA,I A_I · I Iff I 0 0 11 101 101 2 2

I 01 010 111

LDA,R A-R · I IFF I 0 0 11 101 101 2 2

01 011 111

LDI,A I-A · · · · · · 11 101 101 2 2

01 000 111

LDR,A R-A · · · · · · 11 101 101 2 2

01 001 111

Notes: I, r' means any of the registers A, B, C, D. E, H, L

IFF the content of the interrupt enable flip-flop (IFF) is copied into the PIV flag

FlaS Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,

t = flag is affected according to the result of the operation.

No. ofT Cycles Comments 4 " r' R .. ,

7 000 B

001 C

7 010 D

19 011 E

100 H

101 L

19 111 A

7

19

19

10

19

19

7 7

13

7

7

13

9

9

9

9

8-bit load group Table C.2 Courtesy Zilog, Inc.

100

...... Op-C .... No. No. No. Symbolic 01 01 .. oIT

WnetnOllic Operation C Z '", S N H 76 543 210 811 .. Cy"" Stat .. Commenll

to dd, nn dd_nn · · · · · · 00 ddO 001 - n -- n -LD IX, nn IX .... nn · · · · · · 11 011 101

00 100 001

- n -- n -LDIY,nn IV .... nn · · · · · · II III 101

00 100 001 - n -- n -to Ht, (nn) H .... (nn .... ) · · · · · · 00 lOt 010

L_(nn) - n -- n -to dd, (Rn) ddH -(M+}) · · · · · · 11 101 101

ddt _(M) 01 ddt 011

- n -- n -tD IX. (nn) IXH .... (nn+!) · · · · · · 11 011 101

IXL -(nn) 00 101 010 - n -- n -LO IY, (nn) IVH-(nni-I) · · · · · · 11 III 101

IYL .... (Rn) 00 101 010 - n -- n -LD (Rn). Ht {nn+l) .... H · · · · · · 00 100 010

(nn)-L - n -- n -LO (nn), dd (nn"')) -ddH · · · · · · 11 101 101

{nn) ... ddt 01 lidO 011 - n -- n -to (nn), IX (nn+1) -IXH · · · · · · II 011 101

(nnl-IXL 00100010 - n -- n -LD(nnl,IV (nn.+l)-IYH · · · · · · II 111 101

(nnl-IYL 00100010 - n -- n -to SP,Ht S'_Ht · · · · · · II III 001 LO SP,IX S'-IX · · · · · · 11 011 101

11 lit 001

LO S',IV S'-IV · · · · · · 11 III 101 11 111 001

PUSH qq (8.-2) -qqt · · · · · · II qqO 101

(SP-I) -qqu

PUSH IX (SP-2) -IXL · · · · · · 11 011 101 (SP-I) -IXH 11 100 101

PUSH IV (SP-2) -IYL · · · · · · 11 III 101 (SP-I) -IVH 11 100 101

POPqq qqH-(SP+l) · · · · · · 11 qqO 001

qqL - (SP) POP IX IXH -(SP+l) · · · · · · 11 011 101

IXL -<SP) 11 100 001

POPIY IYH -<SP+l) · · · · · · 11 III 101 IYL -(SP) 11 100 001

Not .. : dd il any of the 'epater paUl BC, DE, HL, SP qq ilany of the r ..... pairsAF, &C, DE, HL

, 3 10 .. hi,

00 Be

01 DE

• • 14 10 HL

11 sr

• • 14

3 , 16

• 6 20

• 6 20

• 6 '0

3 , 16

• 6 20

• 6 '0

• 6 '0

1 1 6 , , 10

, , 10 .. "'" 1 3 11 00 Be

01 DE , • " 10 HL

11 AF 2 • " 1 , 10

, • 14

, • ••

(PAIR)H' (PAIR)L refer 10 h.iah order and low order eiahl bill of the repter pair rapec:tmly. E ... BCL -C,AFH-A

n. Notlotiml: _. fJq not affected, 0 • flq relet, 1 • fila sel, X· flq is unknown, * flq il affected aoc:ordirc to tbe result of the operation.

16-bit load group Table C.3

101

courtesy Zilog, Inc.

Flags Op..code

~ Symbolk Mnemonic Operation C Z V S N II 76 543 210

EX DE. ilL DE·- Hl · · · · · · II 101 011

EX AI', AF' AI' .. AF' · · · · · · 00 001 000

FXX

(~t}~D · · · · · · II 011 001

EX (SP), ilL H~ISP+I) · · · · · · II 100 011

l ~ ISP)

EX (SP),IX IXH~(SP+I) · · · · · · II 011 101

IXL ..... (SPI II 100 011

FX ISP), I)' IY H"ISP+ I) · · · · · · II III 101

l)'l~ISP) II 100 011

CD WI 101::)- (!iLl · · I · II 0 II 101 101

1>£ +- DE+ I 10 1110 000

!-Il - IIL+ I

Be - Bel

llllR IDFI- (1I11 · · II · II 0 II 1111 101

DE.- DI::+ I 10 II () 000

IIl- 111.+ I

Be -11('·1

i{l'pt'at until

IH' = 0 CD

lilil IDI" 1 .. - (Ill.) · · I · II 0 II Illi 101

D1. ~ Dr-I III 101 000

HL .. 111.·1

Bt' .. He-I

L1)l)R (UU .. - (JILl · · II · " 0 II 1111 101

IlE-D[-.J 10 III 000

III. - HE·I

B(' - Be·1

Rcpeat until

HC ~ 0

Q)CD

CPI A - HIL! · I I I I I II 101 101

HL - IIL+I 10 100 001

BC-BC-I

Q)CD

ePIR A - (HL) · I I I I I II 101 101

ilL -- HL+l 10 110 001

Be -1lC-1

RCPI'Olt until

A = liIl.I or

BC "I)

a>ICB

CI'D A - (HL! · I I I I I II 101 101

Ill·- Hl·1 10 101 001

BC - B(,·I

Q)CB

ePDR A -1111.) · I I I I I II 101 101

III -lll·1 10 III 001

BC - BC·I

Rcpeal until

A = (Hl) or

BC = 0

Noles: CD P, V flag is 0 if the result of HC-I = 0, otherwise PlY = I

<%> 1 flag I~ 1 if A = <HL I. otherwise Z :::. O.

No. No. of ofM Bytes Cycles

I I

I I

I I

I 5

2 6

2 6

2 4

2 5

2 4

2 4

2 5

2 4

1 4

1 5

1 4

2 4

2 5

2 4

Hag Notation: • = nag not aftl'l.:tcd. 0;;; nag Tt!SCt. I = flag set. X = nag IS unknown,

t = nag I~ affectt!d according to the result of the operation.

No. ofT States Comments

4

4

4 Register bank and auxiliary register ban k exchange

19

23

23

16 Load (HLJ mto (DE). Increment the pointers and decrement the byte ~ounter OK)

21 If BC" 0

16 If BC ~ 0

16

21 If Be "0

16 If Be ~ 0

16

21 If Be " 0 and A " (II 16 If Be = 0 or A = (ilL)

16

21 If Be " 0 and A " (II 16 If Be = 0 or A = (ilL)

Exchange group and block transfer and search group

L)

L)

Table C.4 Courtesy Zilog, Inc.

102

Flags

Symbolic ~ Mnemonic Operation C Z V S N H

ADDA,r A-A+r I I V I 0 I

ADD A,n A-A +n I I V I 0 I

ADD A,(HL) A· A+(HL) I I V I 0 I ADD A,(lX+d) A-A + (lX+d) I I V I 0 I

I ADD A, (IY+d) A-A+(JY+d) I I V I 0 t

ADC A,s A - A + s + CY I I V t 0 I SUB ~ A--A-s I I V I I I sse A,s A -- A - s - CY I I V I 1 I ANDs A-- A A S 0 I P I 0 I

OR s A-A V s 0 I P t 0 0

XORs A ..... A ets 0 I P t 0 0

CP s A-s 1 I V I I I INC r r - r+ I · I V I 0 I INC (Hl) (Ill) - (Hl)+ 1 · 1 V t 0 I INC (IX+d) (IX+d) - · I V I 0 I

(lX+d)+1

INC (IY+dl (IY+dl- · t V I 0 I ClY+d) + 1

DECm m+-m-l · I V I 1 1

Op-Code No, 01

76 543 210 Bytes

10 IQQill r I

II [QQQ] 110 2

- n ~

10 [QQQ] 110 I

II Oil 101 3

10 1QQill110

- d -II III 101 3

10 1QQill110

- d -[@] IQIQ] Il!I!J [jQQJ [jJ]]

Will OJIJ

00 r IJ]jj] 1

00 110 IJ]jj] 1

11 011 101 J

00 110 []]!Q] d .

11 III 101 J

00 '110[J]QJ

- d

Will

No, No, olM ofT Cycles States

I 4

2 7

2 7

5 19

5 19

1 4

J 11

6 2J

6 23

Comments

r Reg. 000 B 001 C 010 D Oil E 100 II 101 l III A

~I~anyofr.n,

(Ill), (IX+d), (IY+d) :h ~hown t AllD imlrtH:tlon

The tnuit:ah..:d blh rcplat:e the 000 in Ihe ADD \.:1 abo"

m is any ofr. (H L), IX+d ),( IY+d a ..

.. hown for INC Saml' format .LIlU

" .. ll''':.1\ INC Ih'pt"l'l' 100 WJlh lUI III OP lOlk

Notes: The Y symbol in the PlY nag column indICate'> that the p'y nag contam~ the overflow of thl' fl''>lJlt 01 !Ill' operation Similarly the P ~ymbol indkatc~ panty. V ::: 1 mc;m\ oYl'rflow, Y = 0 mcam not oVl'rflow p:; I means parity of the result is even. P = 0 mea.n .. pointy of thl' rC\lIlt i\ oL1d.

Flag Notation: • = flag not affl'cted. 0 = nag rc..ct, I = flag ~l't, X = nag I~ unkml\\'n, t = flag is affected according to the rc .. ult of the op..-ralion,

8-bit arithmetic and logical group Table C.5 Courtesy Zilog, Inc.

103

Flap

Symbolic ~ Mnemonic Operation C Z V S N H

DAA Converts acc. I I P I · I content into packed BCD following add or subtract with packed BCD operands

CPL A+-A · · · · I I

NEG A-O-A I I V I I I

CCF cv-ev I · · · 0 X

SCF CY-I I · · · 0 0

NOP No operation · · · · · · HALT CPU halted · · · · · · 01 IFF-O · · · · · · EI IFF-I · · · · · · IMO Set interrupt · · · · · · mode 0

IMI Set interrupt · · · · · · mode 1

1M2 Set interrupt · · · · · · mode 2

Notes: IFF indicates the interrupt enable flip-flop CY indicates the carry flip-flop.

Op-Code No. No. of ofM

76 543 210 Bytes Cycles

00 100 III I I

00 101 III I I

II 101 101 2 2

01 000 100

00 III III I 1

00 110 III I I

00 000000 I I

01 110 110 I I

II 110011 I I

II III 011 I I

II 101 101 2 2

01 000 110

II 101 101 2 2

01 010 110 II 101 101 2 2

01 011 110

Flag Notation: • = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown.



4 Decimal adjust accumulator

4 Complement accumulator (one's compiemen t)

8 Negate ace, (two's complement)

4 Complement car ry flag

4 Set carry flag

4

4

4

4

8

8

8

General purpose arithmetic and CPU control groups Table C.6 Courtesy Zilog, Inc.

104

Symbolic Fl ... OtK:ode

Mnemonic Operation Z r", S N H 76 543 210

ADDHL, IS HL-HL+ss I · · · 0 X 00 ssl 001

ADCHL,ss HL-HL+ss+CY I I V I 0 X 11 101 101

01 .. I 010

SDC HL, II HL-HL-ss.cy I I V I I X II 101 101

01 ssO 010

ADD IX, pp IX -IX +pp I · · · 0 X 11 011 101

00 ppl 001

ADD IY,rr IY-IY+ rr I · · · 0 X 11 111 101

00 rrl 001

INC .. ss-ss+1 · · · · · · 00 ssO 011

INC IX IX-IX+ I · · · · · · 11 011 101

00 100 011 INC IY IY-IY+ I · · · · · · II III 101

00 100 011 DEC .. ss-u-l · · · · · · 00 ssl 011

DEC IX IX-IX·! · · · · · · II 011 101

00 101 011

DECIY IY_IY·I · · · · · · II III 101

00 101 011

Notes: 55 is any of ~he register pairs BC. DE, HI., SP pp is any of the register pairs BC. DE. IX. SP rr is any of the register pain BC, DE, IV. SP.

No. No. of ofM Bytes Cye'"

I 3

2 4

2 4

2 4

2 4

I I

2 2

2 2

I I

2 2

2 2

Fill Notation: - = flag not affected. 0 = nag reset, I = flag sct, X = nag is unknown. S = nag is affected according to the result of the OpcrJlion.

16-bit arithmetic group

No. ofT States Commenta

11 II Rei· 00 DC

IS 01 DE 10 HL 11 SP

IS

IS pp Rei· 00 DC 01 DE 10 IX II SP

IS rr Rei· 00 DC 01 DE 10 IY II SP

6

\0

10

6

10

10


105

Flap Op-Code

~ No.

Symbolic of Mnemonic Operation C Z V S N H 76 543 210 Bytes

RLCA B-Y7 A o..J I · · · 0 0 00000 III I

RLA 4l--i1 ~ ot-l I · · · 0 0 00010 III I

RRCA Y7 A o~ I · · · 0 0 00 001 III I

RRA ~ I · · · 0 0 00 011 III I

RLCr I I P I 0 0 II 001 011 2

OO[QQQ]r RLC (HL) I I P I 0 0 II 001 011 2

00(]QQ]1I0 RLC (IX+d) ~ I I P I 0 0 II 011 101 4

r.(HlI,UX+4),rIV+d) II 001 011 - d -00 [jiQQ}1O

RLC (IY+d) I I P I 0 0 II III 101 4 II 001 011 - d -00~1I0

RLm ~ I I P I 0 0 [Q!Q] m '" •. (HL,,!DI.+df.UY+d)

RRCm ~ I I P I 0 0 @QIJ m 0 r,(Hl).(lX+dJ, flY.d)

RRm ~ I I P I 0 0 [QIT] m" •. (HU.IIX+<IJ,IIY+d)

SLAm ~o I I P I 0 0 [NQ] m ~ r,(HL),HX+d). flY-d)

SRAm ~ I I P I 0 0 I]QIJ m=r,rHL).(lX+d).(lY+d)

SRLm o~ I I P I 0 0 DID m = r. (HL), HX+d), (lY+d)

RLD '~'"U . I P I 0 0 II 101 101 2

01 101 III

'~'"U RRD . I p I 0 0 11 101 101 2

01 100 111

Fl., Notation: • = nag not affected, 0 = flag reset, I = flag set, X = flag is unknown, : = flag is affected according to the result of the operation.

Rotate and shift group

No. No. ofM ofT Cycles States Comments

I 4 Rotate left circular accumulator

I 4 Rotate left accumulator

I 4 Rotate right circular accumulator

I 4 Rotate right accumulator

2 8 Rotate left circular register r

4 15 r lUg.

000 B

6 23 001 C 010 ·D 011 E 100 H 101 L

6 23 III A

Instruction fonnat a nd states are as shown for RLC,m. To form new OP ·code replace lQQiiIof RLC,m with shown code

5 18 Rotate digit left and right between the accumulator and location (HL).

5 18 The content of the upper half of the accumulator is unaffected

Table C.B Courtesy Zilog, Inc.

106

Flap OiKode

~ JIIo. No.

Symbolic: or orM Mnemonic Opention C Z V S N H 76 543 210 Byt .. Cyel ..

BIT b,' Z-rb · f X X 0 I II 001 011 2 2

01 b , BlTb, (HL) Z-(HL~ · f X X 0 1 II 001 011 2 3

01 b 110 BIT b, (IX +d) Z-(IX+d)b · f X X 0 I II 011 101 4 5

11 001 011 - d -01 b 110

BIT b. (IY+d) Z -(IY+d)b · f X X 0 1 II III 101 4 5

II 001 011 - d -01 b 110

SETb, , 'b -1 · · · · · · 11 001 011 2 2

ITIlb , SETb, (HL) (HL)b -I · · · · · · 11 001 011 2 4

[jJ]b 110 SETb, (IX+d) (IX+d)b - I · · · · · · II 011 101 4 6

11 001 011 - d -[jJ]b 110

SET b, (IY+d) (IY+d)b -1 · · · · · · II 111 101 4 6 II 001 011

- d -[ill b 110

RES b, m .,,-0 UQ] m=" (HLl,

(IX+d), (IY+d)

Note,: The notation It, indicate. bit b (0 to 7) or location So

FI .. Notation: _ = flq not affected. 0 = flag rcset, I ':: flag set. X = nag is unknown.

$ = flag j:l; affected according to the result of the operation.

Bit set, reset and test group

No. orT States Comment.

8 , Rea· 000 B

12 001 C 010 D 011 E

20 100 H 101 L 111 A

b Bit Teated 20 000 0

001 I 010 2 011 3 100 4 101 5 110 6 III 7

8

15

23

23

To form new Op· code ,eplace IIil of SET b,m with @. Flags and time states fo, SET instruction


107

Flags OJK:odo

~ No.

Symbolic oC Mnemonic Operation C Z VS N H 76 543 210 Bytes

IP nn PC-nn 0 0 0 0 0 0 II 000011 3 - n -- n -JP ce, nn If condition cc 0 0 0 0 0 0 II cc 010 3

is true PC +-no, .- n -otherwise continue - n -

JR. PC-PC+e 0 0 0 0 0 0 00 011 000 2 - .-2 -JR C.' ICC = 0, 0 0 0 0 0 0 00 III 000 2

continue - 0-2 -ICC = I, 2 PC -PC+e

JR NC,. Irc = I. 0 0 0 0 0 0 00 110 000 2 continue - 0-2 -IC C = O. 2 PC-PC+.

JR Z,. IC Z = 0 0 0 0 0 0 0 00 101 000 2 continue - .-2 -ICZ = I, 2 PC-PC+e

JR NZ,' If Z = I, 0 0 0 0 0 0 00 100 000 2 continue - .-2 -IfZ = O. 2 PC-PC+e

IP(HL) PC-HL 0 0 0 0 0 0 II 101 001 I

IP (IX) PC-IX 0 0 0 0 0 0 II 011 101 2 11 101 001

JP(IY) PC-IY 0 0 0 0 0 0 II III 101 2 II 101 001

DJNZ,' B-B-I 0 0 0 0 0 0 00 010 000 2 ICB = 0, - .-2 -continue

IfB" 0, 2 PC-PC+e

Notes: e represents the extension in the relative addressing mode.

e is a signed two's complement number in the ranae <-126, 129>

e-2 in the op-code provides an effective address of pc +e as PC' is incremented by 2 prior to the addition of Co

No. oCM Cycles

3

3

3

2

3

2

3

2

3

2

3

I

2

2

2

3

Flag Notation: _ = flag not affected, 0 = flag reset, 1 = flag set, X = flag is unknown,


No. oCT States Comments

10

cc Condition

10 000 NZnon zero 001 Z zero 010 NeDon carry 011 C carry 100 PO parity odd 101 PE parity even 110 P sign positive

12 III M sign negative

7 If condition not met

12 If condition is met

7 If condition not mct


7 If condition not met


7 If condition not mt"

12 If condition met

4

8

8

8 IfB=O

13 IF B,. 0

Jump group Table C.l0 Courtesy Zilog, Inc.

108

Flap Op<:ode

~ No. No.

Symbolic of ofM Mnemonic Opention C Z V S N H 76 543 210 Byles Cycles

CALL nn (SP·I)-PCH · · · · · · II 001 101 3 5 (SP.2)-PCL - n ~

PC-nn - n ~

CALL ce, nn If condition · · · · · · II cc 100 3 3 cc is false - n -continue, otherwise - n - 3 5

same as CALL nn

RET PCL -(SP) · · · · · · II 001 001 I 3

PCH-(SP+I)

RETcc If condition · · · · · · II cc 000 I I cc is false continue,

I 3 otherwise same as RET

RETI Return from · · · · · · II 101 101 2 4 interrupt

01 001 101

RETN Return from · 11 101 101 2 4 non maskable · · • • · intenupt 01 000 101

RSTp (SP.I)-PCH · · · · · · II I III I 3 (SP.2)-PCL

PCH-O

PCL-P

Fl .. Notation: • = flag not affected, 0 = flag reaet, 1 = flag set, X = flag is unknown t = flag is affected according to the result of the operation.

Call and return group


17

10 If cc is false

17 If cc is true

10

S If cc is false

II If cc is true cc Condition

000 NZ non zero 001 Z zero 010 NC r.cn CLrry

14 011 C carry 100 PO puilyodd

14 101 PE parity even 110 P siln positive III M sian neptive

11

I P 000 OOH 001 08H 010 10H 011 18H 100 20H 101 28H 110 30H III 38H

Table C.ll Courtesy Zilog, Inc.

109

Flags Op-Code

~ No. No.

Symbolic of ofM Mnemonic Operation C Z V S N H 76 543 210 Bytes Cycles

IN A, (n) A+- (n) · · · · · · II 011 011 2 3 - n -IN r. (e) r-(C) · I P I 0 I 11 101 101 2 3

if r = 110 only 01 r 000 the flags will be affected

iG: INI (HL)-(C) · I X X I X II 101 101 2 4

B-B·I 10 100UIO

IIL-IIL+ I

INIR (ilL) _ (C) · I X X I X 11 101 101 2 5

B- B·I 10 110010 (If B '" 0)

HL-IIL+ I 2 4 Repeat until (If 0 = 0) B=O

IND (IIL)-(C) · jG: I X X I X II 101 101 2 4

B-B·I 10 101 010

ilL-ilL· I

INDR (IIL)-(C) · I X X I X 11 101 101 2 5 B_B-I 10 III 010 (If 0 '" 0)

ilL -IIL-I 2 4

Repeat until (If B = 0) B=O

OUT (n), A (n) -A · · · · · · II 010 011 2 3 <- n ->

OUT(C),r (C)-r · · · · · · II 101 101 2 3

01 r 001 IQ;

OUT! (C) -(ilL) · I X X I X II 101 101 2 4

B-B·I 10 100 011

ilL -ilL + I

OTIR (C) - (HL) · I X X I X II 101 101 2 5

B-B-I 10 110 011 (If B '" 0)

ilL - ilL + I 2 4 Repeat until (If B = 0) B=O

~ OUTD (C) -(ilL)

~ '-" 2 4 · I X X I X II 101 101

B-B -I 10 101 011

IIL-HL-I

OTDR (C) -(ilL) · I X X I X II 101 101 2 5

B- B-1 10 111 011 (If 0'" 0)

IIL-IIL·I 2 4

Repeat until (If 8 =0) 8=0

Notes: CD If the result of B-1 is zero the Z flag is set, otherwise it is reset·

Flag Notation: _ = flag not affected. 0 = flag reset, 1 = flag set, X = flag is unknown. t = flag is affected according to the result of the operation.

Input and output group


II n to AO - A7 Ace to Ag - A 15

12 CtoAO -A7 BtOAg - AI5

16 C to AD - A7

BtoAg - AI5

21 Cto AD - A7

B to A8 - AI5

16

16 C to AO - A7

B to A8 - AI5

21 (' to AO - A7

B to Ag - AI5

16

II n to AU - A1

Ace to Ag - Al5 12 Cto AO - ~

B to Ag - AI5

16 (' to AO - A7 B to AM - A15

21 (' to AU - A7

B to Ag - AI5

16

16 (' to AU - A7

o to Ag - AI5

21 C to AO - A7

BtoAR - AI5

16


110

Appendix D Display and keyboard character codes

The ASCII code character set is shown below

b7 --. 0 0 0 0 I I I b6 - 0 0 I I 0 0 I b5 - 0 I 0 I 0 I 0

b b b b

~ 4 3 2 I 0 I 2 3 4 5 6

0 0 0 0 0 NUL DLE SP 0 @ P ,

0 0 01 I SOH DCI I I A Q a

0 0 10 2 STX DC2 II 2 B R b

0 0 I I 3 ETX DC3 I~ 3 C S c

0 10 0 4 EOT DC4 $ 4 D T d

0 101 5 ENQ NAK 0/0 5 E U e

0 I I 0 6 ACK SYN a 6 F V f

0 I I I 7 BEL ETB I 7 G W 9

10 0 0 8 BS CAN ( 8 H X h

10 01 9 HT EM ) 9 I Y i

10 10 10 LF SUB * · J Z j · 101 I II VT ESC + · K [ k , I 10 0 12 FF FS t < L ""- I

I 10 I 13 CR GS - - M J m

I I 10 14 so RS . > N A n

I I I I 15 SI us / ? 0 - 0

I I

I

7

p

q

r

s

t

u

v

w

x

Y

z

{ I I

} rv

DEL

For example, the AscII code for the character K is binary 1001011, hexadecimal 4B and decimal 75.

111

Appendix E Expression operators

The following table lists these operators which may be used in an operand expression. The list is in order of precedence of evaluation.

OPERATOR

+

.NOT. or \

.RES. ** * I .MOD • • SHR. .SHL. +

.AND. or &

.OR. or A

.XOR.

.EQ. or =

.GT. or >

.LT. or <

.UGT.

.ULT.

FUNCTION

Unary plus Unary minus Logical NOT Result Exponentiation Multiplication Division Modulo Logical shift right Logical shift left Addition Subtraction Logical AND Logical OR Logical XOR Equals Greater than (signed) Less than (signed) Unsigned greater than Unsigned less than

The Result operator (.RES.) causes overflow to be suppressed during evaluation, so that an assembly error does not result from an overflow condition.

The Modulo operator (.MOD.) is defined as

.MOD.B = A-B*(A/B)

where the AlB is an integer division.

The Shift operators (.SHR. and .SHL.) are followed by two arguments. The first argument is shifted by the number of bits specified by the second argument.

The five comparison operators (.EQ., .GT., .LT., .UGT. and .ULT.) evaluate to logical TRUE (all ones) if the comparison is true, and a logical FALSE (zero) otherwise.

112

Exercise answers

The answers are in exercise-number/chapter-number order. This unusual ordering will help you to avoid seeing the answer to the following exercise.

113

ANSWERS TO EXERCISES NUMBERED 1

1.1 A keyboard is used to input programs and data.

2.1 Because the value of n must be contained in one byte.

3.1 ; subroutine to sum the single registers

SUMREG: LD A,O ADD A,B ADD A,C ADD A,D ADD A,E ADD A,H ADD A,L RET

4.1 program to repeatedly output an *

NEXT:

5.1

6.1 255

7.1

8.1 Yes

LD A, '*' CALL COUT JP NEXT

LD A,120 SUB 122 LD B,A SUB B ADD A,70 NEG

LD A, '*' CALL COUT DEC C

A

120 -2 -2 o

70 -70

S

? 1 1 o o 1

z

? o o 1 o o

will be executed 4 times will be executed 24 times will be executed 4 times

9.1 The Z flag will be set to 1.

10.1 The accumulator and carry flag will contain 53H and 1, respectively.

11.1 The result of the logical operator XOR is one if the two binary values to be XORed are different, otherwise the result is zero.

114

12.1 A Carry

RLA 01010110B 1 RLCA 10101100B 0 RRA 01010110B 0 RRCA 00101011B 0

13.1 -32768 to +32767

14.1 Replace LD B,10 by LD BC,number-of-bytes, and DJNZ NEXBYT by DEC BC

LD A,B CP 0 JP NZ,NEXBYT LD A,C CP 0 JP NZ,NEXBYT

15.1 01010111B

A.l 974H is equivalent to 2420. 101B is equivalent to 5.

115


1.2 The accumulator and flag registers, respectively.

2.2 LD A,73 ADD A,55 SUB 21

3.2 47H and +.

4.2 A JP instruction occupies 3 bytes and a JR instruction occupies 2 bytes.

5.2 i) ii)

iii) iv)

LD A,X SUB 10 JP Z,EQUAL LD A,O

6.2 program to output n asterisks

CALL CINEKO SUB 30H

input digit convert to value n

7.2

8.2

9.2

10.2

LD B,A LD A, ,.,

NEXTAS: CALL COUT DJNZ NEXTAS HALT

output •

i) Implied addressing (the accumulator ii) Register addressing (register D)

iii) Implied addressing (the accumulator immediate addressing (the value 50)

iv) Register addressing (register A) and

is

is

extended addressing (the address 6352H)

CARRY

BIT O,A JR Z,EVEN

ODD: SET 7,B JR CONTIN

EVEN: RES 7,B CONTIN: -

B

LD B,11 00001011B (+10) SRA B 00000101B (+5)

implied)

implied)

C

? ?

LD C,-8 " 11111000B (-8) SRA C " 11111100B (-4)

116

and

Carry

? 1 1 0

11.2 A S Z C

LD A,10110101B 10110101B ? ? ? LD C,lll10000B 10110101B ? ? ? AND 00011111B 00010101B 0 0 0 OR C 11110101B 1 0 0 XOR 11001100B 00111001B 0 0 0 CPL 11000110B 0 0 0

12.2 The accumulator rotate instructions each occupy one byte and set only the carry, flag whereas the general register and memory byte rotate instructions each occupy two or four bytes and set the carry, zero and sign flags.

13.2 RESMS will contain 0668H and RESLS will contain 0930H.

14.2 LD LD LD LDDR HALT

HL,SOURCE+9 DE,DESTIN+9 BC,10

set pointers to the end of the blocks

15.2 A byte can contain BCD numbers in the range 0 to 99 and unsigned binary numbers in the range 0 to 255, that is, more than double the range for BCD numbers.

A.2 0 and 1.

111


1.3 Decimal 65536, hexadecimal 10000.

2.3 LD A,56 SUB 22 LD B,A ADD A,B ADD A,B

3.3 1008H

4.3 ; subroutine to input and echo a character

CINEKO: CALL CIN CALL COUT RET

5.3 program to check for B + C being +ve, -ve or 0

LD A,B ADD A,e B + C JP M,NEG JP Z,ZERO LD A, 'pI +ve CALL eOUT JP DONE

NEG: LD A, 'N' -ve CALL COUT JP DONE

ZERO: LD A,' Z' 0 CALL COUT

DONE:

6.3 ; program to output digits 9 to 1

LD A,39H ; code for 9 NEXDIG: CALL COUT

DEC A CP 30H JR NZ,NEXDIG HALT

7.3 A HL

LD HL,N2 ? 1761H LD A,(N1) 14H 1761H SUB (HL) j7H 1761H LD (DIFF) ,A 37H 1761H LD A,(N1) 14H 1761H ADD A, (HL) F1H 1761H LD (SUM),A F1H 1761H HALT F1H 1761H

118

8.3 SCF set carry flag to 1 CCF complement it (now set to 0)

9.3 161H

10.3 SLA A 2 x N LD B,A SLA A 2 x (2 x N) SLA A 2 x (2 x 2 x N) ADD A,B 2 x 2 x 2 x N + 2 x N

11.3 OR 30H

12.3 LD A,B RRCA OR C LD (SEXAGE),A

13.3 SCF reset carry flag CCF to 0 SUB HL,BC

14.3 LD HL,SOURCE LD DE ,DESTIN LD BC,10

NEXBYT: LDI JP PE,NEXBYT HALT

15.3 00010111 BCD 17 + 01101001 BCD 69

--------10000000

+ 0110 --------10000110 BCD 86 --------

A.3 E8A5H = E x 4096 + 8 x 256 + A x 16 + 5 x = 14 x 4096 + 8 x 256 + 10 x 16 + 5 x = 57344 + 2048 + 160 + 5 = 59557

119


1.4

2.4

4.4

5.4

6.4

Hexadecimal BO

27 -27 -26

37H and

lBH E5H E6H

08H

LD A,(COUNT) CP 100 JP M,LESS JP Z,EQUAL JP GREAT

LD A,OAH LD B,OBH LD C,OCH LD D,ODH LD E,OEH LD SP,16383 PUSH AF PUSH BC PUSH DE POP BC POP DE

COUNT < 100 COUNT = 100 COUNT > 100

A B C 0 E SP

OAH ? ? ?? ? OAH OBH ? ?? ? OAH OBH OCH?? ? OAH OBH OCH ODH? ? OAH OBH OCH ODH OEH ? OAH OBH OCH ODH OEH 16383 OAH OBH OCH ODH OEH 16381 OAH OBH OCH ODH OEH 16379 OAH OBH OCH ODH OEH 16377 OAH ODH OEH ODH OEH 16379 OAH ODH OEH OBH OCH 16381

7.4 MESS12: DEFM 'FIRST LINE' DEFB ODH CR code

LF code DEFB OAH DEFM 'SECOND LINE'

8.4 10010101 (-107) + 10010101 (-107)

[1] 00101010 (+42)

9.4 48H - the code for the character H.

11.4 MUL4: MACRO SLA SLA EN OM

12.4 (i) D8H (ii) 2BH

13.4 Replace the ADC opcode by a SBC opcode.

120

14.4 LD HL,HERE LD DE,THERE LD BC,1000

NEXBYT: LDI LD A, (HL) CP 0 JP NZ,NEXBYT

15.4 10000010 BCD 82

A.4

- 01010110 BCD 56

00101100 - 0110

00100110 BCD 26

C7BAH - 9FF8H

27C2H

121

011011018 + 01011110B

110010118


1.5 10000001B

2.5 i) 35H ii) 79

7.5 LD HL,TEXT NEXCH: LD A, (HL)

CP 0 JP Z,LASTCH CALL COUT INC HL JP NEXCH

LASTCH: HALT

TEXT: DEFM 'ABCDEFGHIJK' DEFB 0

11.5 DORP: DEFL n

12.5

OUTLIN: COND DORP

RET ENDC

COND .NOT. DORP OUTLIN: -

RET EN DC

AND OFEH SLA A RLA

14.5 LD HL,START+499 LD DE,START+599 LD BC,500 LDDR

n is 1 for display output n is 0 for printer output

display output subroutine

printer output subroutine

Parity

1 o o

15.5 A

A.5 62EH

LD A,43H LD B,28H ADD A,B DAA

122

43H 43H 6BH 71H


1.6 INC B

12.6 CHKPAR: BIT O,B JP Z,EVTEST AND OFFH JP PO,OK JP NOTOK

EVTEST: AND OFFH JP PE,OK

NOTOK: LD C,1 JP RETSUB

OK: LD C,O RETSUB: RET

14.6 6, or 0 if the block does not contain a zero value.

A.6 FBH is equivalent to 251 A3B2H is equivalent to 41906 142 is equivalent to 8EH 9467 is equivalent to 24FBH

123

ANSWERS TO EXERCISES NUMBERED 7,8 AND 9

14.7 Replace the instructions CPIR to HALT by

NEXBYT: CPI JP PO,FINI end of block? JR NZ,NEXBYT LD A,C output counter ADD A,30H CALL COUT LD A,O restore A JR NEXBYT

FINI: HALT

A.7 9AB3H is equivalent to 1001101010110011B 110011101111B is equivalent to CEFH

A.8 1290 is equivalent to 50AH and 10100001010B 101110111101B is equivalent to BBDH and 3005

A.9 Unsigned numbers in the range 0 to 1111111111111111B (FFFFH and 64535) can be represented in two bytes.

124

ANSWERS TO EXERCISES NUMBERED 10 AND 11

A.10 -1 is equivalent to 11111111B -2 is equivalent to 11111110B

A.11

-126 is equivalent to 10000010B 10000000B is equivalent to -128 10000001B is equivalent to -127

11000100 -60 + 01000110 + +70

--------[1] 00001010 +10

--------

11101001 -23 + 11010010 + -46

--------[1] 10111011 -69

--------

01010101 +85 - 01100000 - +96

--------[1] 11110101 -11

--------

00000101 +5 - 10000111 --121

--------[1] 01111110 +126

--------

125

Index

ADC 13.2. 13.4 ADD 8-bit 2.2. 2.3

16-bit 13.2. 13.3 AND 11. 1. 11.2 Auxiliary registers 16.2

BCD arithmetic 15.2 instructions 15.3 numbers 15.1

Binary numbers A.l. A.2 BIT 9.1 Block search instructions 14.2 Block transfer instructions 14.1 Bytes A.1

CALL 3.2. 1.5. 8.5. 12.5 Carry 8.1

flag 8.2 Character codes 3.3. 4.3. D Comments 2.8 COND 11.5 Conditional jump 5.2 Conditional pseudo operations 11.5 Conversion - numbers A.3 to A.6. B CP 5.3 CPD 14.2 CPDR 14.2 CPI 14.2 CPDIR 14.2 CPL 11.2

DAA 15.3 DEC 8-bit 2.5. 6.2

16-bit 1.4. 13.3 DEFB 2.8 DEFL 11.5 DEFM 1.3 DEFS 9.3 DEFW 13.1 Division 10.4 DJNZ 6.1

126

END 3.4 ENDC 11.5 EQU 4.4 Exchange instructions

stack 6.4 registers 16.2

Expressions 9.5. E Extended addressing 2.1

Flag register 5.1

HALT 2.8 Hexadecimal numbers A.l. A.2

Immediate addressing 2.1 extended 1.2

Implied addressing 1.2 INC 8-bit 2.5

16-bit 1.4. 13.3 Index registers 9.4. 13.3 Input from keyboard 4.2

instructions 16.3 numbers 6.2

Interrupt instructions 16.4

JP conditional 5.2. 8.2. 8.4. 12.5

unconditional 4.1 Jump tables 9.6

Labels 2.8 LD 2.1. 2.4 LDD 14.1 LDDR 14.1 LDI 14.1 LDIR 14.1 Logical operations 11.1 Loops lj. 1. 5.4. 6. 1. 1. 1. 13.3

Macros 11.4 Masking 11.3

Memory 1.3 Modular programming 4.2 Nultiple byte arithmetic 13.4 Multiplication 10.4

NEG 2.6 Nibble 15.1 NOP 16.1 NOT operation 11.1

OR 11. 1, 11. 2 ORG 3.4 Output to display 3.3

of text 7.4 instructions 16.3

Overflow 8.3 flag 8.4

Packing 12.3 Parity 12.4

flag 12.5 POP 6.4 Pseudo operations 3.4,11.5 PUSH 6.4

Register addressing 7.2 indirect 7.2

Registers 1.2

Relative addressing 7.2 RES 9.2 RET 3.2, 7.5, 8.5, 12.5 RLO 15.4 Rotate instructions 12.1,12.2 RRO 15.4

SBC 13.2, 13.4 SET 9.2 Signed numbers A.8 Sign flag 5.1 SLA 10.3 SRA 10.2 SRL 10.1 Stack organisation 6.3

instructions 6.4 SUB 8-bit 2.2, 2.3

16-bit 13.2 Subroutine concepts 3.1

mechanism 7.5

Unconditional jumps 4.1 Unpacking 12.3

XOR 11.1, 11.2

Zero flag 5.1

127

appendix a binary and hexadecimal number systems978-1-349-06155-6/1.pdf · appendix a binary and...

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