“optimization of electrical package design and pcb design ......oct. 2002 fdip 2002, monterey, ca...

# 1

Hitachi, Semiconductoru

Oct. 2002

FDiP 2002, Monterey, CA

“Optimization of Electrical Package Designand PCB Design for CSP Age”

Atsushi Nakamura

Assembly Technology Development Dept.,SIC, Hitachi, Ltd. , JAPAN

# 2


Oct. 2002


1313-240pin 1111-256pin2727-256pin2828-208pin

QFPBGA

TypicalDie size

Package Miniaturization (QFP > BGA > CSP)

WLP

FBGA(Fine-pitch BGA)

CSP28mm

(256pin/0.4mm)

MPU for consumer products has been shaping up his body smaller and smaller

# 3


Oct. 2002


Bottleneck for High speed operation : Interconnect Design

SI (Signal Integrity)

PI (Power Integrity)

EMI (Electromagnetic Interference)

Signal

Supply

Supply

[Reflection, Crosstalk, …..]

[SSN]

[Emission]

Driver ReceiverInterconnect

Higher Freq.Operation

# 4


Oct. 2002


Impedance matching at Driver/TML and TML/Receiver

Near End Far End

Driver Receiver

TML

# 5


Oct. 2002


Case 1

Case 2

Case 3

Case 4

200mm 50mm 10mm

Waveform comparison on Termination, TML length

# 6


Oct. 2002


Miniaturization in Digital Consumer Products

“SiP vs SoC”, NIKKEI MICRODEVICES magazine, p65, No.208, Oct. 2002

Mega pixel capture in Less than “half inch”

Flip Chip “SiP”(CPU, CPU/DSP, SDRAM, Flash)

# 7


Oct. 2002






Signal

Supply

Supply


[SSN]

[Emission]



-1.0

0.0

1.0

2.0

3.0

4.0

0.0E+00 4.0E-08 8.0E-08 1.2E-07Time (sec)

Vol

tage

(vol

t)

Quiet Sig.Threshold

Level

Active BUSSignal

# 8


Oct. 2002


Analysis model (Traces, planes, and PKG)

PCB : 4 LayersPKG (BGA): 2 Layers

Total 6 Layers

Analysis Vehicle

BGA package

Evaluation board for SH4(BGA)

LSI Package, BUS traces and V/G plane conductors inPCB should be analyzed in a single model for field solver.

PCB Modeling for Power Integrity Analysis

BUFFER

SDRAM

BUS traces

BUFFERBUFFER BUFFER

SDRAM

CPU

V/G planes

# 9


Oct. 2002


A B

C D

L1eff

L2eff

L1eff=1.35/0.261= 5.17 nH

L1eff= L1 - M = 5.16 nH

A B

C D

L1 =9.81nH

L2 =5.74nH

M= 4.65 nH

(1) Estimation from measured waveform

(2) EM analysis

0 2 4 6 8 100

50

0 2 4 6 8 100

56

-1

∆V=1.35V

∆V= -0.28V

di/dt=0.261A/ns

Time (ns)

Cur

rent

(mA

)V

olta

ge (V

)

“M” between trace and GND plane

L2eff=0.28/0.261= 1.07 nH

L2eff= L2 - M = 1.09 nH“ECTAS” analysis

# 10


Oct. 2002


SSN evaluation point

Quiet(Low)

Time(sec)

SSN waveform extraction at low frequency operation

Switching 63 I/O tracessimultaneously

# 11


Oct. 2002


Time (sec) Time (sec)

Comparison between measured and simulated waveform

Vol

tage

(V)

SSN evaluation point

Quiet(Low)

Switching 63 I/Otraces simultaneously

# 12


Oct. 2002


Quiet(Low)

(1) CPU (driver)

(3) BUFFER(2) SDRAM

Time(sec)

SSN waveform difference obtained at different point on the quiet trace

# 13


Oct. 2002


Peak voltage increase proportional to trace length

0.0

0.2

0.4

0.6

0.8

1.0

0 20 40 60 80 100

SH4

SDRAM

BUFFER

Trace length from driver (mm)

SSN

pea

k vo

ltage

(V)

Simulation

Experiment

Initial SSN voltage(package inductance)

Additional part(crosstalk)

Quiet(Low)

(1) CPU (driver)

(3) BUFFER(2) SDRAM

# 14


Oct. 2002


Package dominant and PCB dominant region

Cross talk part is dominant on BUS system using low inductance packages(Less than 1nH)

LSI package inductance (nH)

Crosstalk

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.1 1.0 10.0

SSN induced byPackage inductance

Total SSN

CSP package

Eac

h no

ise

peak

vol

tage

(V)

# 15


Oct. 2002






Signal

Supply

Supply


[SSN]

[Emission]



-1.0

0.0

1.0

2.0

3.0

4.0

0.0E+00 4.0E-08 8.0E-08 1.2E-07Time (sec)

Vol

tage

(vol

t)

Quiet Sig.Threshold

Level

Active BUSSignal

# 16


Oct. 2002


Low noise assembly Basicsq Minimize voltage fluctuation around CPU by Supply decouplingq Increase current supply from DeCap (B) and decrease current from

main Power supply (A)q Current ratio A/C represents effectiveness of DeCaps

Chip

Module

Package

CPG

Measuring point (VDE method)

A C

B

DeCap

Main Pwr. supply

Example of multiple Vcc/Vss microExample of multiple Vcc/Vss micro

# 17


Oct. 2002


Noise current measurementq Noise current can be measured by 1 ohm (VDE) probeq Decoupling effect of Caps can be evaluated by w/ and w/o comparison

VccVss

VccVss

VDE Methodmeasuring point

LSI

Chip

(1) VDE Method

IC

Vcc

49ohm

1ohm 50ohmin

S.A.

# 18


Oct. 2002


Decoupling evaluation board

q Investigation for supply decoupling

Current measurement point (Vcc, PVcc, Vss) Pads for Inductor

Pads for Capacitors

Capacitors

Ferrite Bead

# 19


Oct. 2002


Supply Decoupling using Ferrite-Bead

Ferrite Bead

VCC

GND

Capacitor I/Ocurrent

Core current

Capacitor

Pwr plane

Gnd Plane (w/o slit)

Slit (moat)

0

10

20

30

40

50

60

70

0 2 4 6 8 10 12 14 16 18 20

# of capacitors

Noi

se c

urre

nt (d

BuV

)

Caps.

Caps + F.Bead

@ 80MHz

-20dB

Target Level

# 20


Oct. 2002


SH7055R(QFP) Supply Decoupling Evaluation

@ 80MHzBlack bars represent current direction

Cap(t12) Cap(t12)+ FBRef : No Cap

Compare the level of“RF current” in supply lines

# 21


Oct. 2002


Four-axis Near Field Scanner

http://www.hitachi.co.jp/HDEV/products/production/emi2/

# 22


Oct. 2002


h=2.5mm

NF-Probe evaluates Fwd/Bkdcurrent balance in PCB

L op_R op

Additional Resister (470ohm)

L 470_R op L 470_R 470

Line width=1.3mm

Termination(50 ohm)

1/10

1/10C Point out the location generating

Common mode current

Far field field strength estimation

# 23


Oct. 2002


Ref. Symmetric Asymmetric

@100MHz

Narrow & Asymmetric Ref. plane effect

MSL

pitch : 5mm Scan hight : 10mmScanned from bottom side (Ref. plane)

100MHz (Sinusoidal)Vp-p:1.0 volt input applied

terminated

# 24


Oct. 2002


Ref.

pitch : 5mm Scan hight : 10mmScanned from bottom side (Ref. plane)

@100MHz

Narrow & Asymmetric Ref. plane effect

100MHz (Sinusoidal)Vp-p:1.0 volt input applied

Symmetric Asymmetric

# 25


Oct. 2002


Pitch : 2mm, Height : 5mm (above board)

@80MHz

“QFP vs WLP” Current distribution [ NF-probe scan]

Scanned Area[w/o Cap] [w/ Cap]

SH7055R

: Decoupling Capacitor

QFP

WLP

# 26


Oct. 2002


[w/o Cap] [w/ Cap]

Conducted emission “QFP vs WLP” [ VDE method]SH7055R

QFP

Vcc 12 CapsPVcc 14 Caps

FMFMWLP

Vcc 11 CapsPVcc 12 Caps

FMFM

Higher emissionover 250MHz

# 27


Oct. 2002


Inductance comparison “QFP vs WLP”

BGA

27mm

27m

m

CSP

10mm

10m

m

QFP

40mm

28m

m

(Leff)

Wire partRest of wire part

Total

2.0 - 3.0nH5.0 - 8.5nH

7.0 - 11.5nH

2.0 - 3.0nH2.0 - 3.5nH

4.0 - 6.5nH

-0.7 - 2.5nH

0.7 - 2.5nH

QFP BGA CSP

(1.8 - 2.2nH)(0.8 - 1.2nH)

(2.6 - 3.4nH)

Pwr/Gnd

10nH

Single Two conductor in parallel

(10nH+8nH) x 1/2 = 9nH Mutual inductance

# 28


Oct. 2002


Decoupling Capacitor connection [QFP vs BGA]

qTypical DeCap connection for QFP is better than BGAqV/G plane is closer to Vcc/Vss pin than DeCaps

q Needs treatment to reducecurrent flow from V/G plane

Vcc

Vss

LSI

Wire(2-4nH)

Lead frame(8-14nH)

Vcc

Vss

Wire+ via(2-5nH)

Via + ball(1-2nH)

[ QFP package + PCB ] [ BGA package + PCB ]

A

BDeCap position A or B

PCB

LSIPCB

Vcc/Vss planeVcc/Vss plane

[1]

[2]

[1]

[2]

# 29


Oct. 2002


Decoupling capacitors for BGA27mm

Topside (BGA mount) Bottom side

BGA

# 30


Oct. 2002


Cost effective Low ESL Capacitors

“IDC” type capacitor Feed through (Three terminal)Conventional SMD

No extra Path!100% supply must be fed through

# 31


Oct. 2002


-10

0

10

20

30

40

50

60

70

80

0 100 200 300 400 500 600 700 800 900 1000

Frequency [MHz]

Noi

se [d

BµV

]

w/o DeCaps8 DeCaps(T)NFM21

One Feed Through(1mF)

8 DeCaps(0.1mF*8)

VDE measurement point

VDE Measurements

BGA

All DeCaps :bottom side

NFM21DeCaps (Vcc)DeCaps (PVcc, AVcc)

Feed through Capacitor (BGA)Near Field Scan [Macro (Sensitive) probe] @80MHz SH7055R (40MHz)

BGA 256p-20dB

# 32


Oct. 2002


Feed through Capacitor (QFP)

12 DeCaps(0.1mF*12)

Near Field Scan [Macro (Sensitive) probe] @80MHz

VDE measurement point

SH7055R (40MHz)

NFM21DeCaps (Vcc)DeCaps (PVcc, AVcc)

-10

0

10

20

30

40

50

60

70

80

0 100 200 300 400 500 600 700 800 900 1000

Frequency [MHz]

Noi

se [d

BµV

]

w/o DeCaps12 DeCapsNFM21

VDE Measurements

QFP

QFP 256p-20dB

One Feed Through(1mF)

# 33


Oct. 2002


Current distribution [Simulation/ECTAS]

No Decoupling Capacitor

@80MHz One feed-through capacitor

7 traditional Capacitors

- 20dB

- 40dB

50

140dBuA/m

# 34


Oct. 2002


Effectiveness of Feed-through capacitor [ Exp. vs Sim.]

0

10

20

30

40

50

60

70

80

0 50 100 150 200

NONE(Exp.)NONE(Sim.)GMR(Exp.)GMR(Sim.)NFM21(Exp.)NFM21(Sim.)

Frequency (MHz)

Noi

se C

urre

nt(d

BuA

)

Conducted emission reduction capability “Conventional” vs “Feed through”

No Caps

Seven Traditional Caps

One Feed-through Cap

Current distribution at this frequency was shown in the previous slide

# 35


Oct. 2002


Radiation from External BUS

[SH4+SDRAM] demoboard(4L)(HJ940001BP) equivalent

Scanned plane : above 5mm from chip surface

MCM (HJ940001BP)

Area and Level of RF currents can be reduced by using SiP --> Low radiation chance from PCB

CommonScale

Current Direction PlotScanned plane : above 5mm

from board surfaceMCM

@ 81.0MHz (Ext BUS Freq)

Current Direction Plot

Prog Exec (same prog for Demo board and MCM)

ScannedAre

# 36


Oct. 2002


Summary

q Short trace interconnection (in SiP) solves most of the SI concern

q V/G plane analysis takes more important role for CSP age system

q Reduced EMI design is base on “Supply decoupling.” (for Single chip MPU)

q NF-Scanner shows us locations generating “Common mode” current

q Direct connection to V/G plane for CSP (BGA) is not recommended

q Feed-through Capacitor is a good solution for CSP’s decoupling

saving space, great decoupling capability, making sense (cents)

q PCB design locating RF current trace adjacent to Gnd (return) path

reduces emission. (ex. FC-SiP)

“optimization of electrical package design and pcb design ......oct. 2002 fdip 2002, monterey, ca...

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