“em-circuit co- design solution for high-speed memory … · port1 port2 ff1136_package1 io...

“EM-Circuit Co- Design Solution for

High-speed Memory Applications”Presenter:Ansoft Corporation

Nexxim ® : Co-Design Environment with IC chip, PCB module, Socket/Connector and System Board

Mother Board

DIMM Socket

VRM

Decap. model

Memory I/O circuit model

Controller I/O circuit model

VRM model

EM-based Circuit Co-design Enables First-Pass Memory System Success

OutlineHigh Speed Memory System– First-Pass Memory System Success– Design Issues

High Speed Memory System Analysis– SSN/Eye Analysis Example– Impedance Analysis Example (DDR3 RDIMM)

Introducing: Memory system virtual test wizard– SSN/ Eye Diagram Analysis

Summary

Tuning & Optimization(in worst cast condition)

First-Pass Memory System Success

System Design-Performance-Topologies-Feasibility-DFM-Spice simulation

ManufactureTest& Meas.

EM based model (Connector/PCB) + Circuit : Full Channel simulation

First Pass

SSN, Jitter, SkewTDRDecap. tuningCavity resonanceEMI

Achieve First-Pass high-speed memory system success with full channel simulation

Design Suite

for High-speed Memory Applications

Nexxim® : Design environment for memory systems– Frequency and time domain circuit analysis– Co-simulation and dynamic link– Optimization and Tuning

SIwaveTM : PCB and Package EM analysis and modeling– S-parameter extraction for bus lines– Export SPICE sub-circuit

(HSPICE or Full-wave s-element model)

HFSSTM : Connector and Socket EM analysis and modeling

Introduction : What is High-speed Memory ?

Synchronous DRAM

XDR DRAM

Direct RDRAM

GDDR-2,3,4

SGRAM

RLDRAM-I,-II,-III

DDR4 SDRAM

DDR3 SDRAM

DDR2 SDRAM

DDR SDRAM

SDR SDRAM

Network FCRAM (Network DRAM, DDR FCRAM)

Consumer FCRAM

High-speed Memory system

Design Issues:

Speed– Fundamental frequency increase => more SI/PI issues

(Mismatch, ISI, Cross-talk, EMI)

533Mbps/pin

667Mbps/pin

800Mbps/pin

‘07 ‘08 ‘09 ‘10 ‘11‘06

DQ BusSpeed

‘05

DDR2

DDR3 -> 2007: 2.8%, 2008: 19%, 2009: 40%

High-Speed Memory System

1066~1600Mbps/pin

DDR3

1.6~3.2Gbps/pin

DDR4

Design Issues:

PowerSupply power decrease => more PI issues (Power Noise)

Power (Vcc) DDR2 :

DDR3 :

DDR4 :

V tolerance

Time


1.8V1.5V

1.2V

∆V: 180mV

∆V: 150mV

∆V: 120mV

Design Issues at each part

JitterSkewOn-chip PDN

Lumped model ?

-> S-para. Based model (freq. depend. Factor)

Cavity resonanceDecap. tuning EMI

Chip Package Module System

DDR3 RDIMMCavity Resonance

High-speed Memory system


Design Issues :

Board level -

Via Stub effect

Back Drilling : remove the unused portion of PTHVia Stub Effect


Design Issues :

Board level -

Via Pad size effect

Pad Size Effect : Capacitive Pad-stripping


Design Issues :

3D Interconnection

– 3D interconnects are critical for high-speed design

Connector,Socket

Cable Cable Launch


Design Issues:

Wide data buses SSN/SSO– Power/Ground SSN will cause:

• Logic failure, Timing delay/skew, Coupling to signal line, EMI– How to analyze the complex Power/Ground plane ?

H

L

ΔiSSN = Δi1 + Δi2 + Δi3 …+ ΔinChip

Ground plane

Power plane

…………

…………

Data Buses

Vd

Vg


SSN coupling to signal via (reference changing via)

SSN coupling to signal trace (strip line)

VDD

VDDGND

GND

signal

SDRAMControl IC

Id

Id

: I/O Driver Current

Vd

Vg

Design Issues: SSN coupling to signal lineHigh-Speed Memory System

– SSTL18: Stub-Series Terminated Logic for 1.8 Volts (DDR2, JEDEC interface standard)

• SSTL18 specifies 13.4mA into a 25 Ω

load• tS is the minimum time interval within which a valid signal must meet

VIH(AC) or VIL(AC)

RS

RT

VSS

VDDQ (1.8V) VTT : 0.5 x VDDQ (0.9V)

20Ω

25Ω

Driver Receiver

V IH(DC) : 1,025mV (VREF +125mV)

VREF : 900mV Data Valid Window

Skew SkewDQSDQ0-7

V IH(AC) : 1,150mV (VREF +250mV)

V IL(AC) : 650mV (VREF -250mV)V IL(DC) : 775mV (VREF -125mV)

DDR2 SSTL18 dc and ac Input Logic LevelsTypical driver environment for SSTL18

tS


Design Issues: Termination scheme

FWS model for bus channelFWS model : SPICE model ensures wide band accuracy (Full Wave)S-parameter model vs. HSPICE format model from SIwave FWS export

S21, S11 comparison :S-par. model vs. FWS model (HSPICE format)

Frequency dependent parameterHave to consider :

Conductor loss– Skin Effect

Dielectric constant and loss– Djordjević-Sarkar model

( ) ( ) ( )

0

ln)ln( ωε

σωωωω

ωωεε

ωεωεωε

jjj

j

A

B

AB

+⎟⎟⎠

⎞⎜⎜⎝

⎛++Δ

+=

′′+′=

∞

Relative Permittivity

4.4

4.6

4.8

5

5.2

5.4

5.6

1.E+00 1.E+02 1.E+04 1.E+06 1.E+08 1.E+10

Frequency (Hz)Er

Debye modelMeasurementDjordjevic-Sarkar

log(f)

log R(f)

fRacdcR

Frequency dependent models are default in SIwave

High-speed Memory system Analysis Example

SSN/Eye Analysis Example

Xilinx Virtex5 ML523 Board [1]

Micron DDR2 Memory [2]

SSN/Eye Analysis Example

Xilinx Virtex5 ML523 Board Region for SSN/Eye Analysis

Clip Design in SIwave

DDR2 Nets & PowerDDR2 signal nets and Power nets on clipped design

FPGA:Xilinx Vertex-5

Control I/O Power: Vcc (1.8V)

Memory I/O Power: VDD DDR2 (1.8V)

DDR2 Memory:Micron MT47H16M16BG-3:B

Ports setup for SSN/Eye Analysis36Ports setup for SSN/Eye Analysis– Ports for Data line : DQ0-15– VRM Ports : Vcc1v8 net, Vdd_DDR2 net– Power Ports : Vcc1v8 net, Vdd_DDR2 net

Automatic Ports generation in SIwave

Ground Pin groupVcc1v8 Pin group

SIwave FWS Export S-Y-Z-parameter setup– Discrete 0~5GHz, 501 point sweep for transient analysis

Full Wave SPICE Sub-circuit setup– HSPICE format

Nexxim Schematic for SSN/Eye Analysis

SSN/Eye Analysis Schematic– PCB model : HSPICE format model from SIwave FWS export – Driver/Receiver : SSTL18_II , IBIS I/O buffer model– Package sub-circuit– PRBS logic and DC source for VTT termination

00

00

00

00

00

00

00

000

0

00

00

00

00

00

00

00

0

0

0 0 0 0 0 0 0 0

00000000

00000000

000000000

DDR_D0-R_U11-G8

DDR_D0_U1-F29DDR_D1-R_U11-G2DDR_D1_U1-E29

DDR_D2-R_U11-H7DDR_D2_U1-R29



DDR_D5-R_U11-H9

DDR_D5_U1-T31DDR_D6-R_U11-F1DDR_D6_U1-T29

DDR_D7-R_U11-F9DDR_D7_U1-T28

DDR_D8-R_U11-C8DDR_D8_U1-U28

DDR_D9-R_U11-C2

DDR_D9_U1-U27DDR_D10-R_U11-D7DDR_D10_U1-R27

DDR_D11-R_U11-D3DDR_D11_U1-R26

DDR_D12-R_U11-D1DDR_D12_U1-T26

DDR_D13-R_U11-D9DDR_D13_U1-U26

DDR_D14-R_U11-B1

DDR_D14_U1-T25DDR_D15-R_U11-B9DDR_D15_U1-U25

U1_U1_VCC1V8_Group_U1_GND_GroupU11_U11_VDD_DDR2_Group_U11_GND_Group

VCC1V8VDD_DDR2

V193

V226

50

R288

V291

50

R294

R295

R296

50

R302

50

R303

R304

R305

50

R306

50

R307

R308

R309

50

R31

0 50

R31

1

R31

2

R31

3

V340 V341 V342

V343V344V345V346

V352 V353 V354 V355

V356 V357 V358 V359

Port1 Port2

U2FF1136_Package

Port1 Port2

U3FF1136_Package

Port1 Port2

U4FF1136_Package

Port1 Port2

U5FF1136_Package

Port1 Port2

U6FF1136_Package

Port1 Port2

U7FF1136_Package

Port1 Port2

U8FF1136_Package

Port1 Port2

U9FF1136_Package

Port1 Port2

U10FF1136_Package

Port1 Port2

U11FF1136_Package

Port1 Port2

U12FF1136_Package

Port1 Port2

U13FF1136_Package

Port1 Port2

U14FF1136_Package

Port1 Port2

U15FF1136_Package

Port1 Port2

U16FF1136_Package

Port1 Port2

U17FF1136_Package

Port1 Port2

U18DDRII_package

0

0

Port1 Port2

U19DDRII_package

0

Port1 Port2

U20DDRII_package

0

Port1 Port2

U21DDRII_package

Port1 Port2

U22DDRII_package

0

Port1 Port2

U23DDRII_package

0

Port1 Port2

U24DDRII_package

0

0

Port1 Port2

U25DDRII_package

Port1 Port2

U26DDRII_package

0

Port1 Port2

U27DDRII_package

0

Port1 Port2

U28DDRII_package

0

0

Port1 Port2

U29DDRII_package

Port1 Port2

U30DDRII_package

0

Port1 Port2

U31DDRII_package

0

Port1 Port2

U32DDRII_package

0

0

Port1 Port2

U33DDRII_package

VV

V

Driver IBIS Controller IC Package sub-circuit

PCB model

PRBS logic input

DDR2 Package sub-circuit Receiver IBIS

Vdd 1.8V

VTT 0.9V

SSN results and Jitter noise by SSN

13.00 13.50 14.00 14.50 15.00 15.50 16.00 16.50 17.00Tim e [ns ]

-0.50

0.00

0.50

1.00

1.50

2.00

2.50

Y1

[V]

Ansoft Corporation SSO_16agrXY Plot 1

m1m2

Curve Info

V(Vcc18)Transient

V (vin)Transient

V (Vcc18)1Imported

V(vin)1Imported

V(Vcc18)2Imported

V(vin)2Imported

Name Delta(X)

d( m1 ,m2 ) 0.0264

Name Time

m1 14.7724

m2 14.7988DQ driver out signal

Vcc 1.8V

Δt : 26.4p

Green : 1 I/O SwitchingBlue : 8 I/O SwitchingRed : 16 I/O Switching

ΔV : 0.51V

Vdd tolerance SPEC : ± 100mV

SSN coupling to signalSwitching noise coupling to signal

Received signal with SSO

Received signal without SSO

Noise signal with SSO on silent net

SSN

DQS Lines Skew AnalysisDQ,DQS include meander lines for delay and skew

Schematic for DQS lines skew analysis

DQS Lines Skew Analysis ResultsSkew Analysis results for DQS0-7– DQS3 line show larger skew than others

10.00 10.50 11.00 11.50 12.00 12.50 13.00Time [ns]

0.40

0.60

0.80

1.00

1.20

1.40

Y1 [V

]

Ansoft Corporation DQS_skewXY Plot 1

m2m1Name Delta(X)

d(m1,m2) 0.1805

Curve Info

V(V_DQS0_outTransient





Name X

10.00 10.50 11.00 11.50 12.00 12.50 13.00Time [ns]

0.40

0.50

0.60

0.70

0.80

0.90

1.00

1.10

1.20

1.30

1.40

Y1 [V

]

Ansoft Corporation DQS_skewXY Plot 1

m1 m2

Curve Info

V(V_DQS0_out)Transient







V(V_DQS7_out)TransientName X Y

m1 11.3501 0.8950

m2 11.5306 0.8966

Name Delta(X)

d(m1,m2) 0.1805

DQS3 net has 2 more vias

Skew Analysis ResultsWhy DQS3 line show large skew than others ?

Rs

DQ0

DQS0

DQS#

DQS, DQ Line Timing and Slew Rate Analysis

DQS, DQ point-to-point connection:– Controller IC Package – Via – Line – Via – Rs – Via – Line – Via –

SDRAM Package– Driver and Receiver buffer model , C_comp, L_pkg, R_pkg, C_pkg

Nexxim IBIS buffer model : Controller IC Input/Output

Packagesub-circuitC_comp

DDR2 PKG and buffer model

Nexxim Schematic for DQS, DQ lines timing and slew rate analysis

00

00

0

0

0 0

0

Port1 Port2

FF1136_Package1

io

pullup

pulldown

logic_in

enable out_of_in

IN

POWER

GND

OUTPort1 Port2

DDRII_package

Port1 Port2

DDRII_package

IN

POWER

GND

OUT

V

0.9V

DDR_D0-R_U11-G8DDR_D0_U1-F29

DDR_DQS0#-R_U11-E8DDR_DQS0#_U1-P30

DDR_DQS0-R_U11-F7VCC1V8_U1 VDD_DDR2_U11

VCC1V8 VDD_DDR2

DDR_DQS0_U1-P31io

pullup

pulldown

logic_in

enable out_of_in

Port1 Port2

FF1136_Package

0

0

0

V

IN

POWER

GND

OUTPort1 Port2

DDRII_package

0

V

00

00

io

pullup

pulldown

logic_in

enableout_of_in

Port1 Port2

FF1136_Package1

Controller IC Packagesub-circuit

DDR2 Packagesub-circuit

DQS, DQ Line Timing and Slew Rate Analysis

8.00 9.00 10.00 11.00 12.00 13.00 14.00 15.00Time [ns]

0.00

0.50

1.00

1.50

2.00

2.50

3.00

Y1 [V

]

Ansoft Corporation DQS_DQ_slewrateXY Plot 3

m1

m2

m3

m4m5

m6m7 Curve Info

dqs0_outTransient

dqs0_out_diffTransient

V(V_DQ0_out)Transient

Name X Y

m1 9.7184 0.6401

m2 10.8811 0.7816

m3 10.9468 0.9084

m4 11.0890 1.1576

m5 12.0175 1.0337

m6 12.0917 0.8909

m7 9.5872 0.9012

tDS tDH tDS tDH

DQS0

DQS0#

DQ0

VREF(DC)VIL(DC)MAX

Timing and Slew Rate Analysis

VIL(AC)MAX

VIH(DC)MIN

VIH(AC)MIN

∆TR ∆TF

tDS : Data setup time , tDH : Data hold timeSlew rate rising signal = [VREF(DC) – VIL(DC)MAX] /∆TRSlew rate falling signal = [VIH(DC)MIN – VREF(DC)] /∆TFSlew rate load : 25ohm between Vout and VTT

Slew rate falling : 1.92 V/ns722ps439ps

317ps 612ps

Slew rate rising : 1.93 V/ns

Slew rate load

Offset

Nexxim Eye Diagram PlotTransient Result

Eye Diagram

Cut and Fold(2 unit interval)

Unit Interval= 0.5Tr + PW + 0.5Tf

0 .0 0 5 .0 0 1 0 .0 0 1 5 .0 0 2 0 .0 0 2 5 .0 0 3 0 .0 0 3 5 .0 0 4 0 .0 0 4 5 .0 0 5 0 .0 0T im e [n s ]

-0 .2 5

0 .7 5

1 .7 5

Y1

[V]

A n s o ft C o rp o ra t io n S S O _ 1 a g rX Y P lo t 1

2* Unit interval

Plotting Range

Plotting RangeEye Plotting Range of Transient Results

Transient ResultsPlotting Range : 0~10us Plotting Range : 10~20us

Vdd with Switching Noise

DDR2 DQ0 ReceivedUnexpected Startup Behavior

Add Eye MaskEye Mask– Edit Eye Mask– Export/ Import Mask file

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50Time [ns]

0.40

0.60

0.80

1.00

1.20

1.40

V(V

_DD

R_D

0-R

_U11

-G8)

[V]

12.38Time [us]

0.40

0.90

1.40

V(V

_DD

R_D

0-R

_U11

-G8)

[V]

10.00 15.00

Ansoft Corporation Nexxim1XY Plot 3

Curve Info

V(V_DDR_D0-R_U11-G8)Transient

Nexxim Eye Diagram Plot

DDR2 Data Valid window

Jitter Histogram sampling across Y-value

Jitter Histogram

X scroll bar

Transient Results

Add Eye MeasurementsAll Eye measurements can be displayed

High-speed Memory system Analysis Example

Impedance Analysis Example (DDR3 RDIMM)

DDR3 Memory Module PDNPower Distribution Network Design for DDR3 memory module

– Should be considered with Main board PDN impedance– Should meet the Vdd noise SPEC : ±

75mV (Vdd=1.5V)– Vdd noise is transferred to Vref– Need Freq. domain optimization (de-cap. Tuning) with P/G

Impedance Plot

DIMM Decoupling CapacitorDIMM decoupling capacitor :– Affect at range of ~150MHz

DIMMMB Chip

Impedance profile for DDR_VDD nets

Mother board PDN can be modeled by equivalent Capacitor which has series R/L

VRM

Equivalent circuit for Mother Board’s Power plane and VRM

DDR3 RDIMM PDN Analysis

VDD pin group on DIMM connector

GND pin group on DIMM connector

What If ? De-Cap. Change

Mouse drag.VDD decoupling Capacitor (32EA)

De-Cap. Tuning– Case1 : 0.01uF (34EA, VDD De-cap.)– Case2 : 0.1uF (34EA, VDD De-cap.)– Case3 : 0.47uF (34EA, VDD De-cap.)

Case1 :0.1uF 34EA VDD decap.

What If ? De-Cap. ChangeCase2:0.01uF 34EA VDD decap.

Case3:0.47uF 34EA VDD decap.

Introducing: Memory System Virtual Test Wizard

(Ansoft PCB Design Suite Wizard)

APDS Wizard DemoSSN & Eye-Diagram

for High Speed Memory Data Bus

Simulation TargetMemory Controller

DDR2 MemoryChecking data Lines: Controller IC-to-DDR2 Memory

it’s a critical path for High-Speed Memory

Previously …

1.

PCB S/Y/Z parameter Simulation SPICE Model Extraction

2.

Import SPICE modelAssign port name at each pin

3.

Apply package models..Check up IBIS files..Set up IBIS buffer models..

4.

Copy & paste & modify…repetition, repetition …

6.

Setup simulation….Analyzing….make Report….

5.

Assign Vdd & GND…Attach voltage probe…Routing…

Previously, these steps were completed Previously, these steps were completed manuallymanually…… Huk.. Huk..

And..

Manual RepetitionManual Repetition

ItIt’’s ans anOld Type !Old Type !

Now!

Automationusing

APDS Wizard

PCB LayoutPCB Layout SimulationSimulationResultResult

JUMP UP !JUMP UP !“

What you have to check up ” “

What you want ”

Automation ProcessLayout ImportLayout Import

(Automatic) Port Assign(Automatic) Port Assign

S/Y/Z parameter SimulationS/Y/Z parameter Simulation

SPICE model ExtractionSPICE model Extraction

Schematic DesignSchematic Design-- SPICE model ImportSPICE model Import

-- IBIS buffer Model SettingIBIS buffer Model Setting-- Package Parasitic SettingPackage Parasitic Setting

-- VDD/GND SettingVDD/GND Setting-- Termination SettingTermination Setting

-- Voltage probe SettingVoltage probe Setting-- Wiring Wiring

Transient SimulationTransient Simulation-- SSN & EYE DiagramSSN & EYE Diagram

ReportReport

Ansoft Link

SIwave

Ansoft Designer/ Nexxim

Automation!Automation!Using VBscript & Visual Basic

Save Time,Save Time,Eliminate Steps!Eliminate Steps!

What is VB Script?

Array("NAME:ComponentProps", "Name:=", "IbisInput4", "Id:=", _"5", Array("NAME:CellLayerMerger", "DrawLayers:=", Array("Measures:Measures", _"Rats:Rats", "Errors:Errors", "Symbols:Symbols"))), Array("NAME:Attributes", "Page:=", _1, "X:=", -0.01016, "Y:=", 0.00508, "Angle:=", 0, "Flip:=", false)

oEditor.CreateComponent Array("NAME:ComponentProps", "Name:=", "IND_", "Id:=", "6", Array("NAME:CellLayerMerger", "DrawLayers:=", Array( _"Measures:Measures", "Rats:Rats", "Errors:Errors", "Symbols:Symbols"))), Array("NAME:Attributes", "Page:=", _1, "X:=", -0.01778, "Y:=", 0.00508, "Angle:=", 0, "Flip:=", false)

oEditor.CreateComponent Array("NAME:ComponentProps", "Name:=", "Res_", "Id:=", "7", Array("NAME:CellLayerMerger", "DrawLayers:=", Array( _"Measures:Measures", "Rats:Rats", "Errors:Errors", "Symbols:Symbols"))), Array("NAME:Attributes", "Page:=", _1, "X:=", -0.02794, "Y:=", 0.00508, "Angle:=", 0, "Flip:=", false)

oEditor.CreateComponent Array("NAME:ComponentProps", "Name:=", "Cap_", "Id:=", "8", Array("NAME:CellLayerMerger", "DrawLayers:=", Array( _"Measures:Measures", "Rats:Rats", "Errors:Errors", "Symbols:Symbols"))), Array("NAME:Attributes", "Page:=", _1, "X:=", -0.03302, "Y:=", 0, "Angle:=", 4.71238898038469, "Flip:=", false)

oEditor.CreateGround Array("NAME:GroundProps", "Id:=", 18), Array("NAME:Attributes", "Page:=", _1, "X:=", -0.03302, "Y:=", -0.00762, "Angle:=", 0, "Flip:=", false)

oEditor.CreateGround Array("NAME:GroundProps", "Id:=", 23), Array("NAME:Attributes", "Page:=", _1, "X:=", -0.01016, "Y:=", 0, "Angle:=", 0, "Flip:=", false)

oEditor.CreatePagePort Array("NAME:PagePortProps", "Name:=", "pageport_0", "Id:=", _28), Array("NAME:Attributes", "Page:=", 1, "X:=", -0.04064, "Y:=", 0.00508, "Angle:=", 0, "Flip:=", false)

oEditor.CreateWire Array("NAME:WireData", "Name:=", "", "Id:=", 32, "Points:=", Array( _"(-0.040640, 0.005080)", "(-0.033020, 0.005080)")), Array("NAME:Attributes", "Page:=", 1)

IBIS Model

Inductor

Resistor

Capacitor

GND1

GND2

PagePort

Wire

• All Design Processes can be reproduced and modified by Visual Basic Script

Port Assignments on PCB Line

2. Just Select PCB lines

to simulate.SIwave will automatically generate the ports

1.

Import

layout data & component information to SIwave

ThatThat’’s ALLs ALL that you have to do…

APDS WizardSSIIwave file Loadingwave file Loading

IBIS file LoadingIBIS file Loading

IBIS Component &IBIS Component &Model SelectionModel Selection

Port AssignPort Assign

Add TerminationAdd TerminationCheck Probe PointCheck Probe Point

Simulation SettingSimulation Setting

You don’t need simulation skill.

Just Use.

Step #1 –

SIW Loading

1. Load the SIwave file with pre-assigned ports

2. Input the data speed of memoryto decide the sweep range of S parameter simulation

3. Check this option for S parameters simulation & SPICE extraction using SIwave

Step #2 –

IBIS File Analysis

APDS wizard contains Intelligent IBIS file Analysis Engine

Major functions ofMajor functions of

IBIS file Analysis EngineIBIS file Analysis Engine

• Extract all package models (Components) at each pin.

• Extract Typical & Min & Max R/L/C parasitic for each component

• Model selector listing & auto-mapping with models

• Extract all model information such as model_type, VDD/GND clamp…

• Automatic composite IBIS buffer model name for Nexxim at each model

• Intelligent Handling for IBIS file with off-standard format (IBIS rule check engine)

Step #2 –

IBIS File Analysis

IBIS file path Component (Package Model)

Model name

Just select what you need!Components, Model Selector, Model

IBIS file Analysis

Click!

Model Selector

Step #2 –

IBIS File Analysis

When a model name is selected ,IBIS file analysis engine checks the model_type & clamp condition of that pin in the IBIS fileand then composes the model type for the Nexxim simulation at the same time.

Ex) pin model : SSTK18_II

Model_type in IBIS file : I/OClamp : exist at VDD & GND node

Needs I/O with ClampI/O with Clamp type buffer.automatically generate model name “ibisIO8” for IBIS model of Nexxim

Model type generation for Nexxim simulation

Step #2 –

IBIS File AnalysisIBIS File Information

Main information of the IBIS file is presented in the APDS wizard

Component description, package models, model type, signal name of each pin …

Note: Don’t open & read IBIS file with text editors such as Notepad, VI, etc.

Step #3 –

Port Assignments

1. When you read SIwave file(*.siw) , All PCB ports will load to Open Port List

2. You can move ports to any port list from open port

by clicking GetGet

Button

Termination PortVDD - SSN node

GND

VDD Supply

IBIS Driver output

IBIS Receiver input

Very Simple & Easy

Step #3 –

Port Assignments

3. Return the ports to open port listby clicking “ < “ button

4. Select termination type

5. If it’s needed, add external termination to all receiver portsby clicking the “Copy from Receiver” button once.

All ports in each list can be checked at once by clicking the port name (toggle)

Step #3 –

Port Assignments

Check the box adjacent to any port whose voltage is to be plotted.A probe will appear next to all selected ports.

AutoProbing

Step #3 –

Port AssignmentsAutomatch

Just 1 Click!

The Automatch option will assign all Driver & Receiver ports at once,by checking the SIwave port name and pin name in the IBIS file.

Last Step –

Optional Setting

1. Select function to automate. 2. Setup simulation conditions. 3. Run!

All Systems Go !

Wizard Start!

• PCB Line S/Y/Z SimulationSPICE model Extraction

2. SPICE Model Import

3. Schematic Generation4. Transient Simulation &

Report

AUTOMATIC !AUTOMATIC !

Automatic Schematic Generation

It doesn’t matter!

Too many ports,

Very complex circuit,

Different package model at each pin …

Simply watch the animation of the schematic being generated

IBIS models in NEXXIM

APDS Wizard APDS Wizard can generate a schematic can generate a schematic for any IBIS model type in NEXXIMfor any IBIS model type in NEXXIMuusing the sing the Adaptive Schematic Generation Engine.Adaptive Schematic Generation Engine.

R/L/C Package models

individually assigning different R/L/C parasitics to each pin/port is time consuming & prone to error.

It’s very important at high speeds to apply accurate package models.

Now, the APDS Wizard allowsR/L/C parasitics to be applied rapidly and accurately.

However,

Note: If the IBIS file doesn’t have exact parasitic information for each pin,the APDS Wizard will extract typical parasitic values from the IBIS fileand will automatically apply these to all R/L/C components.

0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00Time [ns]

-0.50

0.00

0.50

1.00

1.50

2.00

2.50

3.00

Y1 [V

]

Ansoft Corporation Nexxim1XY Plot 1Curve Info

V(DDR_D0_U1-F29)Transient

V(DDR_D0-R_U11-G8)Transient

V(SSN_Driver)Transient

Simulation Result -

SSNSSNSSN

0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00Time [ns]

-1.00

-0.50

0.00

0.50

1.00

1.50

2.00

2.50

3.00

Y1

[V]


V(V_DDR_D0-R_U11-G8)TransientAll portsAll ports

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50Time [ns]

0.40

0.60

0.80

1.00

1.20

1.40

1.60

V(V

_DD

R_D

0-R

_U11

-G8)

[V]

0.00 20.00 40.00 60.00 80.00 100.00Time [ns]

0.40

1.40


V(V_DDR_D0-R_U11-G8)Transient

Eye-Diagram

Automatic Simulation & Eye-Diagram Report

EM-based circuit co-design- Through examples, it was shown how simulation technology may be used to

address several current, high-speed memory design challenges and, ultimately, to identify optimal first-pass designs. Specifically, we focused on:Signal noise analysis : Jitter, Eye-Diagram : Power noise : SSN

The Ansoft PCB Design Suite Wizardfor Eye/SSN analysis was introduced.

Summary

References[1] UG225 (v1.1) August 6, 2007, ML52x user guide, www.xilinx.com[2] Micron DDR2 SDRAM data sheet,

http://download.micron.com/pdf/datasheets/dram/ddr2/256MbDDR2.pdf

[3] Hynix DDR2 SDRAM data sheet, http://www.hynix.co.kr/datasheet/pdf/dram/HY5PS124(8_16)21C(L)FP(Rev0.6).pdf

[4] Tom Granberg, “Handbook of Digital Techniques for High-speed Design”, Prentice Hall, pp. 156-160 and Part 3.

http://www.xilinx.com/

http://download.micron.com/pdf/datasheets/dram/ddr2/256MbDDR2.pdf

http://www.hynix.co.kr/datasheet/pdf/dram/HY5PS124(8_16)21C(L)FP(Rev0.6).pdf

“em-circuit co- design solution for high-speed memory … · port1 port2 ff1136_package1 io...

Documents