ansi ieee std 991 (1986)

ANSI/IEEE Std 991-1986

An American National Standard

IEEE Standard for Logic Circuit Diagrams

Sponsor

IEEE Standards Coordinating Committee 11, Graphic Symbols and Designations

Approved March 21, 1985

IEEE Standards Board

Approved April 25, 1985

American National Standards Institute

Copyright 1986 by

The Institute of Electrical and Electronics Engineers, Inc

345 East 47th Street, New York, NY 10017, USA

No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without theprior written permission of the publisher.

Acceptance Notice

This non-Government document was adopted on 5 June, 1986, and is approved for use by the DoD. The indicatedindustry group has furnished the clearances required by existing regulations. Copies of the document are stocked byDoD Single Stock Points, US Naval Publications and Forms Center, Philadelphia, PA 19120, for issue to DoDactivities only. Contractors and industry groups must obtain copies directly from IEEE, 345 East 47th Street, NewYork, NY 10017.

NOTICE: When reafrmation, amendment, revision, or cancellation of this standards is initially proposed, the industrygroup responsible for this standard shall inform the military coordinating activity of the proposed change and requestparticipation.

Title of Document:

IEEE Standard for

Logic Circuit Diagrams

Document No:

ANSI/IEEE Std 991-1986

Date of Specific Issue Adopted:

27 June, 1986

Releasing Industry Group:

The Institute of Electrical and Electronics Engineers, Inc.

Custodians: Military Coordination Activity:

Army -- AR Amry -- AR

Navy -- SH Project DRPR-0260

Air Force -- 13

Review Activities:

Army -- AV, MI, AM, CR, ER

Navy -- OS, AS

Air Force -- 11, 15, 17

User Activities:

Army -- AT

Navy -- MC

iii

IEEE Standards documents are developed within the Technical Committees of the IEEE Societies and the StandardsCoordinating Committees of the IEEE Standards Board. Members of the committees serve voluntarily and withoutcompensation. They are not necessarily members of the Institute. The standards developed within IEEE represent aconsensus of the broad expertise on the subject within the Institute as well as those activities outside of IEEE whichhave expressed an interest in participating in the development of the standard.

Use of an IEEE Standard is wholly voluntary. The existence of an IEEE Standard does not imply that there are no otherways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of the IEEEStandard. Furthermore, the viewpoint expressed at the time a standard is approved and issued is subject to changebrought about through developments in the state of the art and comments received from users of the standard. EveryIEEE Standard is subjected to review at least once every ve years for revision or reafrmation. When a document ismore than ve years old, and has not been reafrmed, it is reasonable to conclude that its contents, although still ofsome value, do not wholly reect the present state of the art. Users are cautioned to check to determine that they havethe latest edition of any IEEE Standard.

Comments for revision of IEEE Standards are welcome from any interested party, regardless of membership afliationwith IEEE. Suggestions for changes in documents should be in the form of a proposed change of text, together withappropriate supporting comments.

Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecic applications. When the need for interpretations is brought to the attention of IEEE, the Institute will initiateaction to prepare appropriate responses. Since IEEE Standards represent consensus of all concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. For this reasonIEEE and the members of its technical committees are not able to provide an instant response to interpretation requestsexcept in those cases where the matter has previously received formal consideration.

Comments on standards and requests for interpretations should be addressed to:

Secretary, IEEE Standards Board345 East 47th StreetNew York, NY 10017USA

iv

Foreword

(This Foreword is not a part of ANSI/IEEE Std 991-1986, IEEE Standard for Logic Circuit Diagrams.)

The contributors to this standard represent a broad range of institutions, technologies, and documentation needs. Theyinclude industrial, governmental, and educational organizations, producers and consumers of devices and equipment,users and nonusers of computer-aided design and drafting, and a range of aesthetic preferences. That a consensus ofsuch diverse interests could be achieved in producing this standard is indicative of a need for a common practice in thiseld.

Work on this standard started in 1972, in an ad-hoc working group on Logic Diagrams, under the preparing group forY14.15, Electrical Diagrams. Work was suspended for several years while the International ElectrotechnicalCommission, Technical Committee 3 developed Publication 117, Part 7. to which the United States contributed. In1982 a new subcommittee was formed, operating as part of the IEEE Standards Coordinating Committee for GraphicSymbols and Designations, SCC 11. It decided to prepare a new draft incorporating:

1) The 1975 draft of the original working group,2) IEC Publication 113, Part 7. insofar as practical (in the present standard, some parts and illustrations are very

similar to the IEC document; differences and additions result from new developments in symbols for logicfunctions and new perceptions of current needs), and

3) Such parts of ANSI Y14.15-1968 (R 1973) as applied to logic circuit diagrams, but with updating to removeduplication of requirements found in referenced standards and to apply the material explicitly to logic circuitdiagrams.

After ten drafts the present document was completed and submitted to the IEEE Standards Board for approval.

The following persons were on the balloting committee that approved this document for submission to the IEEEStandards Board:

Standards Coordinating Committee on Graphic Symbols and Designations, SCC 11

R. B. Angus, JrJ. C. BrownG. A. KnappC. R. Muller

John PeatmanJ. W. SeifertT. R. SmithS. V. Soanes

R. M. SternL. H. WarrenS. A. Wasserman

Subcommittee on Logic Circuit Diagrams, SCC 11.10

T. R. Smith

, Chair

C. R. Muller,

Acting Secretary

R. W. AndrewsR. B. Angus, JrJohn BalogR. R. BartaL. BurnsL. A. CiskowskiL. Davis *P. H. EnslowC. D. Fisher E. R. FlemingA. C. GannettJ. J. George

A. HendryW. R. HolbrookG. A. KnappJ. A. KohlmeierJ. M. KreherF. A. MannD. MartinecJ. MassaroR. P. MayerJ. F. MorrongielloE. L. NesbittV. T. Rhyne M. R. Richter

R. R. RitterJ. P. RussellR. SandigeL. E. SchulzR. M. SternR. D. StuartM. E. Taylor R. TobiasJ. VargoL. H. WarrenJ. WilliamsR. J. Yuhas

* Liaison AFLC / MM APD Liaison Y14 Resigned Liaison DoD

v

At the time this standard was approved on March 21, 1985, the IEEE Standards Board had the following membership:

John E. May

, Chair

John P. Riganati

, Vice Chair

Sava I. Sherr

, Secretary

James H. BeallFletcher J. BuckleyRene CastenschioldEdward ChelottiEdward J. CohenPaul G. CummingsDonald C. FleckensteinJay Forster

Daniel L. GoldbergKenneth D. HendrixIrvin N. Howell, JrJack KinnJoseph L. Koepfinger*Irving KolodnyDonald T. Michael*R. F. Lawrence

Lawrence V. McCallFrank L. RoseClifford O. SwansonJ. Richard WegerW. B. WilkensCharles J. Wylie

*Member emeritus

vi

CLAUSE PAGE

1. Introduction .........................................................................................................................................................1

1.1 Purpose....................................................................................................................................................... 11.2 Scope.......................................................................................................................................................... 1

2. Applicable Documents ........................................................................................................................................1

2.1 Industry Standards...................................................................................................................................... 12.2 Military Standards...................................................................................................................................... 22.3 International Standards .............................................................................................................................. 2

3. Definitions...........................................................................................................................................................3

4. General Requirements.........................................................................................................................................4

4.1 Content ....................................................................................................................................................... 44.2 Drawing Size and Format .......................................................................................................................... 44.3 Diagram Titles............................................................................................................................................ 54.4 Diagram Revisions ..................................................................................................................................... 54.5 Lettering ..................................................................................................................................................... 54.6 Lines........................................................................................................................................................... 54.7 Abbreviations ............................................................................................................................................. 64.8 Letter Symbols ........................................................................................................................................... 64.9 Layout and Presentation............................................................................................................................. 6

5. Logic Conventions and Polarity Indication ........................................................................................................7

5.1 Relationship Between Logic States and Logic Levels............................................................................... 75.2 Single Logic Convention ........................................................................................................................... 85.3 Direct Polarity Indication........................................................................................................................... 8

6. Symbols for Devices and Functions....................................................................................................................9

6.1 Standard Symbols ...................................................................................................................................... 96.2 Size........................................................................................................................................................... 146.3 Orientation ............................................................................................................................................... 146.4 Application and Identification Information ............................................................................................. 176.5 Inputs and Outputs with Multiple Functions............................................................................................ 196.6 Abbreviated Representation of Symbols.................................................................................................. 216.7 Abutment of Symbols .............................................................................................................................. 236.8 Detached Representation of Symbols ...................................................................................................... 236.9 Unused Terminals and Elements.............................................................................................................. 246.10 Devices Having a Large Number of Terminals ....................................................................................... 24

7. Interconnection of Symbols ..............................................................................................................................25

7.1 General Requirements.............................................................................................................................. 257.2 Line Spacing ............................................................................................................................................ 267.3 Junctions and Crossovers ......................................................................................................................... 267.4 Interrupted Lines ...................................................................................................................................... 277.5 Grouping of Lines .................................................................................................................................... 287.6 Polarity and Negation Matching .............................................................................................................. 287.7 Power Connections .................................................................................................................................. 29

vii

CLAUSE PAGE

8. Labeling of Connecting Lines...........................................................................................................................29

8.1 General ..................................................................................................................................................... 298.2 Names for Logic and Analog Signals ...................................................................................................... 298.3 Names for Power and Other Constant-Level Connections ...................................................................... 378.4 Locator Information ................................................................................................................................. 378.5 Additional Properties and Characterization ............................................................................................. 38

9. Supplementary Information ..............................................................................................................................38

9.1 Reference-Designation Accounting ......................................................................................................... 389.2 Diagram Notes ......................................................................................................................................... 389.3 Tabular Information ................................................................................................................................. 409.4 Waveforms ............................................................................................................................................... 409.5 Diagram Simplification and Abbreviation Techniques............................................................................ 42

10. Examples of Logic Diagrams............................................................................................................................49

Annex A Mnemonics for Use in Signal Names (Informative) .....................................................................................60

Annex B Lines and Lettering Size and Spacing (Informative) ................................................................................72

Annex C Single Orientation of Lettering (Informative) ...............................................................................................82

Copyright 1986 IEEE All Rights Reserved

1

An American National Standard

IEEE Standard for Logic Circuit Diagrams

1. Introduction

1.1 Purpose

The purpose of this standard is to provide standard practices and information for use in the preparation of diagramsdepicting logic functions.

1.2 Scope

This standard provides guidelines for preparation of diagrams depicting logic functions. It includes denitions,requirements for assignment of logic levels, application of logic symbols, presentation techniques, and labelingrequirements with typical examples. The techniques are presented in the context of electrical/electronic systems, butalso may be applied to nonelectrical systems (for example, pneumatic, hydraulic, or mechanical).

2. Applicable Documents

2.1 Industry Standards

The latest editions of the following industry documents form a part of this standard to the extent specied herein:

American National Standards

ANSI X3.4-1977, American National Standard Code for Information Interchange.

1

ANSI X3/TR-1-1983, American National Standard Dictionary for Information Processing.

ANSI Y1.1-1972 (R 1984), American National Standard Abbreviations for Use on Drawings and In Text.

1

ANSI publications are available from the Sales Department, American National Standards Institute, 1430 Broadway, New York, NY 10018.

2


ANSI/IEEE Std 991-1986 IEEE STANDARD FOR

ANSI Y14.1-1980, American National Standard Drawing Sheet Size and Format.

ANSI Y14.2M-1979, American National Standard Line Conventions and Lettering.

ANSI Y14.15-1966 (R 1973), American National Standard Electrical and Electronics Diagrams (includesSupplements ANSI Y14.15a-1971 and ANSI Y14.15b-1973 ).

ANSI/IEEE Std 91-1984, IEEE Standard Graphic Symbols for Logic Functions.

2

ANSI/IEEE Std 100-1984, IEEE Standard Dictionary of Electrical and Electronics Terms.

ANSI/IEEE Std 194-1977, IEEE Standard Pulse Terms and Denitions.

ANSI/IEEE Std 200-1975, IEEE Standard Reference Designations for Electrical and Electronics Parts and Equipment.

ANSI/IEEE Std 260-1978 (R 1985), IEEE Standard Letter Symbols for Units of Measurement (SI Units, CustomaryInch-Pound Units, and Certain Other Units).

ANSI/IEEE Std 280-1985, IEEE Standard Letter Symbols for Quantities Used in Electrical Science and ElectricalEngineering.

ANSI/IEEE Std 315-1975, Graphic Symbols for Electrical and Electronics Diagrams (Including ReferenceDesignation Class Designation Letters).

2.2 Military Standards

The latest edition of the following Department of Defense document forms a part of this standard to the extentspecied herein and shall be used for DoD contracts in place of the equivalent Industry Standards listed above:

MIL-STD-12, Military Standard Abbreviations for Use on Drawings, Specications, Standards, and in TechnicalDocuments.

3

2.3 International Standards

This standard is compatible (except as noted) with the following publications:

IEC Publication 113 (1971 - 1983), Diagrams, Charts, Tables.

4

ISO 31/1-1978, Quantities and Units of Space and Time.

5

ISO 646-1983, 7-bit Coded Character Set for Information Processing Interchange.

2

IEEE publications are available from IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854.

3

MIL publications are available from Superintendent of Documents, US Government Printing Office, Washington, DC 20402.

4

IEC publications are available in the United States from the Sales Department, American National Standards Institute, 1430 Broadway, New York,NY 10018, USA. The IEC publications are also available from International Electrotechnical Commission, 3, rue de Varemb, Case postale 131,1211Genve 20, Switzerland/Suisse.

5

ISO publications are available in the United States from the Sales Department, American National Standards Institute, 1430 Broadway, New York,NY 10018, USA. ISO publications are also available from the ISO Office, 1, rue de Varemb, Case postale 56, CH-1211, Genve 20, Switzerland/Suisse.


3

LOGIC CIRCUIT DIAGRAMS ANSI/IEEE Std 991-1986

3. Definitions

The following denitions are for use with this standard. For other use and for denitions not contained herein, seeANSI/IEEE Std 100-1984 .

6

graphic symbol:

A gure, mark, or character conventionally used on a diagram, document, or other display torepresent an item or a concept.

logic symbol:

A graphic symbol that represents a logic function.

qualifying symbol:

A graphic symbol added to another to provide additional information. For a logic element, agraphic symbol added to the basic outline to designate the overall logic characteristics of the element or the physicalor logic characteristics of an input or output of the element.

negation bar:

A line over a signal label that indicates logic inversion of that signal.

element:

As used within this standard, a representation of all or part of a function within a single outline, which may,in turn, be subdivided into smaller elements representing subfunctions of the overall function. Alternatively, thefunction so represented.

logic circuit diagram:

A circuit diagram that predominantly uses symbols for logic functions to depict the overallfunction of a circuit.

basic logic diagram:

A logic circuit diagram that depicts, in simple form, the intended function of a circuit. It doesnot necessarily contain constructional or engineering information, nor does it represent exactly the nal physicalform.

detailed logic diagram:

A logic circuit diagram that depicts, in detail, a circuit as actually implemented. It containsinformation that can be used for manufacturing or maintenance purposes, but it does not necessarily includeengineering information that is not concerned with logic functions.

logic state:

One of two possible abstract states that may be taken on by a logic (binary) variable.

0-state:

The logic state represented by the binary number 0 and usually standing for an inactive or false logiccondition.

1-state:

The logic state represented by the binary number 1 and usually standing for an active or true logic condition.

logic level:

Any level within one of two nonoverlapping ranges of values of a physical quantity used to represent thelogic states.

NOTE A logic variable may be equated to any physical quantity for which two distinct ranges of values can be dened. In thisstandard, these distinct ranges of values are referred to as logic

levels

and are denoted H and L.

H is used to denote the logic level with the more positive algebraic value, and L is used to denote the logic level withthe less positive algebraic value.

In the case of systems in which logic states are equated with other physical properties (for example, positive ornegative pulses, presence or absence of a pulse), H and L may be used to represent these properties or may bereplaced by more suitable designations.

high (H) level:

A level within the more positive (less negative) of the two ranges of the logic levels chosen torepresent the logic states.

low (L) level:

A level within the more negative (less positive) of the two ranges of logic levels chosen to representthe logic states.

signal state:

The logic state corresponding to the truth-value of the statement or expression represented by a signalname.

6

When reference is made to any publication throughout this standard the user should refer to Section 2. for the full title and location of availability.

4



logic conventions and polarity indication

positive logic convention:

The representation of the external 1-state and the external 0-state by the high (H) and low(L) levels, respectively.

negative logic convention:

The representation of the external 1-state and the external 0-state by the low (L) and high(H) levels, respectively.

direct polarity indication:

The indication of the relationship between the internal logic state and the external logiclevel at each input and output of the every logic element directly by means of the presence or absence of the polaritysymbol ( ).

4. General Requirements

4.1 Content

4.1.1 Basic Logic Diagram

This diagram shall show the conceptual principles of a circuit. It shall include as a minimum the required logicsymbols and other necessary functional symbols, together with their signal and major control path connections. Otherinformation such as waveforms, formulas, and algorithms may be included. Physical location, pin connection, andassembly level information are usually omitted.

4.1.2 Detailed Logic Diagram

This diagram shall show the information necessary for manufacture, installation, maintenance, and training for a logiccircuit or system. It shall include as a minimum:

1) Graphic symbols for logic functions and other devices (see Section 6.)2) Connections among symbols (signal, control, and power) (see Section 7.)3) Reference designations (see 6.4.1.1)4) Terminal identication (see 6.4.1.5)5) Signal-level conventions applicable to the diagram: positive or negative logic, logic states or levels (for

example, H and L) (see Section 5.)6) Information necessary to trace paths and circuits among sheets of the diagram (see 7.4)

4.1.3 Combined Forms of Circuit Diagrams

Provided that approved standards are followed, diagrams combining logic circuit information with conventionalschematic (mechanical, or electrical) diagram information may be prepared.

4.2 Drawing Size and Format

Drawing sizes and formats used with diagrams shall conform to ANSI Y14.1-1980 . In general, the smallest standardformat compatible with the nature of the diagram should be selected. See also Appendix 11..

4.2.1 Drawing Zones

On logic diagrams with many logic elements, it is often helpful to have a coordinate system to permit referencingparticular areas or zones on the sheet (see ANSI Y14.1-1980). This is especially helpful when many sheets arerequired and cross references between sheets are numerous. Signal tracing is expedited if reference can be made fromone point in a diagram to both sheet and zone of another point.


5


4.2.2 Supplemental Drawing Number Location

If a diagram is reproduced for an instruction book or similar purposes and the title block is not retained, it may bedesirable to include the original drawing number within the reproduced area. This drawing number (if included)should be shown close to the lower right edge of the reproduced area in a lettering size comparable to that used fornotes and other detailed reference material.

4.3 Diagram Titles

The title of the diagram should include the name of the circuit or equipment followed by the diagram type. Forexample: MEMORY CONTROLLER, MODEL 1134 CIRCUIT DIAGRAM.

4.4 Diagram Revisions

Provision shall be made on all logic circuit diagrams for recording revisions. The record of changes made in eachrevision shall be identied

7

by either a number, letter or character, and the date of the revision. When it is possible tomake a brief detailed explanation of the revision, this is desirable. When a detailed explanation is not practicable, anote covering the general nature of the revision should be included. A reference to a change order document may beshown in lieu of an explanation.

4.5 Lettering

Lettering style, size, spacing, and legibility shall conform to ANSI Y14.2M-1979 .

NOTE Lettering height and spacing affect symbol size and overall layout of diagrams. See Appendix B for guidelines includingthose applying to diagrams that are used both as a part of the engineering drawing set and in technical manuals.

4.5.1 Orientation

All lettering within a diagram shall be readable from no more than two orientations of the diagram, 90

apart.

8

4.6 Lines

Line width and quality shall be such that, after reproduction of the diagram at the required size, all lines shall be legibleand without breaks. For detailed recommendations concerning line width, see Appendix B.

Thick lines may be used for general use (including symbols and connecting lines) and for lettering. Thin lines shouldbe approximately half the width of the thick lines.

If emphasis of special features, such as main or transmission paths, is essential, an extra-thick line, approximatelytwice the width of thick lines, may be used to provide the desired contrast.

Line conventions for use on logic circuit diagrams are shown in Fig 1.

7

For US Department of Defense applications, the identification shall be an uppercase letter, used in alphabetical sequence, omitting the letters I, O,Q, S, X, and Z.

8

For special IEC requirements, see Appendix 11..

6



Figure 1Line Conventions for Diagrams

4.7 Abbreviations

For rules applying to connecting-line labels, see Section 8. Other abbreviations used on diagrams shall conform toANSI Y1.1-1972 (R 1984).

9

If the term is not included in ANSI Y1.1-1972 (R 1984), an abbreviation given in otherstandards recognized as National Standards may be used. If no suitable abbreviation exists, a special abbreviation maybe used, but shall be explained by a note on the diagram.

4.8 Letter Symbols

Letter symbols for units of measurement shall conform to ANSI/IEEE Std 260-1978 (R 1985).

Letter symbols for quantities used in electrical science and electrical engineering shall conform to ANSI/IEEE Std280-1985.

4.9 Layout and Presentation

4.9.1 Coverage

A logic diagram, which may consist of several sheets, should be prepared for each distinct unit, or assembly of units,intended to fulll a dened purpose. It may thus relate to a single unit or to several units that together form a functionalentity. In cases where the logic diagram cannot be shown on a single sheet, the division into separate sheets should bebased on the purpose of the diagram.

4.9.2 Planning

Basic logic diagrams are prepared primarily for design engineers. It is possible, in many cases, for the basic diagramto be converted to a detailed diagram simply by adding the required labeling. If this can be foreseen, the basic diagramshould initially be laid out with sufcient space left both inside and outside of the symbols to accommodate futurelabeling.

9

See also 2.2.


7


4.9.3 Signal Flow

The principal direction of signal ow should be from left to right or, alternatively, from top to bottom. Flow directionmay be indicated by the orientation of symbols, logic polarity symbols, or ow arrowheads, or by a convention ofunidirectional ow suitably noted. Regardless of the convention used, the signal ow shall be clearly indicated. Theow arrowhead is a small arrowhead superimposed upon data lines or control lines. The ow arrowhead shall not touchany part of the symbol.

4.9.4 Layout

The layout shall be such that the main features are prominently shown. The parts should be spaced to provide an evenbalance between blank spaces and lines. Sufcient blank area should be provided in the vicinity of symbols to avoidcrowding of information. Functionally related symbols should be grouped (see 4.9.5) and placed as close to oneanother as the requirements of annotation and the avoidance of overcrowding will allow. Large spaces should beavoided, except that space provision may be made for anticipated circuit additions.

The logic diagram shall use a layout that follows the circuit, signal, or transmission path either from input to output,source to load, or in the order of functional sequence. Long interconnecting lines between parts of the circuit shouldhe avoided. Similar basic circuits should be drawn in a similar form (this does not prevent the use of simpliedrepresentation to depict repeated circuits).

Where practical, signal ow lines should begin and terminate at the outer edge of the sheet. If this is not practical,references to the terminations may be made by the use of drawing zones.

4.9.5 Grouping of Symbols

If a circuit contains symbols that need to be shown grouped, the grouping may be indicated by means of a boundary(phantom) line enclosure (see Fig 1). The phantom line enclosure may be omitted if sufcient space is providedbetween groups. Typical groupings are by function or by physical location (for example, unit assemblies,subassemblies, printed circuits, integrated circuits, sealed units). Labeled brackets may be used in place of a boundaryline to identify functional groups of symbols if there is sufcient space between groups, so that confusion is unlikelyas to which group any symbol belongs. The dashed line used to indicate shielding also implies that the symbolsenclosed by the dashed line are grouped (see Figs 31 and 32).

5. Logic Conventions and Polarity Indication

5.1 Relationship Between Logic States and Logic Levels

When logic symbols are used to represent physical devices, it is necessary to establish the relationship between logicstates and the nominal values (logic levels) of the physical quantities used to represent these states. There are twomethods by which this may be done:

1) The use of the symbol for logic negation and requires the adoption of a single logic convention, eitherpositive or negative, for the whole diagram (see 5.2)

2) The use of direct polarity indication in which the presence or absence of the logic polarity symbol indicates the required relationship between logic level and internal logic state at each input and output ofevery logic symbol on the diagram (for direct polarity indication, see 5.3).

8



5.2 Single Logic Convention

With this method the correspondence between a given external logic state and logic level is the same at all inputs andoutputs on the diagram.

The symbol for logic negation shall be used as required to dene the relationship between the

external

logic state andthe

internal

logic state. Specically the presence of the logic negation symbol at an input or output signies that theinternal and external states are the complements of one another for that terminal. The absence of the logic negationsymbol signies that the internal and external states are the same for that terminal. The symbol for logic polarity shallnot be used with this method.

The convention in use, either positive logic or negative logic (see 5.2.1 and 5.2.2), shall be clearly stated on thediagram or in referenced documentation. This statement can include a useful, small waveform diagram withindications of the logic states and, if necessary, of the nominal value of corresponding physical quantities.

NOTE Different logic conventions may be used for different parts of the same diagram; for example, on either side of aninterface between contrasting technologies the convention applying to each part should be clearly shown and theareas of the diagram to which each applies should be clearly delineated.

5.2.1 Positive Logic Convention

For every logic connection, the more positive value of the physical quantity H-level corresponds to the external 1-state.The less positive value L-level corresponds to the external 0-state. This may be stated on a diagram thus:

See Fig 31 for an example of a diagram using positive logic.

5.2.2 Negative Logic Convention

For every logic connection, the less positive value of the physical quantity L-level corresponds to the external 1-state.The more positive value H-level corresponds to the external 0-state. This may be stated on a diagram thus:

5.3 Direct Polarity Indication

With this method the relationship between the internal logic state and the external logic level of each input and outputof every logic element is indicated directly by means of the presence or absence of the logic polarity symbol .Specically, the presence of the polarity symbol at an input or output indicates that the external low level correspondsto the internal 1-state for that terminal. The absence of the polarity symbol signies that the external high levelcorresponds to the internal 1-state for that terminal. No relationship between an external logic state and either aninternal logic state or an external logic level is dened by the symbol. A relationship between the external logic leveland a signal state is dened only by the signal name (see 8.2.2.1).

In this system the symbol for logic negation shall notbe used, except within a symbol outline as permitted by ANSI/IEEE Std 91-1984

.


9


Direct polarity indication has been called

mixed logic

implying that both positive and negative logic are present on adiagram using that method. This is misleading since the xed relationship between logic levels and external logicstates inherent in a single logic convention does not exist with direct polarity indication. Therefore, the term

mixedlogic

is deprecated.

For diagrams prepared with direct polarity indication but showing no logic polarity symbols, a statement indicatingthat direct polarity is employed shall be placed on the diagram or in referenced documentation.

6. Symbols for Devices and Functions

6.1 Standard Symbols

Graphic symbols shall conform to the following applicable standards: ANSI/IEEE Std 91-1984 and ANSI/IEEE Std315-1975 .

If no suitable standard symbol exists, any special symbol used shall be explained by a note on the diagram.

The use of a symbol in the illustrations of this standard does not preclude the use of alternatives permitted by thegraphic symbol standards.

6.1.1 Symbols for Logic Elements

Each logic element should be shown by the symbol that best depicts actually the logic function performed by theelement in the system. Thus, in Fig 31, the same type of hardware element is represented once by the symbol for an ORelement with negated inputs (designated U4D) and elsewhere by the symbol for AND element with negated output(NAND) (designated U4B and U4C).

6.1.2 Distributed Connections (Dot-AND, Dot-OR)

The connection of certain logic elements to achieve the effect of an AND or an OR operation without the use ofadditional logic elements shall be depicted using the symbols shown in ANSI/IEEE Std 91-1984 .

There are two basic methods for showing the distributed-AND function and two basic methods for showing thedistributed-OR function. In each case, the rst method uses one of the usual methods of showing a junction with theaddition of either a qualifying symbol or a surrounding distinctive-shape symbol to denote the logic performed.Method 2 replaces the junction with a rectangle containing the & or 1 qualifying symbol appropriate to the ANDor OR function, respectively. This qualifying symbol is followed by the qualifying symbol indicating that the logicis performed by a distributed connection instead of by a separate element.

10 Copyright 1986 IEEE All Rights Reserved


Method 2 permits the use of qualifying symbols for negated inputs and negated outputs with positive and negativelogic, and for the polarity indicator with direct polarity indication. These are used with the rectangular symbol in thesame manner that they are used if the logic were performed by discrete logic gates with one exception: all the inputsand the outputs shall show the same qualifying symbol since a distributed connection cannot be inverting.

Method 1 does not lend itself to the use of the input and output qualifying symbols. Therefore, to understand the logicperformed by the distributed connection, it is necessary to consider the types of outputs that are connected together.

L-type open-circuit outputs (for example, n-p-n open collectors) connected together perform either active-highANDing or active-low ORing. H-type open-circuit outputs (for example, n-p-n open emitters) connected togetherperform either active-high ORing or active-low ANDing. See Fig 2. For denitions of open-circuit outputs, see ANSI/IEEE Std 91-1984 .

Copyright 1986 IEEE All Rights Reserved 11


Figure 2Distributed Connections



Figure 2Distributed Connections (continued)



Figure 2 assumes that the same negation symbols or polarity symbols can be appropriately used at the driving outputsand the driven inputs. This is the recommended practice; however, sometimes it is not possible to follow this practiceat all points in a diagram. The presence or absence of negated output or active-low output qualifying symbols does notinuence which type of logic, AND or OR, applies. In Fig 3 the AND and the OR representations are equivalent.

Figure 3Distributed Connections with a Mix of Negated and Unnegated Outputs (Positive Logic Shown)

The same principle applies for direct polarity indication. In Fig 4 the AND and the OR representations are equivalent.

Figure 4Distributed Connections with a Mix of Active-High and Active-Low Outputs



6.2 Size

In most cases, the meaning of a symbol is dened by its form and contents. The size and the line thickness do not, asa rule, affect the meaning of the symbol.

In some cases, it may be desirable to use different sizes of symbols to

1) Emphasize certain aspects, or2) Facilitate the inclusion of additional information

Logic symbol size should be governed by the space necessary for internal annotations and the length of the side neededto accommodate input and output lines at an acceptable spacing. In Fig 5 a binary logic AND element symbol is shownat the left as specied in ANSI/IEEE Std 91-1984 . The symbol at the right has been increased in size to facilitate theaddition of pin numbers, designations, and other application information.

Figure 5Enlargement of Symbol Outline to Accommodate Application Information

Graphic symbols may be drawn to any proportional size that suits a particular diagram, provided the selection of sizetakes into account the anticipated reduction or enlargement. On any printed document, nonlogic symbols should be nosmaller than 0.6 times the size shown in ANSI/IEEE Std 315-1975 . If those symbols are drawn approximately 1.5times the size shown, the resulting drawings may be reduced as much as 2.5 to 1. Detailed recommendations regardingthe size and proportions of logic symbols may be found in ANSI/IEEE Std 91-1984 .

6.3 Orientation

Symbols or parts of symbols that lend themselves to being rotated or mirror imaged may also be manipulated forsimplication of circuit layout, provided

1) Proper orientation of lettering is maintained (see 4.5.1),2) Signal ow on the resultant diagram is generally from left to right or top to bottom, and3) The requirements of ANSI/IEEE Std 91-1984 and ANSI/IEEE Std 315-1975 are met.

The logic symbols contained in ANSI/IEEE Std 91-1984 have been designed for the usual case of inputs on the leftand outputs on the right, and this orientation is preferred.

6.3.1 Orientation of Logic Symbol Lettering

In diagrams where two orientations of the lettering are permitted, all lettering inside a logic symbol including alpha-numeric qualifying symbols should be oriented parallel to the predominant direction of the input and output lines onthe symbol. See Fig 6.10

10For special IEC requirements, see Appendix 11..



Figure 6Logic Symbol Orientation Examples for Diagrams that Permit Two Orientations of Text



Figure 6Logic Symbol Orientation Examples for Diagrams that Permit Two Orientations of Text(continued)



6.3.2 Orientation of Qualifying Symbols Derived from Characteristic Curves

If part of a symbol is derived from the characteristic curve of a device, this part of the symbol shall not be rotated.However, in logic symbols, orientation shall be maintained with respect to the lettering within the symbol. See Fig 7.

Figure 7Orientation of Qualifying Symbols Derived from Characteristic Curves (See NOTE to Fig 6)

6.4 Application and Identification Information

Identication or detailed references within or adjacent to symbols, other than qualifying symbols, indicator symbols,and control symbols, are referred to as application information (tagging lines). See Fig 8.

6.4.1 Types of Application Information

Depending upon the kind of logic diagram and its hardware implementation: all, none, or any combination of the typesof application information that follow may be needed.

6.4.1.1 Reference Designation

Reference designations uniquely identify symbols on a diagram and shall be in accordance with ANSI/IEEE Std 200-1975 and the applicable portion of ANSI/IEEE Std 315-1975. All letters and digits that make up a referencedesignation shall be of the same size and on the same line, with no spaces or hyphens between them. Referencedesignations are required on detailed logic circuit diagrams.

All symbols representing elements contained within the same physical package (device) shall carry the same basicreference designation. If a device is represented by several detached symbols (see 6.8), then each symbol should carrya different alphabetic sufx to the reference designation.

The examples in this standard conform to the Unit Numbering Method of ANSI/IEEE Std 200-1975 .



6.4.1.2 Element Physical Identification (Type Designation, Reference Number, Part Number, Circuit Diagram Number, etc)

In the case of highly complex function elements, the logic element physical identication (type designation, typenumber) may be provided as part of the symbol function information.

6.4.1.3 Physical Location of Device (In the Assembly)

6.4.1.4 Functional Use (Function of Element in the Particular Circuit)

6.4.1.5 Terminal Identification (Required on Detailed Logic Diagrams)

Terminal identication or pin numbers shall be shown outside of and adjacent to the symbol. They may be placedadjacent to the connection line or in a break in the connection line. See Figs 9, 10, and 11 for typical examples. If asingle terminal on the symbol represents a multiplicity of physical device terminals, reference shall be made tosupporting information that provides individual terminal identication.

6.4.1.6 Other Information (Such as Values, Stylized Waveforms, and Pulse and Timing Characteristics)

6.4.2 Application Information Placement

Care shall be exercised to separate application information from qualifying symbols,indicating symbols, and controldesignation symbols. Arrangement and meaning of application information should be consistent on a set of drawings,and should be explained on the diagram or in supporting documentation.

The sequence of application information and identication information should remain the same even if all types ofinformation are not provided; the lines of application information should be compressed, leaving no blank lines.

6.4.2.1 Logic Symbols

The preferred placement of application and identication information for logic symbols is internal to the symbol. Asuggested arrangement of information is shown in Fig 8 (a), (b), and (c). If the information is shown external to thelogic symbol it shall be placed adjacent to the symbol, and should be in the same sequence as if it were internal to thesymbol.

6.4.2.2 Nonlogic Symbols

Application and identication information for nonlogic symbols shall be placed adjacent to the symbol with thereference designation on the rst line and the remaining information provided on succeeding lines in the same order asfor logic symbols on the diagram. See Fig 8 (d) for an example.



Figure 8Application Information: Typical Examples

6.5 Inputs and Outputs with Multiple Functions

Some logic devices have inputs or outputs that serve more than one function. For example, a terminal may be an inputand an output at different times, or an input may be a clock input and a level-operated control input. Multiple-functionterminals may be depicted in the following ways:

1) The individual functions may be shown as separate inputs or outputs tied together outside the symbol outline.



Figure 9Multiple-Function Terminal (Terminal 1) Shown as Separate Lines

This method requires that the terminal identication (pin number) be positioned on or adjacent to thecombined circuit path. This location of the terminal identication indicates that the connection is internal tothe device.

2) If all functions require identical polarity and dynamic symbols and if no ambiguity is likely regarding whichlabels apply to the input and output functions, then a single terminal may be shown and a solidus (/) used toseparate the labels associated with the separate functions.

Figure 10Multiple-Function Terminal (Terminal 1) Shown as a Single Line

3) To simplify a diagram, a multiple-function terminal may be depicted more than once at the symbol outlinewith the terminal identication repeated, provided the requirements of 7.4 are met.

Figure 11Multiple-Function Terminal (Terminal 1) Repeated on Symbol Outline

If necessary to identify repetitive information, this may be done by placing the repeated terminal identication inparentheses or by a special identier explained on the diagram.



6.6 Abbreviated Representation of Symbols

6.6.1 Identical Inputs and Outputs

A set of identical inputs to or outputs from an element (inputs or outputs having identical functions and labels) may beshown in abbreviated form by using the symbol for multiple conductors and a single input or output line at theelement. This technique cannot be used if terminal identiers are required at the symbol.

Figure 12Abbreviated Representation of Identical Inputs and Outputs

6.6.2 Arrays of Identical Elements (See Fig 13.)

An array of identical elements may be indicated in abbreviated form by using the symbol for multipleconductors and the notation mX where m is to be replaced by a number indicating the number of elements in thearray. In the case of logic symbols, this notation shall be placed in the position used for the normal general qualifyingsymbol. If this position is already occupied by a general qualifying symbol, then mX shall be placed in front of thegeneral qualifying symbol.

NOTE Because the elements are identical, the multiple conductors are distributed equally among the elements.

n

n



Figure 13Abbreviated Representations of Arrays of Identical Elements



6.7 Abutment of Symbols

Logic symbols, whether representing elements in the same or different packages may be abutted according to the rulesof ANSI/IEEE Std 91-1984 provided that

1) All required application information is shown2) All connections external to the devices are shown3) Nonexistent internal connections are not implied. See Fig 14.

Figure 14Abutment of Symbols

6.8 Detached Representation of Symbols

Logic symbols may be shown in detached (disassembled) form provided that connections internal to a device areclearly indicated. See also 6.4.1.1.

Internal connections, if necessary to depict the logical relationships, shall be shown as solid connecting lines. Aninternal connection is implied by

1) The omission of terminal identications at the outline of the separated symbol portion,2) Stating IC at the usual terminal identication location, or3) Special identiers explained on the diagram or in a reference document

Connecting lines depicting internal connections may be interrupted provided the requirements of 7.4 are met.



Figure 15Detached Representations of Devices

6.9 Unused Terminals and Elements

Terminals or circuit elements that are not used (for example, inputs, outputs, or complete elements in a multiple-element package) may be shown. If shown, terminal identication shall be included. If reserved for a specic futureuse, the intended use should be indicated.

Any terminal that, if connected, could adversely affect the circuit shall be shown and labeled11 to warn against use.

6.10 Devices Having a Large Number of Terminals

The depiction of complex devices having very large numbers of terminals (for example, hundreds of pins) may beimpractical using techniques applicable to less complex devices. The following possibilities should be considered:

1) Break the main complex device outline into parts. Put each part on a separate sheet of the diagram.2) Break the main complex device into functional groups and detail each group separately.3) Show the main complex device as a reentrant (open-jaw) shape. Place external devices connected between the

terminals of the main device in the reentrant space. Other external connections may be shown around theoutside periphery of the main device.

11Presently published conventions are:ANSI Y1.1-1972 (R 1984) None.IEC Publication 147-OF NU = not usable.MIL-STD-12 DNU = do not use.



4) Group leads and use the Bus or Data Path symbols where practical.5) Tabulate the full details of multilead paths in a separate table.

7. Interconnection of Symbols

7.1 General Requirements

Lines should be drawn horizontally or vertically except in those isolated cases where oblique lines improve the clarityof the diagram. After arranging the symbols on the diagram for functional clarity and symmetry, connecting linesshould be drawn with as few bends and crossovers as possible.

If a signal feeds a multiplicity of elements, the use of a single straight line with appropriate indications of T-junctionsaids comprehension of the diagram. See Fig 16.



Figure 16Diagram Layout

7.2 Line Spacing

Minimum spacing (center-to-center) between parallel connecting lines, shall be approximately twice the letteringheight if there is lettering between the lines. If there is no lettering between the lines the minimum spacing shall beequal to the general lettering height used on the diagram. See 4.6 and Appendix 11.. The longer parallel lines shall bearranged in groups, with approximately double spacing between groups. In determining the grouping, the functionalrelationship of the lines should be considered.

7.3 Junctions and Crossovers

All junctions of connecting lines should be shown as T-junctions, as shown in Fig 17(a), or Fig 17(b). When layoutconsiderations prevent the exclusive use of the T-junction methods of Fig 17(a) or (b), multiple junctions may beshown as in Fig 17(c). Figure 17(d) illustrates the use of both the no-dot T-junction and multiple-junction methods inan array of lines if spacing or clarity of presentation precludes the exclusive use of the no-dot T-junction method ofFig 17(a).



Figure 17Junctions and Crossovers

7.4 Interrupted Lines

Complex diagrams with many crossovers or with many elements in series (see Fig 18) may be simplied by breakingow lines and providing a cross-reference between the interrupted connections. The cross-reference may be by signalnames, common connection symbols, connection tables, or other unambiguous means. If necessary for clarity,reference to the locations (on the diagram) of the related common connections shall be provided.

Figure 18Layout Techniques (a) Complex Presentation (b) Alternative Presentation

The same techniques shall be used for common connections between sheets of multiple sheet drawings.



7.5 Grouping of Lines

The recommendations for grouping and omission of lines given in ANSI Y14.15-1966 (R 1973) apply also to linesrepresenting information ow and connection lines in logic diagrams. The techniques of highway or cable diagrams,ANSI Y14.15-1966 (R 1973) , can be used to simplify logic diagrams where groups of similar signals are encountered.For example, binary coded decimal (BCD) lines 1, 2, 4, 8, 10, 20, 40, and 80 could be combined (see Fig 19), providedthat the individual lines are properly identied at both ends.

Figure 19Grouping of Lines

7.6 Polarity and Negation Matching

The symbols used in an application usually are chosen so that the polarity or negation indication at an input is the sameas that at the source of a signal feeding that input. If this is done, a reader of the diagram can directly apply the internallogic state of an output as the internal logic states of the inputs fed by that output. In the case of direct polarityindication, if the form of the signal name is chosen as described in 8.2.2.2 the signal name, excluding the levelindication, directly expresses the meaning of that internal logic state.

However, it is not always possible to choose symbols so that all the inputs and outputs connected by a signal carry thesame polarity or negation indication. If there is a mismatch between the indication at the source of a signal and theindication at the destination, a reader of the diagram must invert the internal logic state of the source before using it asthe internal logic state of the next input. Because these mismatches are a common source of errors in logic circuitdesign, it can be helpful to clearly indicate where such mismatches (and inversions) intentionally exist. If it is desiredto highlight these mismatches, it should be done using a short perpendicular line (the mismatched symbol) across theconnecting line.



This symbol divides the connection into two segments each of which contains consistent polarity or negationindicators. If the connecting line is branched, one or more symbols should be used to divide the connection tree intoconsistent subtrees.

7.7 Power Connections

Power connections (voltage requirements) to logic devices shall be specied on detailed logic diagrams. Normallyconnections to logic device power terminals (for example, VCC, VBB, GND) are not shown graphically but arespecied in a table or a note.

8. Labeling of Connecting Lines

8.1 General

Labeling of connecting lines can greatly promote the understanding of a diagram and facilitate the maintenance of alogic system, provided that the lines are labeled intelligently and that names are chosen carefully, based on systemfunctions. Each label should be shown adjacent to the line to which it applies or within a break in that line.

8.2 Names for Logic and Analog Signals

Signal names are used to uniquely identify sets of points that are electrically interconnected without interveningdevices.

8.2.1 General Requirements

Signal names should be concise, informative, and unambiguous.



8.2.1.1 Descriptive Requirements

Signal names should indicate the function performed by the signal or the particular information carried. Every effortshould be made to use mnemonic names (see Appendix A) and standard abbreviations (see ANSI Y1.1-1972 (R 1984). The mnemonics and abbreviations used should be explained on the diagram or in supporting documentation. If spacepermits, easy-to-understand mnemonics should be used instead of overly short abbreviations. For example, SELDEV1better conveys the meaning SELECT DEVICE 1 than does SD1. For other examples see Figs 20, 31, and 32.

Signals should be named based on the function they perform rather than on the signals that are used to generate them.If a signal PRUN is gated with a second signal TP6 to produce a signal that sets a bistable element called RUN, thenits function is obvious if the output signal is named SETRUN. However, if the output signal is named PRUNTP6, thenits function is open to speculation. See Fig 20, Example (a).

NOTE Mnemonics and abbreviations based on typical usage in the English language cannot all be translated without risk ofconfusion.

8.2.1.2 Recommended Characters

Signal names should be composed from standard character sets, excluding lowercase letters. Single embedded spacesmay be used where necessary. To maintain compatibility with computer processing, it is recommended that charactersets be restricted to12

8.2.1.3 Length

Practical considerations and design automation systems usually place limits on the allowable length of signal names.Therefore, it is recommended that a maximum length of 24 characters be mutually supported by designers and design-automation systems.

8.2.1.4 Similar and Equivalent Signals

Identical names shall not be applied to different signals, no matter how similar the functions. A signal name shall bealtered whenever the signal is amplied, inverted, gated with another signal, delayed, chopped, stored, or changed inany way. This change may take the form of an addition of a suitable sufx to the signal name so as to construct a newsignal name. For example see Fig 20, Examples (d) and (f).

If the same signal is generated more than once, is amplied, or is level shifted, then each occurrence or variation of thebasic signal should have the same basic name modied by the addition of a different serial number or letter sufx. Theserial number or letter may be concatenated with the basic name or separated from it by a space. For example, if thesignal STOP drives two ampliers, the outputs of those ampliers may be labeled STOP1 and STOP2. For example,see Fig 20, Example (f).

12ISO 646-1983 , 7-bit Character Set (International Reference Version (except for ).ANSI X3.4-1977, 7-bit Character Set (except for - ).

(1) Capital letters A to Z

(2) Digits 0 to 9

(3) Negation characters - ~

(4) Special characters ! " % & ' ( ) * + , - . / : ; < = >

? ^



Figure 20Examples of Signal Name Allocation



If a binary logic signal is simply inverted, then the inverted signal should have the same basic name as the uninvertedsignal, modied by the addition (or deletion) of negation bars (or other negation indication). On diagrams using directpolarity indication, the indicated signal level (see 8.2.2.2) may be changed instead. If a signal is inverted more thanonce, serial numbers or letters should be used to distinguish different inverted or uninverted versions of a signal.

8.2.2 Binary Logic Signals

Binary logic signals are signals having only two states, represented by two nonoverlapping ranges of physical valuesfor the signal. These two ranges are called levels.

8.2.2.1 Signal State

For binary logic signals, the signal name should include an abbreviation of a statement or expression that is either trueor false. For example, the name ALARM is an abbreviation of the statement ALARM IS ACTIVE. A signal name shallnot contain an inherent contradiction. The name ON/OFF consists of two parts, and when one part is true the other isfalse. Such a signal name is ambiguous and might seem to imply a statement that is always true.

The truth value obtained from evaluating the statement or expression represented by the signal name is called thesignal state.

The true value of a statement represented by the signal name corresponds to the 1-state of the signal. The false valueof a statement represented by the signal name corresponds to the 0-state of the signal. For example, the signal nameALARM means that ALARM IS ACTIVE is true when the signal is in its 1-state and false when the signal is in its 0-state. See Table 1, rows 1 and 2.

Table 1Relationships Among States and Signal Names (Single Logic Convention)

Relationship Defined by Presence or Absence of

Negation Symbol

Row Input (or Output) System

Condition

Signal State (Truth-Value)

External Logic State

Internal Logic State

1alarmno alarm

true=1false=0

10

10

2alarmno alarm

true=1false=0

10

01

3alarmno alarm

false=0 true=1

01

01

4alarmno alarm

false=0 true=1

01

10

NOTES:1The signal state being true always corresponds to the external logic state being 1.2The signal state being false always corresponds to the external logic state being 0.



8.2.2.1.1 Negated Signals

Signal names that embody an inherent negative, such as NORUN, are difcult to understand. It requires some mentalsomersaults to say whether the corresponding statement NORUN IS ACTIVE is true or false. If possible, such signalnames should be made inherently true. For example, STOP or HALT could be substituted for NORUN.

However, sometimes an action should take place when a certain statement, or expression, is not true. The preferredmethod of indicating negation of a signal name is to place a negation bar over the portion of the name representing theexpression to be negated. For example, RUN corresponds to the statement RUN IS NOT ACTIVE. Note that the signalname includes the negation bar. The signal name RUN means that RUN IS NOT ACTIVE is true when the signal is inits 1-state and false when the signal is in its 0-state. This further implies that RUN IS ACTIVE is true when the signalRUN is in its 0-state and false when the signal RUN is in its 1-state. See Table 1, rows 3 and 4.

If an in-line notation for negation is required, then the negation bar may be replaced by a preceding mathematicalsymbol for logic negation 13 or a different notation explained on the diagram or in supporting documentation, forexample RUN. If confusion is likely regarding which portion of the signal name is negated, that portion of thesignal name to be negated shall be enclosed in parentheses with the negation symbol placed immediately following theopening parenthesis, subject to the following rule:

The in-line negation symbol applies to the string to the right of the symbol up to the rst occurrence of

1) An unmatched closing parenthesis,2) A solidus that is itself not enclosed within a matching set of parentheses to the right of the negation symbol,

or3) The end of the string.

For example

The tilde (~) may be substituted for the symbol for logic negation on computer systems not having the logic negationsymbol as part of their character sets.8.2.2.1.2 Arithmetic and Logical Expressions

The plus sign (+) denotes algebraic addition and the minus sign (-) denotes algebraic subtraction; for example, AR+1may be the mnemonic for ADDRESS REGISTER PLUS 1.

In signal names the plus sign (+) should be used to denote the OR function only if no confusion with algebraic additionis likely. If the content does not clarify the distinction, an often used solution is to substitute the words OR or PLUS asappropriate in one or both of the cases.

13ISO 31/1-1978 , Symbol 11-2.3.



A logic AND function may be denoted by a dot (), an asterisk (*), or, if no confusion is likely, by normal juxtaposition.For example, ENABLE may be the mnemonic for ENABLE A ANDed with BLOCK E; PQ may mean P ANDed withQ. See also 8.2.1.1.

Parentheses may be used to clarify expressions. For example, (ENA)BLE is another way to indicate the mnemonic forENABLE A ANDed with BLOCK E.

8.2.2.1.3 Bus Signals and Other Grouped Signals

Bit and byte labeling within a bus or other set of grouped signals should include a numeric sufx to the bus or groupname. For buses or groups with an inherent weighting of the signals within, the numeric sufxes should represent theactual weights of the signals, all of which are consistently expressed either as decimal numbers or as exponents of thepowers of 2. The numeric sufx may be enclosed in angle brackets.14 For example, the 32 lines of an intermediateregister may be labeled IRBUS to IRBUS, or IRBUS to IRBUS. A seven line BCDintermediate register should be labeled IRBUS, IRBUS, IRBUS, IRBUS, IRBUS, IRBUS,IRBUS.

Connecting lines representing entire buses, rather than individual signals within them may be labeled as follows:

IRBUS IRBUS, IRBUS, ..., IRBUS

IRBUS IRBUS, IRBUS, IRBUS, ..., IRBUS

If any other convention is used, and the meaning is not obvious, it shall be explained on the diagram or in supportingdocumentation.

For clarity, weighting of individual bits of a bus shall be indicated either in the symbol elements or with the connectinglines. IEC Publication 113-7 (1971-1983) states that connecting lines for buses should be ordered proceeding fromleast signicant to most signicant, from top to bottom, or from left to right. This is the normal result of using logicsymbols for weighted arrays having a common control block on the top or left of the symbol.

8.2.2.1.4 Clock Signals

In signal names for clocks, it is often helpful to include important characteristics such as period (or frequency) andphase. For example, if the basic clock period is 25 ns, the mnemonic might be CP25N. Clocks derived from the basicclock might then be termed CP50N, CP100N, and so on.

The timing pulses from CP50N might be designated as indicated in Fig 21.

8.2.2.2 Signal Level

In detailed logic diagrams employing a single logic convention (positive or negative logic), the relationship betweenthe external logic states of the signals and the corresponding logic levels is xed. For example, if the positive logicconvention is in force, the 1-state of a signal (the true state of the signal name) always corresponds to the H-level. Forthe negative logic convention, the 1-state always corresponds to the L-level.

14 Angle brackets can be formed from the less than () characters.



Figure 21Clock and Timing Pulses

In detailed logic diagrams employing direct polarity indication, the logic symbols do not imply any external logicstate, only logic levels. Therefore, each logic signal name should include an indication of which logic levelcorresponds to the 1-state (true state) of the signal. The preferred method for doing this is to place an indication of thatlogic level (for example, H or L) within parentheses at the end of the signal name.

EXAMPLES:

ALARM(H) means ALARM IS ACTIVE is true when the logic level of the signal is high and is false when the logiclevel is low.

ALARM (H) means ALARM IS NOT ACTIVE is true when the logic level is high and is false when the logic level islow. This further implies that ALARM IS ACTIVE is true when the logic level of the signal is low and false when thelogic level is high. See Table 2 for all combinations.

STOP(L) means STOP IS ACTIVE is true when the logic level of the signal is low and is false when the logic level ishigh.

A signal whose true state corresponds with a high level may be referred to as a true-when-high signal.

A signal whose true state corresponds with a low level may be referred to as a true-when-low signal.

If all signal names on a diagram are true when high, the logic level indications may be omitted from the names.



Table 2Relationships Among States, Levels, and Signal Names (Direct Polarity Indication)

A signal name that can be derived by applying both logic negation and level inversion to an existing signal name isequivalent to the existing signal name and therefore shall not be used to identify a different signal. For example:

STOP(L) = STOP(H)

ALARM(H) = ALARM(L)

RD/WR(H) = RD/WR(L)

Relationship Defined by Presence or Absence of

Negation Symbol

Row Input (or Output)System

Condition

Signal State (Truth-Value)

External Logic State

Internal Logic State

1alarmno alarm

true=1false=0

HL

10

2alarmno alarm

true=1false=0

LH

10

3alarmno alarm

true=1false=0

LH

01

4alarmno alarm

true=1false=0

HL

01

5alarmno alarm

false=0true=1

LH

01

6alarmno alarm

false=0true=1

HL

01

7alarmno alarm

false=0true=1

HL

10

8alarmno alarm

false=0true=1

LH

10

NOTES:1 The signal state being true corresponds to the external logic level being that level specied in the signal

name.2 The signal state being false corresponds to the logic level being the opposite of the level specied in the

signal name.



To reduce the amount of mental translation necessary in interpreting a logic diagram, usually the signal name isconstructed so that its level indication agrees with the polarity indication at the source of the signal.

Signal names on connections with mismatched polarity indications (see 7.6) should be consistent with the polarityindications on the portion of the connecting line where the signal name is shown.

8.2.3 Analog Signals

Analog signals have a continuous range of possible physical values. Names for analog signals should convey thevariable or function represented by the signal.

8.3 Names for Power and Other Constant-Level Connections

Constant-level connections, such as power supply connections, should be named according to the value of the physicalquantity they carry. This can be either a numerical value with a unit of measure or a commonly understoodabbreviation that implies a nominal numerical value and may also imply a tolerance to other additional properties. Forexample, a ground connection may be named 0.0 V or GND. A TTL supply voltage connection may be named +5.2 Vor VCC. All of the rules of 8.2 through 8.2.1.5 also apply to constant-level connections.

8.4 Locator Information

Locator information is information in addition to the connection names that aids in locating the connections, or otherinformation about the connections in the documentation or on the device itself. This may include documentation cross-references and physical-access information. Conventions used for locator information should be explained on thediagram or in supporting documentation.



8.4.1 Cross-Reference Information

Labels may include additional information that assists in locating other places on the diagram where a signal orconnection is represented, including sources, destinations, and drawing coordinates. They may also includeinformation used to identify a signal or connection in other documents, including computer-processed or computer-generated documents.

8.4.2 Physical Access Information

Labels and symbols may be associated with a signal or connection for the purpose of explaining how and where thesignal or connection may be accessed on the nished device (for example, test points).

8.5 Additional Properties and Characterization

Additional information that claries the operation, appearance, maintenance, or adjustment of a signal or constant-level connection may also be included (see also Section 9.).

9. Supplementary Information

9.1 Reference-Designation Accounting

If the class-code, sequential-numbering, reference designation system is used and items are eliminated as a result of arevision, remaining items need not be renumbered. For circuits showing many items, a table may be used to showwhich numbers are not used and the highest numerical reference designations, as shown in Fig 22. This table mayinclude any or all types of items and shall be located conveniently near notes or other tabular information.

Figure 22Typical Table Indicating Omitted and Highest Numerical Reference Designations

9.2 Diagram Notes

Notes may be used on diagrams to

1) Consolidate repetitious information2) Explain abbreviations3) Specify standards and conventions upon which the diagram is based4) Specify supporting documentation5) Otherwise augment the circuit diagram



These notes may be consolidated in one location or placed near their point of application.

9.2.1 General Notes

General notes usually apply to the entire drawing and are grouped together. They often include or may be preceded bythe words, UNLESS OTHERWISE SPECIFIED.

9.2.2 Local Notes

A local note is one that is placed near to and is clearly associated with a specic diagram detail.

9.2.3 Referenced (Indexed) Notes

Referenced notes are usually grouped together with the general notes. However, referenced notes apply to one or moreof the diagram details and are referred to by local notes that state, for example, SEE NOTE 15. Referenced notesshould be used if

1) The note invokes or references another document,2) The identical note applies at several locations on the diagram, or3) The note is lengthy and placing it at the point of application reduces clarity or tends to crowd other

information.

9.2.4 Examples

The following examples are typical of the kinds of information that should be considered when preparing NOTES.

a) FOR ASSEMBLY, SEE (drawing number).b) FOR WIRING INFORMATION, SEE (document number).c) FOR TEST SPECIFICATION, SEE (document number).d) UNLESS OTHERWISE SPECIFIED, RESISTANCE VALUES ARE IN OHMS (W), PLUS OR MINUS

(tolerance) %, (power rating) W.e) UNLESS OTHERWISE SPECIFIED, CAPACITANCE VALUES ARE IN MICROFARADS (mF), PLUS OR

MINUS (tolerance) %, (voltage rating) V.f) UNLESS OTHERWISE SPECIFIED, INDUCTORS ARE (value) MICRO-HENRIES (mH), PLUS OR

MINUS (tolerance) %.g) UNLESS OTHERWISE SPECIFIED, TRANSISTORS ARE (type disignation).h) UNLESS OTHERWISE SPECIFIED, DIODES ARE (type designation).i) TERMINAL NUMBERS ARE NOT NECESSARILY MARKED ON PARTS. SEE ASSEMBLY

DRAWING FOR TERMINAL LOCATIONS.j) ROTARY DEVICES ARE VIEWED FROM THE FRONT WITH KNOB IN EXTREME CCW POSITION.k) (State convention) DENOTES LOWERCASE LETTERS.l) PARTIAL REFERENCE DESIGNATIONS ARE SHOWN. FOR COMPLETE DESIGNATION, PREFIX

WITH (show all of the reference designations that apply to the subassemblies or assemblies within which theitem is located including the highest level required to designate the item uniquely).

m) NOMENCLATURE ENCLOSED IN A RECTANGLE IS A FRONT-PANEL MARKING.n) ALL WAVEFORMS ARE IDEALIZED.o) ABBREVIATIONS CONFORM TO (state document).p) (Insert TERMINALS or CONTACTS) SHOWN WITHOUT CONNECTION ARE SPARES.q) DNU INDICATES (insert TERMINALS or CONTACTS) TO WHICH CONNECTION SHALL NOT BE

MADE.r) (Starting reference designation) THROUGH (last reference designation in the series) ARE IDENTICAL

COMPONENTS CONNECTED IN PARALLEL.s) PREPARED IN ACCORDANCE WITH ANSl/IEEE Std 991-1985 .t) LOGIC SYMBOLS CONFORM TO ANSI/IEEE Std 91-1984 .



u) (Specify POSITIVE or NEGATIVE) LOGIC CONVENTIONS APPLY.v) DIRECT POLARITY INDICATION APPLIES.

9.3 Tabular Information

A logic diagram may be supplemented by other information such as:

1) Truth tables or function tables2) Tables containing information on components and packaged elements used to implement functions3) Tables providing information on signal source, destination, etc

9.4 Waveforms

9.4.1 Use

Waveforms shall be shown where required for testing, adjustment of the circuit, or clarication of the circuit function.Waveforms may be required to show the waveshape or the timing relation of the wavetrain.

Waveforms or their stylized representation should be oriented as they appear on an oscilloscope or other devicenormally used to view a waveform.

9.4.2 Stylized Waveforms

Unless otherwise required for the application, waveforms may be shown in a stylized manner; for example, anapproximation of the actual waveshape, with sharp corners and omitting signicant trailing edges or spikes (seeFig 23).

Narrow pulses may be represented by a single line if representation of the pulse duration is not essential.



Figure 23Stylized Waveforms

Waveforms may be shown adjacent to a line or, if not confusing, may use the signal line as the x-axis, as shown inFig 24.

Figure 24Typical Waveforms for Signal Lines

9.4.3 Simplified Waveform Notations

The time of occurrence of a pulse, or the beginning and ending times of a pulse train, or of a level may be indicated ina simplied manner as shown in Fig 25.



Figure 25Simplified Waveform Notations

9.5 Diagram Simplification and Abbreviation Techniques

Diagram simplication and abbreviation techniques may be used, for example, to reduce preparation effort, increaseamount of information shown per diagram sheet, or reduce clutter by eliminating repetitive details. In general, anyabbreviation method may be used that does not impair understanding of the diagram and that maintains the continuityof signals within the diagram. If simplication or abbreviation techniques are employed, they should be explained onthe diagram or in supporting documentation unless they are self-explanatory.

The following paragraphs provide typical examples of some simplication and abbreviation techniques.

9.5.1 Repeated Symbol Simplification

If a logic symbol for a specic device is shown two or more times on a diagram, the fully delineated symbol need beshown only once. The repeated appearances may be represented by a simplied symbol.



The simplied symbol shall be a rectangle and contain all relevant application and identication information. It shallalso include an appropriate reference to the fully delineated symbol. A rectangular box shall be added outside, at theupper-left corner of the fully delineated symbol, to contain a unique reference identication. The same referenceidentication shall be shown in a rectangular box located at the inside, at the upper-left corner of each correspondingsimplied symbol. If on a single sheet only one fully delineated symbol is used for a specic device, the device typeis sufcient reference for repeated appearances of that device on that sheet. If more than one sheet of a multisheetdiagram is involved, a sheet cross-reference to the fully delineated symbol shall be shown in the lower-left corner ofthe repeated pattern enclosure.

Individual inputs and outputs of the simplied symbols shall include appropriate references to the correspondinginputs and outputs on the fully delineated symbol. If there are no terminal identiers (for example, in a basic logicdiagram) or other corresponding internal labels, the arrangement of inputs and outputs in the simplied symbol mustbe the same as in the fully delineated symbol (the arrangement provides the cross reference). Otherwise, the individualinputs and outputs must have appropriate cross-references provided.

If there are identical terminal identiers on both symbols, the terminal identiers, not their arrangement, provide thecross-reference. However, it is recommended that the terminal arrangement still be the same. See Fig 26.



Figure 26Repeated Symbol Simplification

9.5.2 Repeated Circuit Patterns

If a portion of circuitry is used repeatedly in the same diagram, only one complete delineation is necessary. Alladditional applications may be shown in simplied form. Both theoriginal pattern and the repeated-patterns shall beenclosed in solid single-line boxes. The repeated-pattern enclosures shall be drawn only as large as required sincecircuit detail is omitted. If more than one sheet of a multisheet diagram is involved, a sheet cross-reference to the fullydelineated pattern shall be shown in the lower-left corner of the repeated-pattern enclosure. Connections to repeatedcircuit patterns shall be arranged in the same order and direction as shown on the fully delineated circuit pattern.Otherwise, the connections shall include appropriate references to the corresponding connections of the fullydelineated circuit pattern.

A unique identication shall be assigned to each different circuit pattern. The same circuit pattern identication shallbe assigned to all like patterns in a diagram. The identication shall be shown in a rectangle located at the upper-leftcorner of both the fully delineated and the repeated patterns.

Any differences within the repeated pattern from the original in de

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