annual report: 0087487 annual report for period:07… · annual report: 0087487 page 1 of 6 annual...

Annual Report: 0087487

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Annual Report for Period:07/2004 - 07/2005 Submitted on: 07/08/2005

Principal Investigator: Karri, Ramesh . Award ID: 0087487

Organization: Polytechnic Univ of NY

Title:Towards enabling a 2-3 orders of magnitude improvement in call handling capacities of switches

Project Participants

Senior Personnel

Name: Veeraraghavan, Malathi

Worked for more than 160 Hours: Yes

Contribution to Project: Malathi Veeraraghavan guided PhD students, MS and undergraduate students in various tasks. In addition to handling specific aspects of the project itself, Malathi came up with research ideas for extending/applying the results of the project, e.g., the VBLS work.

Name: Karri, Ramesh


Contribution to Project: Ramesh Karri provided expertise in our selection of hardware (FPGA) and related design choices. He guided the many students involved in this project on the hardware aspects of the work.

Name: Wu, Liji


Contribution to Project: Dr. Liji Wu designed the SONET switch board, which includes the FPGA implementing our signaling engine.

Name: Karri, Ramesh


Contribution to Project:

Name: Veeraraghavan, Malathi


Contribution to Project:

Post-doc

Graduate Student

Name: Wang, Haobo


Contribution to Project: Haobo Wang focussed on implementing the signaling protocol subset in a FPGA. He modeled it using VHDL and implemented it on an FGPA and tested it in a Wildforce prototype board. He was supported as an RA with stipend and tuition for the year.

Name: Tao, Zhifeng



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Contribution to Project: Zhifeng (Jeff) Tao compared several network processors to see if any of these were suitable for our protocol implementation. He was supported as an RA with stipend and tuition for the year.

Name: Li, Tao


Contribution to Project: Tao Li defined the subset of CR-LDP for hardware implementation. He also designed a set of tests to run on our hardware-accelerated signaling engine.

Name: Lee, Hojun


Contribution to Project: Hojun studied the VBLS algorithm. This is important to support file transfers on high-speed circuits, which we think is the primary application for hardware-signaling based switches.

Name: Ghee, Sevron


Contribution to Project: Sevron Ghee did the physical layout for the board using Allegro and other Cadence tools.

Name: Nethi, Murali


Contribution to Project: Murali is testing the VHDL models for the RSVP-TE signaling engine.

Undergraduate Student

Name: Qin, Yixing


Contribution to Project: Yixing Qin implemented the test software to generate RSVP-TE messages to test the hardware implementation.

Name: Glorioso, Russ


Contribution to Project: Russ developed testbenches to test the VHDL models.

Technician, Programmer

Other Participant

Research Experience for Undergraduates

Organizational Partners

Other Collaborators or Contacts


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University of Ottawa, Network Control and Computing Technologies laboratory, is interested in our hardware implementation of RSVP-TE.

Activities and Findings

Research and Education Activities: (See PDF version submitted by PI at the end of the report)

Findings: (See PDF version submitted by PI at the end of the report)

Training and Development:Students learned the use of many hardware design tools, Modelsim, Synplify, Xilinx ISE, Cadence's Concept HDL, Allegro, Spectra.

Outreach Activities:We presented a poster at Open Houses at the departmental and school level at University of Virginia. Students' parents and the local community are usually the predominant attendees of these Open Houses.

Journal Publications

M. Veeraraghavan, Xuan Zheng, Wu-chun Feng, Hojun Lee, Edwin Chong & Hua Li, "Scheduling and transport for file transfers on high-speed optical circuits", Journal of Grid Computing, p.1, vol. 00, (2004). Accepted

M. Veeraraghavan and X. Zheng, "A Reconfigurable Ethernet/SONET Circuit Based Metro Network Architecture", IEEE Journal on SelectedAreas in Communication (JSAC), p. , vol. , ( ). Accepted

H. Wang, M. Veeraraghavan, R. Karri, T. Li, "Design of a High-Performance RSVP-TE Signaling Hardware Accelerator", IEEE JSAC, p. ,vol. , ( ). Accepted

Malathi Veeraraghavan, Xuan Zheng, Zhanxiang Huang, "On the use of GMPLS networks to support Grid Computing", IEEE Communicationmagazine, p. , vol. , ( ). Submitted

Books or Other One-time Publications

H. Wang M. Veeraraghavan R. Karri, "A Dynamic Circuits Based Wide-Area SAN Solution", (2003). Workshop paper, PublishedCollection: Optical Networking Technologies for Global SAN Solutions Workshop (in association with Opticomm 2003)Bibliography: Oct. 13-17, 2003, Dallas, TX

M. Veeraraghavan, H. Lee, E. K. P. Chong and H. Li, "A varying-bandwidth list scheduling heuristic for file transfers,", (2004). Conferenceproceedings, PublishedCollection: Proc. of the IEEE Intl. Conference on Communications (ICC)Bibliography: June 20-24, 2004, Paris, France


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H. Wang, R. Karri, M. Veeraraghavan, T. Li, "Hardware-Accelerated Implementation of the RSVP-TE Signaling Protocol,", (2004).Conference Proceedings, PublishedCollection: Proc. of IEEE Intl. Conference on Communications (ICC)Bibliography: June 20-24, 2004, Paris, France

H. Lee, M. Veeraraghavan, H. Li and E. K. P. Chong,, "Lambda scheduling algorithm for file transfers on high-speed optical circuits,", (2004). Conference Proceedings, PublishedCollection: IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2004)Bibliography: April 19 - 22, 2004, Chicago, Illinois, USA

M. Veeraraghavan and H. Wang, "A Comparison of In-Band and Out-of-Band Transport Options for Signaling", (2004). ConferenceProceedings, PublishedCollection: IEEE Workshop On the Quest to Control Next-Generation Transport Networks: The Role of Generalized Multi-Protocol LabelSwitching (GMPLS), held in conjunction with IEEE Globecom 2004Bibliography: Nov. 29 - Dec. 3, Dallas, TX

H. Wang R. Karri M. Veeraraghavan, "A 6.4Gbps RSVP-TE Signaling Engine", (2004). Symp. proceedings, SubmittedCollection: IEEE HOT CHIPS, A Symposium on High Performance Chips.

Bibliography: August 22-24, 2004, Stanford

Web/Internet Site

URL(s):http://www.ece.virginia.edu/~mv/research/hwsig/index.htmDescription:

Other Specific Products

Product Type:

Software (or netware)

Product Description:It is the board schematic for a control card on a SONET switch with a hardware-accelerated GMPLS signaling engine implemented on an FPGA.

Sharing Information:This software allows others interested in experimenting with our control card design to download our solution and use it. We will provide the physical layout shortly allowing other research groups to download and send this layout to a board manufacturer. By purchasing the correct devices, one can build an experimental RSVP-TE control card with our design at a low cost.

Product Type:


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Software (or netware)

Product Description:VHDL models for an RSVP-TE subset implementation for a SONET switch. These models were created using the Cadence Concept HDL tool.

Sharing Information:We have posted a tar file consisting of these models on our project web site for others to download. Researchers at the University of Ottawa are interested.

Contributions

Contributions within Discipline: This year, we completed the VHDL models of RSVP-TE and the schematic of a board design for an RSVP-TE control card using off-the-shelf ASICs and our FPGA with the hardware-accelerated signaling engine. This is a design for a high-performance call processor.

Contributions to Other Disciplines: This year, we recognized the impact of our work on hardware signaling on Grid computing. The vision of Grid computing is to pull in computers from anywhere and run a parallel computation. Having the ability to establish high-speed rate-guaranteed connectivity (circuits) between these computers very quickly will allow for the use of such circuits for the transfers of even small amounts of data. This allows for high circuit utilization to be achieved while simultaneously offering rate-guaranteed service to the applications.

Contributions to Human Resource Development: This year, we had an undergraduate student, Russ Gloriso, do his senior thesis on this project. He wrote testbenches for the VHDL models of RSVP-TE. Two graduate students, Murali Nethi and Tao Li have been involved in completing the VHDL model testing and board layout. Haobo Wang completed his PhD on this project in Nov. 2004.

Contributions to Resources for Research and Education: Undergraduate students had an opportunity to learn and use VHDL modeling for communication protocols. A project was created in an undergraduate class on Computer Networks to implement the sliding window flow control using VHDL models.

Contributions Beyond Science and Engineering:

Special Requirements

Special reporting requirements: None

Change in Objectives or Scope: None

Unobligated funds: less than 20 percent of current funds


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Animal, Human Subjects, Biohazards: None

Categories for which nothing is reported: Organizational Partners

Contributions: To Any Beyond Science and Engineering

Year 4 Activities report for the NSF project 0087487: Sept. 2004 - August 2005

Title: Towards enabling a 2-3 orders of magnitude improvement in call han-dling capacities of switches

Please reiterate the goals and objectives of your efforts, and summarize the research and educa-

tion activities you have engaged in that aim to achieve these objectives. Include experiments you

have conducted, the simulations you have run, the collecting you have done, the observations you

have made, the materials you have developed, and major presentations you have made about your

efforts. In a later section you will list more formally any publications and other specific products

(database, collections, software, inventions, etc.) that have resulted.

The goal of this project is to demonstrate a signaling engine for switches in connection-ori-

ented networks with circuit or packet switches, that can have high call handling capacities and

low call setup delays. Our objectives are to achieve call setup delays in the order of microseconds,

and call handling capacities in the order of 100,000 to 1M calls/sec. Both these are two to three

orders of magnitude better than signaling engines in existing connection-oriented switches.

Research activities in year 4 included:

• testing of the VHDL models of RSVP-TE and the interface modules needed to com-

municate with the various devices on the control card

• schematic design of the control card for a SONET switch

• writing software to generate RSVP-TE test messages (for success and failure scenar-

ios)

• writing test benches for the VHDL models

• documenting the VHDL models (RSVP-TE and interface modules)

• documenting the control card design

• design document for the device initialization software

• analyzing and simulating applications that can benefit from hardware-accelerated sig-

naling

• completion of work on the design of a signaling network solution to reduce transmis-

sion delays of signaling messages necessary to complement the reduction in call pro-

cessing delays offered by the hardware-accelerated signaling engine

• study of the use of hardware-accelerated signaling engines in GMPLS networks to

support Grid Computing.

Education activities include the graduation of a Ph.D. student, Haobo Wang, fully supported

by this project, teaching of the use of VHDL models for communication protocols in a class on

Computer Networks, a senior thesis by an undergraduate student (Russ Glorioso), and research

work by two graduate students, Tao Li and Murali K. Nethi.

Our experiments included (1) using Modelsim to create the VHDL models, (ii) synthesizing

the prototype VHDL model of the RSVP-TE signaling hardware accelerator in conjunction with

models of the TCAM, SRAM, and FIFO using Synplify, (iii) using Xilinx ISE for place-and-route

within the FPGA, (iv) using Cadence’s Concept HDL tool to design the control card (schematic),

(v) Cadence’s Allegro tool for physical layout (place-and-route) of the devices of the card, and

(vi) Cadence’s Spectra for auto-route of connectivity between device pins on the board.

After extensive physical-layout design work, we decided to drop the Switch Fabric device

shown in Figure 1 below (from year 3 activities report) from the board design. The board already

needs fourteen layers for routing and the inclusion of the switch fabric device made the board too

complex. Also, in typical SONET switches, the fabric device is in its own board (card), distinct

from the data-plane interface cards and the control card. Finally, without the data-plane interfaces,

there was not much value in having the switch fabric device on board. Our original thinking was

that by including this switch fabric device, we could test the part of the RSVP-TE signaling

engine that issues the actual switch programming commands. Unfortunately, this functionality

cannot be tested given our decision to drop the switch fabric from the board design. Nevertheless

the RSVP-TE signaling engine will include the functionality to issue these commands, specifi-

cally for the Vitesse VSC9182 switch fabric device. Our current board design is thus a control

card that can be used in SONET switches.

For PCB manufacturing and component assembly, after considering quotes from about eight

companies, we selected ACI-Applicad Corporation, NJ. The board is currently under manufactur-

ing. We approved the final physical-layout conducted by the company after a few iterations.

The materials we have developed include VHDL models, board schematics, papers and pre-

sentations. We published a significant journal paper in IEEE JSAC on this work this year, and

have submitted a paper on the application of this technology for Grid Computing to IEEE Com-

munications Magazine. All of the published papers, VHDL models and control card schematic are

available through the project web site: http://www.ece.virginia.edu/~mv/research/hwsig/

index.htm. We presented the work in SuperComputing 2004, Pittsburgh, Nov. 2004, at which the

CHEETAH project, of which this hardware-signaling work is an important component, shared a

booth with the DRAGON project. We also presented this work in various NSF workshops on opti-

cal networking, bringing the attention of the community to the use of hardware-accelerated

RSVP-TE implementations. A list of our presentations is given below:

Title of Presentation Meeting Place Date

Match between Grid Computing and GMPLS networks

US/EU Workshop on Optical Networking

Brus-sels, Bel-gium

June 27-28, 2005

CHEETAH Joint Engineering Team Review of Optical Net-working Testbeds, NSF, Washington, DC

Wash-ington, DC

April 19, 2005

CHEETAH NSF Sponsored Plan-ning Workshop on “The Future of Optical Com-munications: Under-standing the Choices”

Santa Barbara

April 12 & 13, 2005

Enabling a connection-oriented internet

Georgia Tech Atlanta March 30, 2005

Enabling a connection-oriented internet

Duke University Durham, NC

Feb. 11, 2005

CHEETAH Exhibition SuperComputing 2005 Pitts-burgh

Nov. 6-12, 2004

FPGA(XC2V3000)

Switch Fabric(VSC9182)

SRAM1(IDT71V2556)

SRAM0(IDT71V2556)

TCAM(IDT75P52100)

FIFO(IDT72V36100)

GbE MAC(L8104)SerDes

(HDMP-1636)

Clock OSC(CO43S)

Duplex SCConnector

PCI Connector

OpticalTransceiver

(HFCT-53D5)

Fig. 1 Architecture of the prototype board

Immediate-request vs. scheduled calls, Short-duration vs. long-dura-tion calls

MCNC Workshop on GMPLS Control Plane

Pitts-burgh

November 12, 2004.

Served as panelist Optical Networks and Grid Computing Panel, Broadnets, 2004

San Jose Oct. 25-29, 2004

Title of Presentation Meeting Place Date

Year 4 (Sept. 2004 - July 2005) Findings report for the NSF project 0087487

Title: Towards enabling a 2-3 orders of magnitude improvement in call han-dling capacities of switches

Please summarize the conclusions that have emerged from your activities. Later screens will

invite you to identify publications and other concrete products (collections, databases, software,

inventions, and so on) and to explain the significance and implications of both findings and prod-

ucts for your field, for other fields, and even beyond science and engineering.

• If you have no findings to report, at least for now, please click the corresponding but-

ton. We anticipate that as the project progresses your emphasis in reporting will shift

from activities to findings and products, and ultimately to contributions.

Our key conclusions:

1. After completing the schematic of our prototype board, which includes multiple BGA

devices, we found physical layout difficult to achieve even with a 14-layer PCB. Hence we

decided to drop the switch fabric device and limit it to a control card. This is in keeping with

current switch architectures in which the control card is designed exclusively to handle con-

trol functions, such as signaling and routing, and the switch fabric is located in a separate fab-

ric board.

2. We found an interesting application for connection-oriented networks with hardware-acceler-

ated (fast) signaling, i.e., Grid computing. The vision of the Grid is to recruit general-purpose

computers located on a general-purpose network into a parallel computation. GMPLS control-

plane protocols, developed to create large-scale connection-oriented networks with dynamic

bandwidth sharing, seem to be well suited for Grid computing applications. The low call setup

delays possible with hardware-accelerated RSVP-TE signaling engines, makes it possible to

use rate-guaranteed connections even for small (100KB to a few MB) communication

exchanges between components of a parallel computation. We are currently obtaining com-

munication pattern data on Grid Computing applications and developing models to study the

use of GMPLS networks (with hardware-accelerated signaling) to support these applications.

3. We leveraged our work in another NSF-funded project to create the CHEETAH testbed, by

using a software implementation of RSVP-TE signaling protocol to generate messages with

which to test our hardware implementation. Our preliminary results look promising. The hard-

ware implementation successfully accepts those messages that conform to the subset defined

for hardware handling.

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