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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces

Lecture 23Case Studies

Disk Drive Read/Write ChannelsBorivoje NikolićApril 13, 2004.

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Announcements

Homework #3 (the last one!) posted, due in 10 daysFeedback on project, e-mailed to you today

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OutlineWrap up EthernetDisk-drive signal processing

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‘Marvel of Technology’

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Disk Drives1956 IBM engineers in San Jose introduced the first computer disk storage systemThe 305 RAMAC (Random Access Method of Accounting and Control) could store five million characters (five megabytes) of data on 50 disks, each 24 inches in diameter.

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Today’s DisksHitachi (IBM) Travelstar 70 Gb/in2

Experimental densities: 100+Gb/in2; every square inch of disk space could hold 12 GB -- nearly as much data as a three 5.25-inch diameter DVD-ROMs. (4.7 GB per surface) or 20 CD-ROMs (each 650 MB).

Desktop drives 300 GBNotebook drives 80 GBMicrodrive (1-inch) > 4 GB.

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Trends in Magnetic Disk Drives

Exponential growth in capacity is due to:reduction of head flying heightreduction of the gap size in the headreduction of the media thicknessadvanced signal processing methodsadvanced digitalintegrated circuits

Areal density of datain disk drives:

10

100

1000

10000

100000

1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005

Year

Are

al D

ensi

ty [M

b/in

2 ]

Super Paramagnetic Limit

30Gb/in2 Demo

3 Gb/in2 Demo

1 Gb/in2 Demo

60% CGR

30% CGR

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IBM’s Areal Densities

http://www.storage.ibm.com/technolo/grochows/grocho01.htm

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Areal Density Trends

0.01

0.1

1

10

100

1000

10000

100000

1960 1965 1970 1975 1980 1985 1990 1995 2000 2005

MR Head/ PRMLTechnologies

30% CGR

60% CGR

Are

al D

ensi

ty (M

bits

/sq.

in.)

TimeH.Thapar

GMR Head

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Datarate Trends in Disk Drives

Source: ISSCC + vendors’ web sites

10

100

1000

10000

1990 1992 1994 1996 1998 2000 2002Year

Dat

a R

ate

[Mb/

s]

Data rate increase throughtechnology scaling

Data rate trendsin read channels

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Flight Height

Rotation speeds: 4500 – 15000 rpm

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Price Trends

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Magnetic Recording Fundamentals

Magnetic Disk Track Recording

Magnetization Levels

Detected signal in the Head

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Magnetic Recording Fundamentals

ReducedAmplitude

PeakShift

IsolatedPulses

SuperposedPulses

Increased recording density results in:• reduced peak amplitude• peak shift

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Lorentzian Pulse

-2 -1.5 -1 -0.5 0 0.5 1 1.5 20

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Normalized Time t/PW50

Am

plitu

de o

f Ste

p R

espo

nse

PW502

50

21

1)(

+

=

PWt

ts

Lorentzian:

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Bandlimited Channels

Spectral control(ISI control)

SNR limitation

Towards Shannon

capacity

Equalization- Partial response

Channel coding- Trellis/Parity coding

Combined coding andEqualization- Iterative coding

Going to 1Tb/in2 density will lower the SNR by another 6dB

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Signal Equalization

Lorenzian Pulse

Equalization (1−D)(1+D)n

1.0

0.5

PW50

PR4 EPR4 E2PR4

(1-D)(1+D) (1-D)(1+D)2 (1-D)(1+D)3

1 1

2

13

( ) 2

50

21

1

+

=

PWt

tl

User density = PW50/T

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0 5 10 15 20 25 30 35 40 45 50

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time

Am

plitu

de

Recording Channel Input/Output PW50/T = 1.4

0 5 10 15 20 25 30 35 40 45 50

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time

Am

plitu

de

Recording Channel Input/Output PW50/T = 3.0

Signal Response

Simulated readback signal

User density = 1.4 User density = 3.0

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Amplitude Spectra

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

0.00

0.04

0.08 0.12

0.16

0.20

0.24

0.28

0.32

0.36

0.40

0.44

0.48

Normalized Frequency

Am

plitu

de

pw50/T=1.0pw50/T=1.4pw50/T=1.8pw50/T=2.2pw50/T=2.6pw50/T=3.0

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Equalization Targets

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.00

0.00 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 0.44 0.48

Frequency

Mag

nitu

de PR4(n=1)

E2PR4(n=3)

EPR4(n=2)

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Read Channel Building Blocks

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Eye Diagrams

PR4

EPR4

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Maximum Likelihood Detection

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The Viterbi Detector

Equalization Response Memory StatesPR4 1−D2 2 4 (2)EPR4 (1−D)(1+D)2 3 8E2PR4 (1−D)(1+D)3 4 16

Alternative is to use DFE;not used in practice because of error propagation

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Error DistancesChannel input error sequence:

)()(ˆ)( DxDxDex −=

Channel output error sequence:)()(ˆ)( DyDyDey −=

Squared Euclidean error distance:

( ) ( ) ( ) 222 )( DhDeDeEd xy ==

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Error Probability

Probability of misdetection of sequence Sk by Sk’ is a function of error distance, dKPerformance of the PRML system is determined by the minimum distance error events

σ

≈2min

mindQKP de

Q () - Error functionError event distancespectrum

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Signal Processing Trends

PEAK DETECTMFM

(2,7)

(1,7)

PRMLEPRML PARITY CODING

d=0 ord=1

Density

Time

ANALOG DIGITAL

E PRML, GEnPRMLn

TURBO CODING

d=0

H. Thapar

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Current Implementation Approaches

Function Approach System Architecture EPR, E2PR, or generalized E2PR with

16/17 or 8/9 codes

Equalization Digital FIR, analog FIR, orcontinuous-time filter

ADC Flash, typically 6 bits

Detection Full Viterbi detector or Viterbidetector with post-processor

Gain control First-order loop with digital or analogintegration

Timing Recovery Second-order PLL using synchronousor interpolated timing

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Parity-Coded Channel

…

P(D)

+

ViterbiDetector

DelayErrorCorrelate

CheckParity

Maximum

CorrectError

Detect Error

Determine Likely Error Location

Data

-rk nk

xk

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Architecture #1

READSIGNAL

VGAVITERBIDETECT

TIMINGCONTROL

GAINCONTROL

DETECTEDDATA

Low passfilter

FIREq.

Key Features: • All analog

SSI, ’90-’97

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Architecture #2

READSIGNAL

VGAVITERBIDETECT

TIMINGCONTROL

GAINCONTROL

ADC

DETECTEDDATA

Low passfilter

FIREq.

Key Features: • Analog FIR equalizer• 40-levels in ADC

Lucent

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Architecture #3

Key Features: • Digital FIR equalizer• Full 6-bit ADC

READSIGNAL

VGA VITERBIDETECT

TIMINGCONTROL

GAINCONTROL

ADCDETECTEDDATA

Low passfilter

FIREq.

Dominant:TI (SSI), Marvell, Datapath, IBM

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Architecture #4

Key Features: • Digital FIR equalizer• Interpolated timing recovery• Full 6-bit ADC with >(1/T) samples/sec.

READSIGNAL

VGAVITERBIDETECT

TIMINGCONTROL

GAINCONTROL

ADC

DETECTEDDATA

Low passfilter

FIREq.

Interpolationfilter

Cirrus Logic

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Design Examples

1st generation chip170 Mb/s, 1.3W, 5V, 27.5mm2, 0.56mmPublished in 1997 ISSCC Paper 19.7

2nd generation chip240 Mb/s, 1.4W, 5V, 18.5mm2, 0.54mmUnpublished

3rd generation chip400 Mb/s, 1.1W, 3.3V, 13.5mm2, 0.29mmPublished in 1999 ISSCC Paper 2.2

H. Thapar, et al, CICC’98

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Analog Front-EndPre-equalization in analog domain

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Design ChallengesOne of the first Systems-on-a-Chip (SoC)> 2Gb/s ratePower limited (<2W, preferably 1W), inexpensive (<$2.5)Single step vs. lookahead/parallelReduced SNR, complex detectionIntegration with controller gives opportunities for more powerful coding and processingIterative decoders (Turbo, LDPC)

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Architectural ChoicesEqualizer

6-10 taps, >1Gb/sChoices of interleaving, pipelining, recoding, carry-save“Infinite” speed at the expense of power

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Architectural ChoicesViterbi Decoder

16 – 32 state, trellis coded with prostprocessor, variable equalization targetsRadix-2 vs. Radix-4, ACS vs. CSABit-level pipelining

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Future Signal ProcessingSNRs will continue to decreaseIterative decoding – LDPC based

Can we control the byte error rate?Complexity?Timing recovery at low SNRs

Vertical recording is already backMulti-track recording?

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IBM’s Advanced Storage Roadmap

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Holographic Storage

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IBM’s MIllipede

http://domino.research.ibm.com/Comm/bios.nsf/pages/millipede.html