Anil Deshpande#102A,Jubilee Homes,11-11-117, Indira Nagar, Hyderabad-35

Email: anildesh@gmail.comMobile: +919985775911

Objective

5+ years of experience in VLSI chip design and verification and a passionate founder and CEO of an education startup, it is the diverse knowledge and increased perspective of a management background that is fascinating. A wider knowledge base will enable me to hold a top corporate position at an early age.

Experience

QualEdu Technologies, Hyderabad, India Jun 10 –till dateFounder and CEO - Part time EmploymentQualEdu Technologies is a budding startup working on a unique and novel idea to improve the existing education system, the company focuses on providing some core and key education assessment tools and quality audit tools. As a founder and CEO, my vision is to take this unique idea from concept to product phase. Currently responsible for setting the overall direction and product strategy. Leading the QualEdu’s development of core technology and infrastructure.

AMD Research and Development India Pvt. Ltd, Hyderabad, India Jun 09-Till date

Power Management Verification of a Quadcore x86 advanced multi-processor with integrated graphics core 28 nm technology node

Verification Engineer and Lead PresentPart of a four member global team, leading a team of two members locally and individually responsible for several power management modules for verification of the system on chip. Working on overall verification requirement, test plans, coverage plans . Porting tests and covering the holes on verification by writing new verification scenarios. Conversant with overall ACPI spec for power management for multi-processors.

Power Aware Verification of Dualcore Advanced Processing Unit (X86+GPU) System Level Design and Verification Engineer 6 monthsOwned to design and verify circuit contention, power up and power down sequencing of the chip at system level using UPF by making RTL power aware. Came up with a full-chip UPF to mimic the power-gated behavior of the chip, the chip had multiple voltage planes separated using several level shifter and isolation cells . To verify the whole behavior of the chip when it goes in power-gated states ACPI states for power saving modes.

NXP Semiconductors India Pvt. Ltd, Hyderabad, India Jan '07 – Jun '09(Conexant’s Broadband Media Processing Unit was acquired by NXP Semiconductors)System-level Verification Lead for Peripherals of set-top box 10 monthsLead a three-member team that was responsible for the system-level verification of all peripherals of NXP’s next set-top box. Was individually responsible for the peripherals such as USB, DDR controller, PMAN (memory access network) and guided the team for other peripherals. Responsibilities included drawing the strategy for the verification process because of the merger of IPs, tools and resources from both the companies; defining requirements from each of the IPs; creating and running tests.

1

Avantel Softech India Pvt. Ltd, Hyderabad, India Aug '05 – Jan '07 Design and Verification Engineer 16 monthsDesign and Verification for a high-end satellite data receiver for satellite communications as a key member of the IP Design Team involved in design of a Viterbi Decoder IP core, more specifically the Add Compare Select Unit and Branch Metric Unit subsystem, my key contributions were, developed Add Compare Select Unit and Branch Metric Unit subsystem in VHDL and did micro architecture for the subsystem, worked on functional verification of Decoder using VHDL language achieving targeted functional and code coverage goals .Worked at system level verification after completion of module-level verification.

Programme Air Defence ,PGAD,DRDO, Hyderabad, India Aug '04 – Mar '05Project Trainee 9 monthsIn this project an attempt is being made to design a generic Linear Feedback Shift register sequence Generator. The design has been written in VHDL and implemented on FPGA and has also been experimentally verified. Due to configurable nature of the designed hardware, it is found to be capable of generating the entire range of LFSR sequences including maximal length sequences, Gold sequences and Kasami sequences.

Education

B.Tech in Electronics and Communication Engineering, JNTU , Hyderabad, IndiaPercentage:70 Graduated: May 2005

Computer SkillsLanguages: e, Perl, Verilog-XL, System Verilog CAE Tools: Specman, Debussy, Ncsim, VCS

Publications:

a. Anil Deshpande “Verification of IP-Core Based SoC’s” ,IEEE/ISQED-2008 conference on Quality Electronic Design San-José, California, Mar17-19 2008. On page(s): 433-436.

b.Anil Deshpande “Verification of IP-Core Based SoC’s” http://www.design-reuse.com/articles/18032/verification-ip-core-soc.html

c. Anil Deshpande “Power Intent specification and verification of Multi-Rail Macros using LEDA/MVSIM” - SNUG India, SNUG Boston 2010

Honors: Awarded VP Spotlight Award for my contribution at AMD . Awarded Participation Certificate for “How India can unleash its

entrepreneurship Potential” essay from National Knowledge Commission ,India

Received best employee of the month award several times at AMD Hyderabad

Member of a Global Power Verification strategy group from AMD Hyderabad.

2

Received Spontaneous Recognition Award at Conexant, Hyderabad in recognition for the good work done.

Won a special prize at IEEEs (Institute for Electrical and Electronic Engineers) National students convention held at Srinidhi Institute of Science and Technology (Hyderabad) for a technical project on Remote Controlled Fan Regulator.

Won second prize at I.S.T.E National student’s convention held at (Hyderabad) for a technical paper presentation on Flat Lens Antennas and Imaging.

Reported a bug in MICROSOFT Windows Xp professional 2002 edition and received a letter of appreciation from the Microsoft development team.

Extra Curricular Activities:

Engage in social service works and teaching children unique ways of understanding and learning techniques.

Play Table Tennis and Cricket. Hobbies include reading books, Quizzing.

Personal Details:

Name: Anil Deshpande DoB: 19th April 1983

Sex: M Marital Status: Single

Passport Number: F40511811 Nationality: Indian

References:

Available on request.

The above stated information is correct as per my knowledge and I can be held responsible if any information provided by me is found incorrect.

Anil Deshpande

3