analysis and design of analog ic 2012 (1).pdf

2
1 M.E. DEGREE EXAMINATION, JUNE 2012. Second semester Applied Electronics AP 9221/248204/AP 921/10244 AE 201ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS (Common to M.E. VLSI Design) (Regulation 2009) Time: Three hours Maximum: 100 marks Answer ALL the Questions PART A(10 × 2 = 20 marks) 1. Compare long channel and short channel MOS transistors. 2. State the effect of substrate voltage on MOS device characteristics. 3. Define sensitivity factor S vdd vref 4. Draw the circuit schematic of a source follower with current mirror load. 5. Define slew rate and state its significance. 6. What are the various types of noises that affect the performance of operational amplifier? 7. Name the applications and the conditions for each application of Gilbert cell multiplier. 8. Give any two application of PLL. 9. What are the advantages of folded cascade configuration? 10. State the effect of channel length modulation on the current mirror ratio. PART B(5 × 16 = 80 marks) 11. (a) (i) Derive the small signal low frequency model for a MOS transistor operating in the ohmic region with Q point IDQ,VasQ, VDSQ and VBSQ. (10) (ii) What does this reduce to when VDSQ = OV? (6) Or www.vidyarthiplus.com www.vidyarthiplus.com

Upload: anjugadu

Post on 22-Dec-2015

9 views

Category:

Documents


3 download

DESCRIPTION

Analysis and design of analog IC 2012

TRANSCRIPT

Page 1: Analysis and design of analog IC 2012 (1).pdf

1

M.E. DEGREE EXAMINATION, JUNE 2012.

Second semester

Applied Electronics

AP 9221/248204/AP 921/10244 AE 201— ANALYSIS AND DESIGN OF ANALOG

INTEGRATED CIRCUITS

(Common to M.E. VLSI Design)

(Regulation 2009)

Time: Three hours Maximum: 100 marks

Answer ALL the Questions

PART A— (10 × 2 = 20 marks)

1. Compare long channel and short channel MOS transistors.

2. State the effect of substrate voltage on MOS device characteristics.

3. Define sensitivity factor Svddvref

4. Draw the circuit schematic of a source follower with current mirror load.

5. Define slew rate and state its significance.

6. What are the various types of noises that affect the performance of operational

amplifier?

7. Name the applications and the conditions for each application of Gilbert cell

multiplier.

8. Give any two application of PLL.

9. What are the advantages of folded cascade configuration?

10. State the effect of channel length modulation on the current mirror ratio.

PART B— (5 × 16 = 80 marks)

11. (a) (i) Derive the small signal low frequency model for a MOS transistor

operating in the ohmic region with Q point IDQ,VasQ, VDSQ and VBSQ. (10)

(ii) What does this reduce to when VDSQ = OV? (6)

Or

www.vidyarthiplus.com

www.vidyarthiplus.com

Page 2: Analysis and design of analog IC 2012 (1).pdf

2

(b) (i) Explain the various second order effects of MOS transistors. (8)

(ii) From basic principles obtain the Id – V ps relationship in MOS transistors.

(8)

12. (a) (i) Discuss the operation of Band gap voltage reference circuit. Show that it is

temperature insensitive voltage reference. (10)

(ii) Explain operational amplifier noise model. (6)

Or

(b) Draw the schematic of FET differential amplifier with active load and explain the

effect of mismatch of gm and Rd on the gain of differential amplifier.

13. (a) Analyse the operational amplifier circuit in terms of slew rate model and high

frequency response.

Or

(b) Explain the frequency response characteristics of any one multistage amplifier

with relevant expression.

14. (a) Discuss the noise models of the various integrated circuit components.

Or

(b) Draw a four Quadrant Multiplier circuit using Gilbert cell and discuss.

15. (a) (i) With schematic and expressions compare cascade, Wilson and widlar

current sources. (8)

(ii) Draw the circuit of MOS folded cascode operational amplifier and

explain. (8)

Or

(b) (i) Discuss the schematic and characteristics of telescopic operational

amplifier. (8)

(ii) Explain any one type of o/p stage of op amp. (8)

www.vidyarthiplus.com

www.vidyarthiplus.com