analysis and design of a high step-up current-fed...

964 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 2, FEBRUARY 2012

Analysis and Design of a High Step-up Current-FedMultiresonant DC–DC Converter With Low

Circulating Energy and Zero-CurrentSwitching for All Active SwitchesBo Yuan, Student Member, IEEE, Xu Yang, Member, IEEE, Xiangjun Zeng,

Jason Duan, Member, IEEE, Jerry Zhai, and Donghao Li

Abstract—A high-efficiency high step-up current-fed multireso-nant converter (CFMRC) is proposed for interfacing the sustain-able power sources, such as PV panels and fuel cells, which arecharacterized by low-voltage high-current output and have strictcurrent ripple requirement. The proposed converter has the fea-tures of low input current ripple, low circulating energy, achievingzero-current switching (ZCS) for all active switches, and commonground driving. In order to further improve the efficiency andthe power density of the CFMRC, coupled inductor and voltagedoubler are applied to the two input inductors and the outputrectifier, respectively. The operation principle of the CFMRC isintroduced. Its dc voltage gain and the ZCS conditions of boththe primary switches and the secondary rectifier are also derivedbased on the steady-state analysis. Finally, a design guideline isgiven. The theoretical analysis of the CFMRC was verified on a150-W prototype. An average efficiency of 95.9% was achievedover the entire maximum power point tracking range (23–38 V),with a 350-V output at full load.

Index Terms—Coupled inductor, current-fed multiresonantconverter (CFMRC), step-up converter, voltage doubler, zero-current switching (ZCS).

I. INTRODUCTION

FOSSIL fuel related environmental issues and the chal-lenges to sustainable industrialization stimulate the devel-

opment of distributed generation based on renewable energy[1]–[14]. Some of the renewable power sources, such as PVpanels and fuel cells, are characterized by low-voltage high-

Manuscript received August 6, 2010; revised December 31, 2010 andMarch 11, 2011; accepted April 26, 2011. Date of publication May 31, 2011;date of current version October 18, 2011.

B. Yuan was with the State Key Laboratory of Electrical Insulation andPower Equipment, Xi’an Jiaotong University, Xi’an, Shaanxi 710049, China.He is now with the Power Management Products Division, Analog Devices,Inc., Xi’an, Shaanxi 710075, China (e-mail: [email protected]).

X. Yang and D. Li are with the State Key Laboratory of Electrical Insulationand Power Equipment, Xi’an Jiaotong University, Xi’an, Shaanxi 710049,China (e-mail: [email protected]; [email protected]).

X. Zeng (corresponding author) is with the School of Electrical Engineering,Xi’an Jiaotong University, Xi’an, Shaanxi 710049, China (e-mail: [email protected]).

J. Duan and J. Zhai are with the Department of Power ManagementProducts, Analog Devices, Inc., Shanghai 200021, China (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2158036

current output and have strict current ripple requirement[1]–[16]. Consequently, a dc–dc converter with high step-upcapability, galvanic isolation, low input current ripple, and highefficiency is required.

Current-fed converters attract more and more interests insuch kind of applications, with their inherent properties ofhigh boost capability and small input current ripple. Thus, thetransformer’s turns ratio can be reduced, and the bulk inputfilters can be shrunk as compared with the conventional voltage-fed converters. However, the current-fed pulse width modulatedconverters [17]–[23] still have the problems of high voltage andcurrent spikes resulting from the leakage inductance and wind-ing capacitance of the transformer, and high voltage stress onthe rectifying diodes due to their reverse recovery. Hence, theiroperating frequency should be low, and the power conversionefficiency is also limited. Kinds of active clamping techniques[15], [24]–[27] have been proposed to recycle the energy storedin the leakage inductance and to alleviate the surge voltageon the switches. Nevertheless, the additional clamping circuitscomplicate the application, lower the reliability, increase thecost, and always result in triangular switch currents whichincrease the current rms values.

Resonant techniques promise high-efficiency power conver-sion while operating at high switching frequency with theirinstinctive capability of well utilizing the circuit parasiticsand achieving zero-voltage switching (ZVS) or zero-currentswitching (ZCS) for the active switches [28]–[32]. Moreover,the current-fed parallel resonant converters (CFPRCs) [33] alsohave high step-up feature, with the introduced LC parallelresonating driven by a square wave current source. With suchtechniques, not only the parasitics of the transformer can beutilized, but also the turns ratio can be further reduced. Mostof the efforts for the CFPRCs were focused on achieving ZVSof the primary switches no matter if the active switches werecontrolled with dead time [34]–[36] or overlapping [37]–[39].However, in low-voltage high-current input applications, ZVSis not that much important, while ZCS is the key for switch-ing loss elimination [40]–[42], whereas the existing leakageinductance of the transformer still causes high voltage spikeson the switches. References [41] and [42] proposed a resonancebetween the leakage inductance and the parallel resonant ca-pacitor to achieve ZCS turn-off and to reduce the voltage stress

0278-0046/$26.00 © 2011 IEEE

YUAN et al.: ANALYSIS AND DESIGN OF A HIGH STEP-UP CURRENT-FED MULTIRESONANT DC–DC CONVERTER 965

Fig. 1. Schematics of the proposed converter. (a) Without coupled inductorand with full-bridge rectifier. (b) With coupled inductor and with voltagedoubler.

for all primary switches. Nevertheless, in order to achieve fullload range ZCS of the primary switches, the leakage inductancewas manipulated according to the heavy load condition, whichwould result in a large redundant circulating current flowingthrough the antiparallel diodes of the switches and, hence, thegreatly reduced efficiency at light load. Large circulating energywithin the resonant tank also produces high conduction lossesand limits the efficiency improvement of the CFPRCs. Energyfeedback was proposed to reduce the circulating energy [43].However, the necessary extra transformer and its impact on thequality factor make this concept inapposite for a design withhigh density and voltage regulation requirements. Moreover,the reverse recovery issue of the rectifying diodes still existsand results in high voltage spikes on the rectifying diodes. Thislimits the application of ultrafast recovery diodes with lowervoltage rating and lower forward voltage drop.

In this paper, a high-efficiency high step-up current-fedmultiresonant dc–dc converter with low input current ripple isproposed, as shown in Fig. 1. The proposed converter consistsof a square wave current source generator, a multiresonanttank, and an output voltage doubler [15], [26]. The current-fed half-bridge structure is adopted as the square wave currentsource generator, with its inherent merits of low input currentripple, low primary current of the transformer, high step-upcapability, and common ground gate driving. With the expec-tation of further improving the efficiency and reducing the sizeof the converter, coupled inductor techniques [19], [44] werefinally applied to the two input inductors. The multiresonanttank offers high voltage gain to reduce the turns ratio ofthe transformer. Meanwhile, it absorbs both the self-windingcapacitances of the transformer and the junction capacitancesof the rectifying diodes into its resonant capacitor; thus, thecurrent spikes within the circuit are well suppressed. By op-erating the two primary switches with overlapped conduction

time, a resonance between the leakage inductance and theresonant capacitor is introduced during the overlapping intervalto achieve soft commutation of the primary current whichfinally flows through the antiparallel diode before the switchturning off. Thereby, the primary switches are turned off withZCS, and the voltage spikes across the switches are reduced.The adopted single-capacitor output filter clamps the peakvoltage of the resonant capacitor to the output voltage duringthe conduction period of the rectifying diodes, whereas duringthe nonconduction period, the voltage of the resonant capacitorcould resonate down. In this way, the circulating energy withinthe resonant tank and the related conduction losses are reduced,the overshooting of the primary current is limited, and ZCSis achieved for the rectifying diodes without any additionalefforts in full load range. For efficiency improvement, a voltagedoubler was finally selected instead of the full-bridge rectifier.

The detailed operation principle of the proposed converter isintroduced in Section II. Section III carries out a comprehensivesteady-state analysis. The dc voltage gain and the ZCS condi-tions for all active switches are derived. Section IV develops adesign guideline for the proposed converter. Section V demon-strates the theoretical analysis of the proposed converter on a150-W prototype. Finally, Section VI concludes this paper.

II. OPERATION PRINCIPLE DESCRIPTION

As shown in Fig. 1(b), the current-fed half-bridge structureincludes two input inductors Lin1 and Lin2 and two activeswitches Q1 and Q2. DQ1 and DQ2 are the antiparallel diodesof Q1 and Q2, respectively. The multiresonant tank consistsof a resonant capacitor Cp, a first resonant inductor Lp, and asecond resonant inductorLr which participates in the resonancetogether with Lp andCp only during the commutation period ofthe primary current ipri. Lp is performed by the transformer’smagnetizing inductance which is much larger than Lr. Thetransformer’s leakage inductance and self-winding capacitanceare incorporated into Lr and Cp, respectively. The junctioncapacitances of the secondary rectifying diodes D1 and D2

are also absorbed into Cp. The output capacitors C1 and C2

are much larger than Cp and can smooth the rectified resonantcapacitor voltage vCp.

In order to clarify the illustration and analysis of the proposedconverter, several assumptions are first made. Lin1, Lin2, C1,and C2 are sufficiently large so that the input current Iin andthe output voltage Vo are constant during one switching cycle.The active switches Q1 and Q2 and the diodes, including DQ1

and DQ2, are ideal. The parasitics of all passive components arenot considered here.

Fig. 2(a)–(f) shows the first six operation modes of theproposed converter during half switching cycle, and the othersix operation modes for the remaining half switching cycle aresymmetrical to the first six operation modes. Fig. 2(g) showsthe corresponding theoretical waveforms.

Before t0, Q1 is on, Q2 is off, Lin1 is charged by the inputvoltage Vin, and Lin2 transfers its stored energy to the loadthrough D2. vCp is clamped to −Vo/2, and Lp is linearlydischarged. The current flowing through D2 (iD2) is equalto the transformer’s secondary current isec minus the currentflowing through Lp (iLp).


Fig. 2. Operating modes and waveforms of the proposed converter. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Theoreticalwaveforms.

Mode 1 [t0−t1; Fig. 2(a)]: At t0, iLp is equal to isec, and iD2

drops to zero. From t0 on, Q1 keeps on, Q2 keeps off,all rectifying diodes are off, the current flowing throughLin2 (iLin2) feeds the resonant tank formed by Lp and Cp,and Lr is absorbed into Lin2. Mode 1 ends at t1 when Q2

is switched on. In mode 1, Lin1 is charged by Vin, and vCp

resonates up.

Mode 2 [t1−t2; Fig. 2(b)]: From t1 on, both Q1 and Q2 conductthe current, terminals A and B are shorted, and all of therectifying diodes keep on blocking. Lr participates theresonance ofLp andCp for the commutation of ipri. As ipri

oscillating from negative to positive is driven by the initialnegative vCp at t1, current flowing through Q2 (iQ2) in-creases, while current flowing through Q1 (iQ1) decreases.


When iQ1 reaches zero at t2, mode 2 ends. It is criticalto select a proper Lr based on the overlap time to ensurethat iQ1 would drop to zero but with little overshooting,and then, Q1 could be turned off in the ZCS conditionwith minimized circulating energy. During this period,Lin1 and Lin2 are both charged by Vin, and vCp keeps onresonating up.

Mode 3 [t2−t3; Fig. 2(c)]: This mode is similar to mode 2,while iQ1 goes negative. Mode 3 ends at t3 when Q1

gets off. In this interval, ipri and iLp come to their peaks,respectively, and vCp rises across zero but is lower thanVo/2.

Mode 4 [t3−t4; Fig. 2(d)]: This mode is similar to mode 3except that the negative iQ1 flows through DQ1 after Q1 isoff. When iQ1 reaches zero again at t4, mode 4 ends. Thisperiod is expected to be minimized by properly controllingthe turn-off point of Q1 to eliminate the conduction loss onDQ1.

Mode 5 [t4−t5; Fig. 2(e)]: From t4 on, DQ1 blocks off,while Q2 keeps on. Lr is absorbed into Lin1, and thecurrent flowing through Lin1 (iLin1) feeds the resonanttank formed by Lp and Cp, while Lin2 is still charged byVin. Mode 5 ends at t5 when vCp touches Vo/2.

Mode 6 [t5−t6; Fig. 2(f)]: From t5 on, Q1 is off, Q2 is on, D1

is forced on, and vCp is clamped to Vo/2. Lin1 transfersits stored energy to the load, while Lin2 is charged byVin. Lp is charged by Vo/2. The current flowing throughD1 (iD1) is equal to isec minus iLp. Mode 6 ends at t6 wheniLp is equal to isec and iD1 drops to zero. Because vCp

is clamped to Vo/2 during this energy transferring periodwhich takes up most part of the half switching cycle, thecirculating energy within Lp and Cp is minimized, and therelated conduction losses are accordingly reduced. As isecis almost constant during this period, the decreasing slewrate of iD1 is dominated by the well-controlled iLp; hence,ZCS can be ideally achieved for D1, and the reverse recov-ery issue is well eliminated without any additional efforts.The same situation is also applied to D2. Subsequently,the general ultrafast silicon diodes with low forward volt-age drop could be adopted by the rectifying diodes forbetter conduction performance, lower cost, and higherreliability.

III. STEADY-STATE ANALYSIS

As illustrated in Section II, there are two kinds of resonancesin the proposed current-fed multiresonant converter (CFMRC).Lr and Cp dominate the first kind of resonance during the com-mutation of ipri from t1 to t4 (modes 2–4). During this period,Lp is parallel with Lr and participates the resonance with Cp.However, Lp is performed by the transformer’s magnetizinginductance, while Lr would just be the leakage inductance. Lp

is much (more than 40 times in the experiment in Section V)larger than Lr; thereby, Lp has little affection and can beignored in this first kind of resonance. For the second kindof resonances during t0−t1 (modes 1) and t4−t5 (modes 5),Lr is absorbed into Lin1, or Lin2 and has no effect, while Lp

resonates with Cp to offer a high impedance to the currentsource to generate the required high voltage.

Fig. 3. Simplified circuit model of the proposed converter.

Obviously, Lr only affects the commutation of ipri. Fast andsoft commutation of ipri is ensured by the proper design of Lr.In this condition, the input voltage source and the current-fedhalf-bridge together with Lr can be modeled as a symmetricalsquare wave current source (Fig. 3) to simplify the steady-stateanalysis. In Fig. 3, the square wave current source is transferredto the secondary side of the transformer and has a magnitude ofIin/2N , where N represents the turns ratio of the transformer.Such simplification would be accurate enough especially for thederivation of the dc voltage gain characteristics of the proposedconverter as no power is transferred to the load during the com-mutation period of ipri. However, Lr and the commutation ofipri are critical in achieving ZCS for the two primary switches,which will be deeply investigated later.

A. Analytical Solution of the Simplified Circuit Model

For the simplified circuit model shown in Fig. 3, four opera-tion states are identified, and the key waveforms are shown inFig. 4.

In the first state, both of the rectifying diodes block theload current, and the square wave current source iCS feedsthe resonant tank formed by Cp and Lp. The waveform of iLp

presents part of sinusoidal, and it could be expressed as

iLp(t) = ILp_pk sin (ωpt− ϕ) ,π

2< ϕ < π (1)

where ILp_pk is the peak value of iLp, ϕ represent its phaseangle, and

ωp =1√LpCp

. (2)

In the second state, D1 conducts the load current, iCS feedsthe load, the resonant tank voltage vrec is clamped to Vo/2, andLp is linearly charged by Vo/2. For the purpose of making thefollowing analysis brief and clear, a conducting angle θ is de-fined to represent this conducting interval, and then, the afore-mentioned resonant interval could be represented by π − θ.The remaining two states are symmetrical to the previous twostates. In order to simplify the derivation of the analyticalsolution for the simplified circuit model shown in Fig. 3,the following formula deduction begins from the conductinginterval.


Fig. 4. Key waveforms of the simplified circuit model.

During the conducting interval [π − θ to π]

irec(t) = iCS(t) − iLp(t) (3)

iCS(t) =Iin2N

(4)

iLp(t) = ILp_bot +vrec(t)Lp

(t− π − θ

ω

)(5)

vrec(t) =Vo/2 (6)

where irec is the output current of the resonant tank, ILp_bot isthe bottom value of iLp during the conducting interval, and ωrepresents the angular switching frequency.

This conducting interval ends at the time of π/ω when iLp isequal to iCS and irec drops to zero

irec

(πω

)= 0. (7)

From (3)–(7), ILp_bot and irec are obtained as

ILp_bot =Iin2N

− θVo

2ωLp(8)

irec(t) = − Vo

2Lp

(t− π

ω

). (9)

The load current Io is equal to the average current flowingthrough the rectifier (Irec_av)

Io = Irec_av =1πω

πω∫

π−θω

irec(t) dt. (10)

Fig. 5. Conducting angle θ as a function of F and QL.

By substituting (9) into (10)

Io = Irec_av =Voθ

2

4πωLp. (11)

On the other hand

Io =Vo

RL(12)

where RL represents the load resistance.From (11) and (12), θ is obtained as

θ = 2

√πF

QL(13)

where

F =ω

ωp(14)

QL =RL

Zp(15)

Zp =

√Lp

Cp. (16)

Formula (13) could be further shown by Fig. 5. It is clear thatθ increases with the increasing of the load, and it can be wellcontrolled by modulating the switching frequency.

During the resonant interval [0 to π − θ]

irec(t) = 0. (17)

iLp is expressed as equation (1), and the current flowingthrough Cp is

iCp(t) = iCS(t) − iLp(t). (18)

The resonant tank voltage vrec is

vrec(t) = vCp(t) =1Cp

∫iCp(t) dt. (19)


The boundary conditions of the resonant interval are

iLp(0) = − Iin2N

(20)

vrec(0) = vCp(0) = −Vo/2 (21)

iLp

(π − θ

ω

)= ILp_bot (22)

vrec

(π − θ

ω

)= vCp

(π − θ

ω

)= Vo/2. (23)

From (1), (8), (20), and (22), ϕ and ILp_pk are obtained as

ϕ =π + tan−1

(sin(

π−θF

)1 − NVoθ

ZpIinF + cos(

π−θF

))

(24)

ILp_pk =Iin2N

√√√√√1 +

[1 − NVoθ

ZpIinF + cos(

π−θF

)]2sin2

(π−θF

) . (25)

Because iCS changes its polarity during the resonant interval,it is necessary to deduce vrec by dividing a whole resonantinterval into two periods for more detailed investigation. Thefirst period is defined from the beginning of the resonantinterval to the point when iCS changes its polarity, and α isused to represent this period with an angular unit of measure.

In this first resonant period [0 to α]

iCS(t) = − Iin2N

. (26)

From (1), (18), (19), (21), and (26), vrec is obtained as

vrec(t)=−ZpIin2N

ωpt+ZpILp_pk[cos(ωpt−ϕ)−cos(ϕ)]−Vo/2.(27)

Accordingly, the remaining resonant interval is defined as thesecond resonant period [α to π − θ]

iCS(t) =Iin2N

. (28)

The initial condition of this period could be obtained fromthe final condition of the first resonant period

vrec

(αω

)=−ZpIinα

2NF+ZpILp_pk

[cos(αF−ϕ)−cos(ϕ)

]−Vo/2.

(29)

From (1), (18), (19), (28), and (29), vrec is obtained as

vrec(t) =ZpIin2N

(ωpt− 2α

F

)

+ ZpILp_pk [cos (ωpt− ϕ) − cos(ϕ)] − Vo/2. (30)

From (23)–(25) and (30), α is obtained as

α =π − θ

2− NVoF

ZpIin

[1 − θ

2Ftan

(π − θ

2F

)]. (31)

B. DC Voltage Gain of the Proposed Converter

It is especially important to reveal the gain characteristics of aresonant converter for an adaptive control. The basis in derivingthe gain characteristics is the power balance concept and theacknowledgement that the first harmonics of the voltage andcurrent of the resonant tank are the main contributions to powertransferring [45]–[48].

The first harmonics of iCS (iCS1, shown as the dashed linein Fig. 4) is

iCS1 = ICS1_pk sin(ωt− α) (32)

where

ICS1_pk =2IinπN

. (33)

In order to find out the first harmonics of vrec and irec (vrec1and irec1, shown as the dashed lines in Fig. 4), vrec and irec arerewritten as (34), shown at the bottom of this page, and

irec(t) =

{0, 0 ≤ t < π−θ

ω

−ωpVo

2Zp

(t− π

ω

), π−θ

ω ≤ t ≤ πω .

(35)

Then, vrec1 and irec1 are obtained as

vrec1(t) =Vrec1_pk sin (ωt+ φ) (36)

irec1(t) = Irec1_pk sin (ωt+ ψ) (37)

where Vrec1_pk, φ, Irec1_pk, and Ψ can be easily derived by theFourier series expansion.

Then, the phase shift between vrec1 and irec1 can beobtained as

δ = φ− ψ. (38)

The relationship between δ and F in different load conditionsis shown in Fig. 6.

As δ is negative in the possible operation region, i.e., irec1leads vrec1, the resonant tank’s equivalent load impedance couldbe modeled as an equivalent capacitor Ce together with aparalleled equivalent resistor Re [45], [46]. Accordingly, anequivalent ac circuit of the simplified circuit model is obtained,as shown in Fig. 7.

vrec(t) =

−ZpIin

2N ωpt+ ZpILp_pk [cos (ωpt− ϕ) − cos (ϕ)] − Vo/2, 0 ≤ t < αω

ZpIin

2N

(ωpt− 2α

F

)+ ZpILp_pk [cos (ωpt− ϕ) − cos (ϕ)] − Vo/2, α

ω ≤ t < π−θω

Vo/2, π−θω ≤ t ≤ π

ω

(34)


Fig. 6. Phase angle δ of the equivalent load impedance.

Fig. 7. Equivalent ac circuit of the simplified circuit model.

The power dissipation on Re must be equal to the outputpower of the converter

V 2o

RL=V 2

rec1_pk

2Re(39)

where vrec1_pk is the peak value of vrec1.Re is then obtained as

Re =V 2

rec1_pk

2V 2o

RL. (40)

Moreover, with the relationship

tan (|δ|) = ωCeRe. (41)

Ce is obtained as

Ce =2V 2

o tan (|δ|)ωRLV 2

rec1_pk

. (42)

In Fig. 7, Zin represents the input impedance of the equiva-lent ac circuit. Its amplitude is

|Zin| =Vrec1_pk

ICS1_pk=

QeZp√1 +

[Qe

(1F − F

)− tan (|δ|)]2 (43)

where

Qe =Re

Zp. (44)

Supposing the efficiency of the proposed converter is η, then

Po =V 2

o

RL= ηPin = ηVinIin. (45)

Fig. 8. DC voltage gain characteristics.

Fig. 9. Input phase angle λ.

From (33), (39), and (43)–(45), the dc voltage gain G =Vo/Vin of the proposed converter is obtained as

G = πηN

√2QL

Qe

√1 +

[Qe

(1F

− F

)− tan (|δ|)

]2. (46)

Suppose η = 1 and N = 1, the dc voltage gain character-istics of the proposed converter are then revealed in Fig. 8.The calculated results based on (46) and the cycle-by-cyclesimulated results are marked with lines and points, respectively.For each QL, the dc voltage gain curve stops at the bottomlimitation of the operating frequency determined by the ZCScondition of the primary switches, as will be illustrated in thefollowing part.

C. Input Phase Angle of the Equivalent AC Circuit

Another important property of a resonant converter is theinput phase angle λ, i.e., the phase shift between the firstharmonics of the tank voltage vAB and the primary current ipri.In the equivalent ac circuit of the simplified circuit model, thefirst harmonics of vAB (vAB1) is in phase with vrec1, and thefirst harmonics of ipri (ipri1) is in phase with ics1. Hence, fromFig. 7

λ = tan−1

(Qe

(1F

− F

)− tan (|δ|)

). (47)

Formula (47) is also shown in Fig. 9.


D. ZCS Condition of Two Primary Switches

Achieving soft commutation of ipri is essential for the ZCSoperation of Q1 and Q2. The condition for the soft commutationof ipri is that ipri leads vAB , i.e., λ should be negative, and thatthere is enough energy stored in Cp to help the commutationof ipri. During the commutation period of ipri, Lr resonateswith Cp (here, Lp is neglected as it is always much larger thanLr). Thereby, the condition for the soft commutation of ipri isobtained as

λ < 0 (48)12Cpv

2Cp

(αω

)≥Lr

(Iin2

)2

. (49)

Criterion (48), together with Fig. 9, indicates the bottomlimitation of the operating frequency. It is preferable to alwaysrun the switching frequency above the resonant frequency toensure the soft commutation of ipri in full load range, althougha larger operating frequency range would be available withprecise control.

Criterion (49) indicates the design criterion for Lr as

Lr ≤ 2Cpv2Cp

(αω

)I2in

. (50)

A maximum value of Lr (Lr_max) is then set by (50). If Lr

is designed to be larger than Lr_max, the soft commutation ofipri would be failed. On the other hand, if Lr is designed tobe much smaller than Lr_max, the energy stored in Cp wouldcause too much overshooting of ipri, and the related circulatingenergy would induce extra conduction losses which reduce thepower conversion efficiency.

With the soft commutation of ipri, the ZCS operation ofQ1 and Q2 can be achieved by properly controlling theiroverlapped conduction time ∆Tov as

∆T1,2 ≤ ∆Tov ≤ ∆T1,4 (51)

where

∆T1,2 = t2 − t1 (52)∆T1,4 = t4 − t1 (53)∆Tov = (D − 0.5)T (54)

and T represents the switching period. Subsequently, the limi-tation for the duty cycle D is obtained as

Dmin =∆T1,2

T+ 0.5 (55)

Dmax =∆T1,4

T+ 0.5. (56)

For the purpose of correctly controlling ∆Tov , two crite-ria time periods ∆T1,2 and ∆T1,4 should be calculated. Asimplified circuit model for the analysis of ipri during thecommutation period can be derived, as shown in Fig. 10.

Here,C ′p is the equivalent value ofCp referred to the primary

side of the transformer

C ′p = N2Cp. (57)

Fig. 10. Simplified circuit model for the analysis of ipri during the commuta-tion period.

At t1, the initial conditions of this resonant circuit are

ipri(t1) = − Iin2

(58)

vC′p(t1) =1NvCp

(αω

). (59)

From t1 to t4, Lr resonates with C ′p, and the related differen-

tial equations are

−vC′p(t) =Lrdipri(t)dt

(60)

ipri(t) =C ′p

dvC′p(t)dt

. (61)

Then, ipri could be solved as

ipri(t)=−Iin2

cos (ωr(t−t1))− 1NZr

vCp

(αω

)sin (ωr(t−t1))

(62)where

ωr =1√LrC ′

p

(63)

Zr =

√Lr

C ′p

. (64)

At t1 and t4, here comes the following equation:

ipri(t) =Iin2. (65)

Finally, ∆T1,2 and ∆T1,4 could be calculated as

∆T1,2 =1ωr

sin−1

(−4NZrIinvCp

(αω

)N2Z2

r I2in + 4v2

Cp

(αω

))

(66)

∆T1,4 =π

ωr. (67)

It is clear that the commutation period of ipri (∆T1,4) onlydepends on ωr, and it has no relationship with the operatingfrequency and the load condition. In order to shorten ∆T1,4,proper resonant parameters, shown in Fig. 10, should be se-lected. The relationship between ∆T1,2 and F with differentQL’s is clearly shown in Fig. 11 for practical design. Accord-ingly, the control criterion for D is also shown in Fig. 12. Here,the condition (∆T1,2 < ∆T1,4 in Fig. 11 or Dmin < Dmax inFig. 12) for ZCS operation of the two primary switches has agood accordance with the condition (λ < 0 in Fig. 9) for the softcommutation of ipri on the bottom limitation of the operatingfrequency.


Fig. 11. Commutation times ∆T1,2 and ∆T1,4.

Fig. 12. Control criteria for duty cycle D.

E. ZCS Condition of Rectifying Diodes

As shown in Figs. 3 and 4, the essential for ZCS operationof the rectifying diodes is that iLp has to be charged up toiCS before its commutation point, and α indicates this timemargin. However, with the increase of the operating frequency,as shown in Fig. 9, iCS would lead vrec more and more, andhence, the margin α would decrease continuously until zero.If the operating frequency continually increases, the advancedcommutation point of iCS will finally cut down the conductinginterval of the rectifying diodes; hence, there will not be enoughtime for iLp to be charged up to iCS before its commutationpoint, and ZCS turn-off cannot be achieved for the rectifyingdiodes. Fig. 13 shows the simulation results that the rectify-ing diodes lose ZCS turn-off when the operating frequency(350 kHz) is much higher than the resonant frequency(250 kHz). The simulation circuit is based on the simplifiedcircuit model shown in Fig. 3. Although the proposed converteralso works without achieving ZCS for the rectifying diodesand the extended operating frequency is helpful to broaden theapplication of the proposed converter, the related discussion isbeyond the scope of this paper.

The ZCS condition of the rectifying diodes is obtained as

α ≥ 0. (68)

Fig. 14 describes the criterion (68) and indicates the top lim-itation of the operating frequency for achieving ZCS operationof the rectifying diodes.

Fig. 13. Simulation results while the rectifying diodes are under hardswitching.

Fig. 14. ZCS margin α as a function of F and QL.

IV. DESIGN GUIDELINE

A. Resonant Tank Design

1) Set the resonant frequency ωp.2) From (46)–(48), set the operating frequency range and

QL to fulfill the voltage regulation requirement, whilemaintain the ZCS condition for the primary switches.

3) Calculate the minimum voltage gain Gmin, and select theturns ratio of the transformer (N).

4) Calculate Lp and Cp from (2), (15), and (16) with theselected ωp, RL, and QL.

5) Calculate Lr from (50).6) Manipulate all of these resonant components together

with the circuit parasitics.

B. Duty Cycle Calculation

With the derived Lr,Cp, andN , the duty cycle limitation canbe calculated from (55)–(57), (63), (64), (66), and (67). Practi-cally, the duty cycle should be selected as close as possible toDmax to minimize the conduction of the antiparallel diode of


the MOSFET. This would be helpful not only in reducing theconduction loss but also in minimizing the reverse recovery ofthe antiparallel diode of the MOSFET.

C. Input Inductor Design

As shown in Fig. 2, the input current iin rises up during theoverlap time and declines during the off-time of any primaryswitches. Hence, iin has the input ripple current of two timesthe switching frequency and the peak-to-peak amplitude of

∆iin = 2Vin

L∆Tov (69)

where Lin1 and Lin2 are assumed to have the same value as L.With the symmetrical operation of the current-fed half-bridge

structure, the average current flowing through each input induc-tor ILin is equal to half of the input current (Iin/2).

As explained in part B, ∆Tov can be substituted with ∆T1,4,and then, the design criterion for L can be obtained from (57),(63), (67), and (69) as

L =2πNVin

√LrCp

∆iin. (70)

D. Primary MOSFET Selection

With the single capacitor instead of LC for the output filter,the peak voltage of vAB is clamped to Vo/2N . However,the existing resonance between Lr and the output capacitanceof the primary MOSFET (Coss) induces an overshooting ofvAB when the MOSFET is turned off. An experiment-basedempirical constant of 1.5 is accepted to represent such over-shooting. Hence, the voltage stress on the primary MOSFETs isobtained as

VAB = 1.5Vo

N. (71)

With the modeled symmetrical square wave current source inSection III, the current flowing through each MOSFET could beconsidered as the pulse current with an amplitude of Iin and aduty cycle of 0.5. Hence, the rms current of each MOSFET isobtained as

IFET_rms =Iin√

2. (72)

E. Voltage Stress of the Rectifying Diodes

For the rectifying diodes, the off-time voltage is clamped toVo, and ZCS turn-off is well ensured; hence, the voltage stressis Vo.

V. EXPERIMENTAL RESULTS

The proposed converter in Fig. 1 was implemented as part ofa PV module integrated converter (MIC), as shown in Fig. 15,with the following key specifications: maximum power pointtracking (MPPT) range Vin is 23–38 V [49], output voltage Vo

is 350 V, and maximum output power Po_max is 150 W.

Fig. 15. Picture of the PV MIC prototype with the proposed converter adoptedas the dc–dc part.

Besides the PV modules supported by Solarfun, major com-ponents of the prototype are listed as the following: Q1 andQ2 (IRFB4115GPbF), D1 and D2 (MUR860), transformer core(PC44PQ32/30Z-12) and turns ratio (N1 : N2 = 5 : 14), Lp =89 µH, Lr = 2.24 µH, Cp = 4.29 nF, Lin1 = Lin2 = 100 µH,and C1 = C2 = 2.2 µF. The input capacitor Cin was not ap-plied for the experimental illustration of the small input currentripple property of the proposed converter. Pulse frequencymodulation is adopted as the control method, and FPGA acts asthe controller. ADP3624ARDZ with 3.3-V compatible inputsand dual channel common ground 4-A high-speed driving isselected as the driver.

Figs. 16–22 show the experimental waveforms of the proto-type with an optimum design for Vin = 23 V, Vo = 350 V, andswitching frequency fs = 255 kHz. Fig. 16(a)–(c) shows vAB

and ipri at full, 20%, and 5% loads. vg1 and vg2 are the drivingsignals of Q1 and Q2, respectively. The waveforms show that,in full load range, two primary switches are both turned offwith ZCS, the voltage spikes and current overshooting are verysmall, and no additional clamping circuit is necessary. Theoscillation of vAB is mainly caused by the reverse recovery ofDQ1 and DQ2. Although the reverse recovery of the low-voltageMOSFETs’ antiparallel diodes is not severe, it is suggestedto seriously evaluate the reverse recovery performance of theantiparallel diode when selecting the MOSFET. An externalantiparallel Schottky diode would be preferred to bypass theinternal intrinsic diode if necessary.

It is clear that, as the load comes to light, the decreasedload current conduction period releases the clamping of vCp,and such mechanism enables downward resonance of vCp andgenerates lower initial energy for the resonance among Lr,Lp, and Cp. Although the leakage inductance is still designedaccording to heavy load condition for the purpose of ensuringfull load range ZCS operation of the primary switches, theovershooting of ipri is reduced, and a little redundant circulatingcurrent flows through the antiparallel diodes. Thereby, the nec-essary circulating energy for the ZCS operation of the primaryswitches is adaptive to the load and can be very low, and thelight load efficiency is not affected.

In Fig. 16(a)–(c), another important feature of the proposedconverter is revealed, i.e., the turn-on voltage of the primaryMOSFET also comes down as the load decreases. Hence, it

PELS TECH

Highlight


Fig. 16. Waveforms of vg1, vg2, vAB , and ipri at (a) full, (b) 20%, and(c) 5% loads.

can be concluded that quasi-ZVS is achieved at light load, andthis is also helpful in improving the light load efficiency of theproposed converter.

The primary active switches have the failure risk when theirZCS cannot be achieved. However, by following the proposeddesign method in Section III-D, a stable ZCS margin can beensured, and little failure risk comes to the practical. Fig. 17shows the waveforms of vAB and ipri when the proposed

Fig. 17. Full load direct startup waveforms of vAB and ipri.

converter starts up without any soft start techniques at full load.Hence, the robust ZCS operation of the primary active switchesin the proposed converter is well demonstrated by Figs. 16and 17.

However, if the freewheeling path of the two input inductors’current is broken in case of the gate driver or auxiliary powersupply losing earlier than the input power, it will destroy theprimary active switches. This is a common issue for current-fedconverters no matter if push–pull half- or full-bridge structuresare adopted as a current source generator. Such kind of situationshould be greatly taken care of and can be well handled inpractical engineering.

Fig. 18(a) and (b) shows the vCp, the voltage of D2 (vD2),and the current flowing through the rectifying diodes (irec) atfull and 20% loads, respectively. It can be seen that vCp isclamped to Vo/2 for most of the switching cycle at full load.Therefore, the circulating energy within the resonant tank issmall. vD2 is clamped to Vo without any overshooting. irecdecreases to zero with low slew rate. Thereby, ZCS operationis also well achieved for all of the rectifying diodes.

Fig. 19 shows iin, iLin1, and Vo when the two input inductorsare not coupled together. iLin2 is similar to iLin1 but with 180◦

phase shift; hence, the current ripple of iin is very small, andits frequency is twice the switching frequency. Then, a smallcost-effective nonpolarity cap would be enough to filter theinput ripple current. Although two input inductors seem bulkycompared to the voltage-fed converters, the proposed CFMRCeliminates the bulky input current ripple filters in which theelectrolytic capacitors are always necessary but have muchshorter lifetime compared to the inductors. Hence, the two inputinductors will not impact the volume of the whole converter,but they promise a longer lifetime to the converter. Since theinput current is relatively high, the two input inductors sharethe input current, which not only reduces the primary current ofthe transformer and the related conduction losses but alsoreleases the design and thermal stress of the inductor itselfcompared to a single inductor.

For further power density and efficiency improvement, cou-pled inductor techniques are finally applied to the two inputinductors. Fig. 20 shows the related waveforms. Compared tothe noncoupled inductors, coupled inductor techniques help in


Fig. 18. Waveforms of vCp, vD2, and irec at (a) full and (b) 20% loads.

reducing the inductance from 100 to 80 µH and, with only onecore (3C96-E28/17/11+I28/3.5/11) for the same current ripple,cancel part of the magnetic fluxes, hence reducing both coreand copper losses.

Fig. 21 shows the measured efficiency curve with fourFLUKE 289 multimeters within full load range. A peak ef-ficiency of 97.2% is achieved at 60% load, and the full loadefficiency is 96.2%.

Fig. 22 shows the loss breakdown results at full load for theproposed converter, and the unit is Wart. In Fig. 22, Pother

represents a summary of the losses caused by the reverserecovery of DQ1 and DQ2, the losses induced by the parasiticringing, and the losses on the PCB circuits and terminations.

Obviously, copper losses occupy the most 30% of the totalloss. The copper losses are mainly induced by the magnetizingcurrent. Compared with large resonant current flowing throughthe parallel resonant inductor Lp in conventional CFPRCs withLC output filter [32], such magnetizing current is limited andis essential in keeping the high boost capability and in achiev-ing ZCS of the rectifying diodes of the proposed converter.Moreover, the unavoidable magnetizing current only circulatesin the resonant tank, without going through the switchingnetworks; hence, the current rating of the silicon devices is notaffected, and only the secondary winding of the transformer

Fig. 19. Full load waveforms of iin, iLin1, and Vo without coupling the inputinductors.

Fig. 20. Full load waveforms of iLin1 and iLin2 with the applied coupledinductors.

Fig. 21. Measured efficiency curve.

should be designed with proper copper to reduce the conductionloss.

In Fig. 22, the turn-on losses of the two primary MOSFETstake up almost 9% total loss. However, as the load decreases,the turn-on voltage will decrease quickly and will not affect


Fig. 22. Loss breakdown of the proposed converter.

Fig. 23. Measured gain curve with the specified parameters.

the light load efficiency much as aforementioned. Moreover,even for lower input voltage applications, the hard switching-on impact for the efficiency will be much smaller. Moreover,the proposed converter certainly has the potential of achievingmuch higher dc gain while maintaining high efficiency as morethan 15 times dc gain has already been achieved with a turnsratio of only 5:14 in the current prototype.

Fig. 23 shows the measured dc voltage gain of the proposedconverter. With the designed parameters (QL = 5.6 and N =2.8), the experimental results demonstrate well the calculatedand simulated results shown in Fig. 8.

Finally, some modifications are applied to the resonant tankto meet the wide input voltage requirement. The efficiency datawith different input voltages at full load have been collectedand shown in Fig. 24. Here, the efficiency is 95.3%, with a 23-Vinput at full load. There is about 0.9% efficiency drop comparedto an optimum dc transformer oriented design. However, theefficiency curve is flat over the entire MPPT range, an averageefficiency of 95.9% was achieved, and a maximum efficiencyof 96.5% was recorded at a 38-V input.

VI. CONCLUSION

A novel high-efficiency high step-up dc–dc converter withlow input ripple current has been proposed for interfacing the

Fig. 24. Efficiency data with different input voltages at full load.

sustainable power sources, such as PV panels and fuel cells,which are characterized by low-voltage high-current output andhave strict current ripple requirement.

The operation principle of the proposed converter is wellintroduced. The current-fed half-bridge structure promises lowinput current ripple, low primary current of the transformer,high step-up capability, and common ground gate driving.The multiresonant tank creates ZCS condition for the primaryswitches, provides high voltage gain, and fully utilizes theparasitic parameters of the transformer. The adopted single-capacitor output filter helps in reducing the circulating energy,in limiting the overshooting of the primary current, and inachieving ZCS for the rectifying diodes all in full load range.In order to further improve the performances of the proposedconverter, coupled inductor and voltage doubler techniqueswere finally applied. All of these features guarantee the highperformance of the proposed converter.

Based on a comprehensive steady-state analysis for the pro-posed converter, the dc voltage gain and the ZCS conditionsof all active switches are derived. A design guideline for theproposed converter is also developed.

Withal, it is found that the proposed converter also workswhen the switching frequency exceeds its top limitation forZCS operation of the rectifying diodes. However, the relateddiscussion is beyond the scope of this paper.

The theoretical analysis and the merits of the proposed con-verter are verified on a 150-W prototype. An average efficiencyof 95.9% was achieved over the entire MPPT range (23–38 V),with a 350-V output at full load.

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Bo Yuan (S’07) was born in China in 1981. He re-ceived the B.S., M.S., and Ph.D. degrees in electricalengineering from Xi’an Jiaotong University, Xi’an,China, in 2005, 2007, and 2011, respectively.

He was an Intern with FSP-Powerland Technol-ogy, Inc., Xi’an; Delta Hangzhou Design Center,Hangzhou; and the Power Management Products(PMP) Division, Analog Devices, Inc., Shanghai, inthe summer of 2008, 2009, and 2010, respectively.He is now with the PMP Division, Analog Devices,Inc., Xi’an, Shaanxi 710075 China, where he en-

gages in developing digital power supply systems.

Xu Yang (M’02) was born in China in 1972. Hereceived the B.S. and Ph.D. degrees in electricalengineering from Xi’an Jiaotong University, Xi’an,China, in 1994 and 1999, respectively.

He has been a member of the faculty of the Schoolof Electrical Engineering, Xi’an Jiaotong Univer-sity, since 1999, where he is presently a Professor.From November 2004 to November 2005, he wasa Visiting Scholar with the Center of Power Elec-tronics Systems, Virginia Polytechnic Institute andState University, Blacksburg. He then came back to

Xi’an Jiaotong University and engaged in teaching and research in the powerelectronics and industrial automation areas. His research interests include soft-switching topologies, pulsewidth modulation control techniques and powerelectronic integration, and packaging technologies.

Xiangjun Zeng was born in China in 1975. Hereceived the B.S., M.S., and Ph.D. degrees inelectrical engineering from Xi’an Jiaotong Uni-versity, Xi’an, China, in 1998, 2001, and 2005,respectively.

From 2006 to 2007, he was with Aalborg Univer-sity, Aalborg, Denmark, as a Visiting Scholar. Hethen came back to Xi’an Jiaotong University andengaged in teaching and research in the power elec-tronics area. His research interests include renewableenergy harvesting and power electronic integration

technologies.

Jason Duan (M’10) was born in China in 1978.He received the B.S. and M.S. degrees in electricalengineering from Xi’an Jiaotong University, Xi’an,China, in 2000 and 2003, respectively.

He was with Delta Power Electronic Center,Shanghai, China, in 2003. He joined the Power Man-agement Products Division, Analog Devices, Inc.,Shanghai, in 2007, where he engages in developingdigital power supply systems.

Jerry Zhai was born in China in 1967. He re-ceived the B.S. degree in electrical engineering fromthe Huazhong University of Science and Technol-ogy, Wuhan, China, in 1988 and the Ph.D. degreein electrical engineering from Zhejiang University,Hangzhou, China, in 1994.

He is currently the Director of the Power Man-agement Products Division, Analog Devices, Inc.,Shanghai, China, and is responsible for the powerIC development and regional marketing and businessdevelopment. He is also responsible in leading the

power management application team for the Asian country sales.

Donghao Li was born in China in 1986. He re-ceived the B.S. degree in electrical engineering fromthe Taiyuan University of Science and Technology,Taiyuan, China, in 2008 and the M.S. degree in elec-trical engineering from Xi’an Jiaotong University,Xi’an, China, in 2011.

He is currently with the Second Academy of ChinaAerospace, Beijing, China, where he engages indeveloping power supplies with high reliability foraerospace application. His research interest is soft-switching topologies.

analysis and design of a high step-up current-fed...

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