Analog-to-DigitalConversion

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Common ADC Architectures

Flash

cascade of n comparatorsfastest (Gsps)low resolution (n ~ 8)more expensive

Common ADC Architectures

Successive Approximation

compares input to internal DACstarts with MSBsuccessively updates DAC to matchmid-range speed (Msps)

Flash

cascade of n comparatorsfastest (Gsps)low resolution (n ~ 8)more expensive

Common ADC Architectures

Successive Approximation

compares input to internal DACstarts with MSBsuccessively updates DAC to matchmid-range speed (Msps)

Flash

cascade of n comparatorsfastest (Gsps)low resolution (n ~ 8)more expensive

Sigma-Delta

oversamples then filtershighest possible resolutionlower-speed (<Msps)

Common ADC Architectures

Successive Approximation

compares input to internal DACstarts with MSBsuccessively updates DAC to matchmid-range speed (Msps)

Flash

cascade of n comparatorsfastest (Gsps)low resolution (n ~ 8)more expensive

Sigma-Delta

oversamples then filtershighest possible resolutionlower-speed (<Msps)

Integrating

compares against ramp referencecounts time until comparelowest-speed (<100ksps)

ATmega32U4 ADC

10-bit

successive approximation

12 channels

up to 15 ksps

ADC CONVERSIONCOMPLETE IRQ

8-BIT DATA BUS

15 0ADC MULTIPLEXERSELECT (ADMUX)

ADC CTRL. & STATUSREGISTER (ADCSRA)

ADC DATA REGISTER(ADCH/ADCL)

MUX

2

ADIE

ADAT

E

ADSC

ADEN

ADIF

ADIF

MUX

1

MUX

0

ADPS

0

ADPS

1

ADPS

2

MUX

3

CONVERSION LOGIC

10-BIT DAC+-

SAMPLE & HOLDCOMPARATOR

INTERNAL REFERENCE

MUX DECODER

MUX

4

AVCC

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC1

ADC0

REFS

0

REFS

1

ADLA

R

+

-

CHAN

NEL

SELE

CTIO

N

GAI

N SE

LECT

ION

ADC[

9:0]

ADC MULTIPLEXEROUTPUT

DIFFERENTIALAMPLIFIER

AREF

BANDGAPREFERENCE

PRESCALER

SINGLE ENDED / DIFFERENTIAL SELECTION

GND

POS.INPUTMUX

NEG.INPUTMUX

TRIGGERSELECT

ADTS[3:0]

INTERRUPTFLAGS

ADHSM

START

ADC13

ADC12

ADC11

ADC10

MUX

5

TEMPERATURESENSOR

3037766D–AVR–01/09

ATmega16U4/ATmega32U4

Figure 24-9. Analog Input Circuitry

24.7.2 Analog Noise Canceling TechniquesDigital circuitry inside and outside the device generates EMI which might affect the accuracy ofanalog measurements. If conversion accuracy is critical, the noise level can be reduced byapplying the following techniques:

a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digi-tal tracks.

b. The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 24-10.

c. Use the ADC noise canceler function to reduce induced noise from the CPU.d. If any ADC port pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress.

Figure 24-10. ADC Power Connections

Note: The same circuitry should be used for AVCC filtering on the ADC8-ADC13 side

ADCn

IIH

1..100 k!CS/H= 14 pF

VCC/2IIL

VCC

GND

100nF

Analog Ground Plane

(ADC0) PF0

(ADC7) PF7

(ADC1) PF1

(ADC4) PF4

(ADC5) PF5

(ADC6) PF6

AREFGND

AVCC

34

35

36

37

38

39

40

41

42

43

44

1

10µH

ADC : inputs

Vin

Vout

Vout = Vin

high-impedance inputlow-impedance output

ADC : inputs - buffering!

Anti-Aliasing & The Nyquist Theorem

recommended cutoff < 100 kHz

N > 2fmax

samplingrate

maximumdesired

frequency

Add a buffered RC low-pass filter before the input to the microcontroller

ADC : inputs

fc =1

2!RC

R

C

In Out

ADC : inputs - filtering!

ADC : process

set the voltage reference

set the ADC clock prescaler

disable some digital inputs

set up interrupts and triggering, if desired

select the desired analog input

enable conversions

start the conversion process

read the result

ADC : voltage reference

setting the MAX value (0x03FF) to one of the following:

external AREF (default!)

Vcc

2.56V

ADMUX : REFS1, REFS0

ADC : prescaler

set ADC clock to 50-200kHz

driven from system clock

ADCSRA : ADPS2, ADPS1, ADPS0

ADC : digital disable

turn off the digital input circuitry

DIDR0 : ADCnD (for n=0...7)DIDR2 : ADCnD (for n=8...13)

ADC : triggering

single-conversion (leave alone)

vs.

free-running

ADCSRA : ADATE

ADC : input selection

single ADC unit

12 multiplexed inputs

ADCSRA : MUX5ADMUX : MUX2, MUX1, MUX0

ADC: enable and start

must enable and start conversion

ADCSRA : ADENADCSRA : ADSC

ADC: results

16-bit pseudoregister

ADC