1

Analog Integrated Filters

C. PsychalinosAssist. Professor

UNIVERSITY OF PATRASDEPARTMENT OF PHYSICS

SECTION OF ELECTRONICS & COMPUTERSELECTRONICS LABORATORY

GR-26500, Rio, Patras, GREECE

2

Part-I: Overview

3

Classification of filters– Analog filters

A/Dconverter

DSP D/Aconverter

Analogreconstruction

filterIN OUT

Analogbandlimiting filter

– Digital filters

• Continuous-time

• Sampled-data

LC, RC, gm-C, Log-Domain,….

IN OUT

S/H SC, SIAnalog

reconstructionfilter

IN OUTS/HAnalog

bandlimiting filter

4

Digital vs. Analog Implementations

☺Programmability.☺Flexibility.☺Short design cycles.☺Good immunity to noise.☺Good immunity to manufacturing process tolerances.

Their performance is degraded in very high frequency applications.

5

The analog part provides the I/O interface (amplification, filtering, etc.) to the core of the chip which is digital.

6

The approximation problem • Frequency response of ideal filters

Lowpass filter Highpass filter

Bandpass filter Bandreject filter

The above responses could not be realized by causal systems.

Gain

ω0 ω c

1

Gain

ω0 ω c

1

Gain

ω0 ωc1

1

ωc2

Gain

ω0 ωc1

1

ωc2

7

• Practical specifications for a LP filter

• Characteristic transfer functions.

8

• Chebyshev vs Butterworth responses.

☺Higher attenuation in stopband.☺Steeper roll-off near the cut-off frequency.

More complex filter realizations.Less linear phase characteristics.

The choice of frequency response that should be implemented, requires trade-off between the above conflicting requirements.

9

⎟⎟⎠

⎞⎜⎜⎝

⎛−

−

≥

PB

SB

PB

SB

A

A

N

ωω

log

110110log 1.0

1.0

• Determination of the order of a Butterworth filter.

10

LC ladder filters

υ

R

Rin

1 3 5S

LCL

i i

LC C1

2

2 4

4

3 5 out

o

o

υ

υ υ υ

☺A doubly terminated LC ladder has the advantage of low sensitivity to component tolerances.☺LC ladder filters are mainly used in very high frequency

applications.

Inductors are heavy and bulky and thus they are difficult to adapt to IC realization.

11

Active RC filters• Miller integrator

C

R

Uo

Uin

RCssUsUsH

ino 1

)()()( −==

RCsH oo

1 ,)( == ωω

ω ωo: unity-gain frequency

Frequency response

12

• First-order filters

C

R1

Uo

Uin

R2

11

)()()(

212

+−==

CsRRR

sUsUsH

ino

21

2

1

1)(

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

c

RRjH

ωω

ω

Gain(dB)

ω

0

ωc=1/RC

-3Frequency response

The cutoff frequency is determined by the integrator’s time constant.

13

• Second-order filters (Biquads)

They are constructing using two-integrator loop.

Tow-Thomas Biquad

14

Design of high-order RC filters• Using second-order sections in cascade connection or

with multiple-loop feedback.

• Simulating the corresponding LC ladder prototypes.

– Functional simulation of LC ladders.– Topological simulation of LC ladders.

15

• Cascade connection of biquads

∏=

=n

jj sTsT

1)()(

Design procedure for maximizing the Dynamic Range•Pole-zero pairing: each pole is assigned to the closest zero.

•Section ordering: in the order of increasing values of Q. In addition, LP or BP are employed as first section and HP or BP are

employed as last section.

•Gain assignement: the gain constants are computed in such a way that the maxima of output voltages of all sections would be made equal.

☺Easy to design and tune.

Higher sensitivity, in comparison to other filter configurations.

16

• Functional simulation of LC ladders

VoC3

L2

C1

Rs

Vin RL

V1 V3

I2

⎟⎟⎠

⎞⎜⎜⎝

⎛−−=

−−=−

⎟⎟⎠

⎞⎜⎜⎝

⎛−

−−=−

2L

3

33

312

2

2s

1in

11

IRV

sC1V

)VV(sL1I

IR

VVsC1V

LC ladder prototype

Voltage/current equations

17

⎟⎟⎠

⎞⎜⎜⎝

⎛−−=

−−=−

⎟⎟⎠

⎞⎜⎜⎝

⎛−−−=−

RIVRR

sRC1V

)VV(R/sL

1RI

RIVRRV

RR

sRC1V

23L3

3

312

2

21s

ins1

1

1

1sRC

−RsL /

12 3

1sRC

−LR

R

V3=Vo

1

1

1

1-V1

sRR

sRR

Vin -I2R

Signal Flow Graph (SFG)

18

Active RC filter

Vo

R7

R2

C1a

rr

R3

R4R6

R5

C2a

C3a

R1Vin

19

• Topological simulation of LC ladders

I1 I2

V1 V2f(s) 21

21

I)s(f

kI

kVV

=

= L1i Z)s(fZ ⋅=

• General impedance converter-GIC

s2i Z)s(f1Z =

s R sR

Simulation of a grounded inductance

20

V1

I1 R2 R3 R4 C5

V2

I2

Antoniou circuit

RCs)s(f =

21

C1

RLL2

C1

RL s R

R2 R3 R4 C5C1

RL R

LC prototype

Equivalent circuit using GIC

Active RC filter

Steps of design

22

MOSFET-C filters

C

Uo

Uin

Vc

☺ Resistors are replaced by MOS transistors operated in linear region. Their values are electronically adjustable by the gate voltage.

☺ The developed active RC design methods can be directly used in MOSFET-C filters.They suffer from the nonlinearities introduced by MOS transistor.Reduced dynamic range in comparison to active RC filters

MOSFET-C Miller integrator

Fully balanced structures are used, in order to reduce the distortion introduced by MOS transistor.

In low-frequency applications (ωc=10krad/sec) in case of active RC filters,a resistor with value 5MΩ is required, in case that C=20pF.

23

Transconductance-C (Gm-C) filtersThe opamp frequency limitations (finite GBW) degrade the performance of active RC, MOSFET-C and SC filters.

Basic CMOS transconductance stage

)( 21 ininmout VVGi −⋅=

Box

m ILWCG

2μ

=

☺ Gm is electronically adjustable.☺ The stage has simpler structure, in comparison to the op-amp.

24

Gm

Vin

C

Vo

• Basic building blocks for functional simulation of LC ladders & biquads

Lossless integrator

sCG

VV m

in

o −=

Gm1

Vin

C

Vo

Gm2

Lossy integrator

1

1

22

1

+=

sGm

CGG

VV

m

m

in

o

25

VinVo

Gm1 Gm2 Gm3 Gm4 Gm5 Gm6G

m7Gm8 C2 C3 C4 C5 C6

5-th order LP Gm-C filter.

υ υ'

υ

υ'

υ υυ

-1 -1

-1 -1

1

1 1 1

1 1in

2

3

4

5out

1

RC s RC sRC s(L R) s1 532 41 111 1

+ +

+ +

(L R) s-1

+

-1

SFG

Configuration of filter

26

• Basic building blocks for topological simulation of LC ladders

Inductance simulation

Gm1

Gm2

C

Gm2 Gm1 Gm2

C

21 mmeq GG

CL =

27

Current-Conveyor (CCII) filters

∞→

→

∞→

=

=

z

x

y

xz

yx

RR

R

ii

0

υυDefinitions for CCII

RCssIsIsH

io 1

)()()( ==

• CCII lossless integrator

28

Current Amplifier filters

Mnc3

Mp1 Mp2 Mp3 Mp5

Mpc1 Mpc2 Mpc3 Mpc4

Mn2 Mn4

iin

Vb2

1 1 1: : :

Mnc2Mnc1

Mn1

1

VDD

Mnc5

Mpc6

Mn5

iout

1

oI

1

Mn3

iout

Mp6

VSS

Vb1

Mnc4

Mpc5

Mp4

: :

INOUT+OUT-

iin iout

ioutC

current amplifierIN

OUT-

OUT+

inout iAi ⋅=

mgRRCs

sH

/11

1)(

=+

=

• Lossy integrator

☺ The time-constant of integrator can be electronically adjusted

om ILWKg 2=

29

Switched-Capacitor (SC) filtersThe time-constants in active RC circuits could not be accurately implemented on chip.Large resistor values are needed in case of low-frequency applications.

1

1/ CT

VTVC

i ininav ==

1CTReq =

SC integrator

☺ The time-constant is:

☺ For a resistor value of 10MΩ, and using 100kHz clock, a capacitor 1pF is needed.

1

2CCT ⋅=τ

☺ The time-constant of integrator is defined by capacitors ration and thus the achieved accuracy is 0.1%.

☺ Tuning is achieved using that clock frequency.

30

)2Tt(C)t(q nin1n1 −= υΔ

)]Tt()t([C)t(q nono2n2 −−−= υυΔ

)t(q)t(q nn 21 ΔΔ =

12/1

21

ino

2/1z1

zCC

)z(V)z(V)z(H −

−

−−==

The previous direct replacement of resistors by switched capacitors is valid only in case that the clock frequency is much higher than the signal frequency.The frequency limitations of op-amps degrade the performance of SC filters.

Setting z=ejω:)2/sin(

2/j

C/C)(H 212/1 ωω

ωω −=

☺SC filters were designed using s-z transformations.

31

The circuit is sensitive to the effect of parasitic capacitances.

z1z

CCC

)z(V)z(V)z(H 1

2/1

2

1p1

ino

2/1 −−

−

+−==

☺ SC integrator insensitive to the effect of parasitic capacitances.

z11

CC

)z(V)z(V)z(H 12

11/1

in

o−−

−==

32

• Steps for designing SC filters

VoC3

L2

C1

Rs

Vin RL

V1 V3

I2LC ladder prototype

Continuous-time SFG

33

Discrete-time SFG using s-z transformation

⎟⎠⎞

⎜⎝⎛=−= −

−

2sin

T2 ,

zz1

T1s 2/1

1 ωΩ

The above SFG was derived using the LDI transformation

34

SC filter

35

Switched-Current (SI) filters

L2WC

iJVoxo

inTGS μυ

++=

Basic memory element

2/1

in

o2/1 Az)z(i

)z(iH −−==

•In time-slot 1 the voltage at gate capacitance is equal to:

•In time-slot 2 transistor M1 sustains its drain current, and thus:

☺ Capacitors are not further needed and as a result SI filter are fully compatible with standard digital CMOS process.

36

Dynamic current copier cell

2/1

in

o2/1 z)z(i

)z(iH −−==

☺ This cell is insensitive to the effect of MOS transistor parameters mismatch.

Scaling of output current is not available.

Full period delay cell

37

• SI lossless integrator

1

11/1

1)( −

−

−=

zzAzH

21/1

2sin

2)(ω

ωω

ω

ω

jj e

jAeH

−

⎟⎠⎞

⎜⎝⎛

=

Transfer function

Frequency response

☺ The time-constant of integrator is defined by the MOS transistors aspect ratio.

38

1

1

1/1

111

1)(−

−

+−

+=z

B

zB

A

zH

BB

T

j

BA

eH j

+

+=

221

)(1/1 ωω

frequency off-cut 2

2

gain frequency low

BB

T

BAa

o

o

+=

=

ω

• SI lossy integrator

Transfer function

Frequency response

39

• Effects of non-idealities in SI filters

MOS transistor parameters mismatch

40

Finite input-output conductance ratio of MOS transistor.

ioin

o

gg

zzizizH 21)()()(

2/11/2

+−==

−

0)(

2)(

)()(1)()(1/2

=

−=

−−=

ωθ

ω

ωθω

ωω

io

jij

ggm

jmeHeH

Regulated-cascode structures are used

⎟⎟⎠

⎞⎜⎜⎝

⎛≅

11

mds

ooc gggg

41

Clock-feedthrough effect in MOS switches.

•The error that is caused is similar to that of VT mismatch.

42

RFERENCES

1. T. Deliyannis, Y. Sun and J. K. Fidler, “Continuous-time active filter design”, CRC Press, 1999.

2. R. Schaumann and Mc E. Van Valkenburg, “design of active filters”, Oxford University Press, 2001.

3. M. Ismail, T. Fiez “Analog VLSI-Signal and information processing”, McGraw-Hill 1994.

4. C. Toumazou, F. J. Lidgey, and D. G. Haigh,”Analog IC design: the current-mode approach”, IEE Circuits and Systems Series 2, 1990.

5. C. Toumazou, J. B. Hughes and N. C. Battersby,”Switched-currents:an anlogtechnique for digital technology”, IEE Circuits and Systems Series 5, 1993.

6. M. S. Ghausi and K. R. Laker, “Modern filter design: active RC and switched capacitor”, Englewood Cliffs, NJ:Prentice-Hall Inc., 1981.

7. R. Gregorian, and G.C. Temes, “Analog MOS integrated circuits for signal Processing”, John Willey & Sons, 1986.

43

Part-II:Companding

filters

44

INTRODUCTION

☺ They open the door to elegantly realizing a linear system with inherently non-linear building blocks, and may achieve the advantageous potential of companding (compress-expand) signal processing.

Log-Domain filter expandercompressor

in out

45

•Linear and companding signal processing

46

20 20.5 21 21.5 22 22.5

-30

-20

-10

0

10

20

(mV )

20 20.5 21 21.5 22 22.5

-15

-10

-5

0

5

10

15

2 (mV )

Waveforms at the internal nodes of a typical log-domain system.

☺ Companding filters have potential for low-voltage operation, as the signal swings within filter are typically less than 100mV.

47

Log-Domain Filters

48

Methods for designingLog-Domain filters

Using the well-known state-space synthesis approach in linear domain, and an appropriate mapping of the resulted equations.

Using the well-known Signal Flow Graph (SFG) synthesis approach in linear domain, and a set of complementary operators.

A large number of equations is needed in case of high order filters.

☺This method is more simpler than the ESS.

By following the concept of Wave Active Filters.

☺ The design procedure of high-order filters is quite facilitated.

☺Modular filter structures are derived.

49

Log-Domain filters synthesis using the SFG approach

Representation of a Log-Domain filter using complementary operators

50

BJT Translinear principle

For any closed loop comprising any number of pairs of clockwise and counter-clockwise forward-biased identical junctions, the product of currents for the elements in one direction is equal to the corresponding product in the opposite direction.

∏∏ =ccw

Ccw

C II

•As an extension to the above principle, when a voltage source is introduced into the loop, then:

∏∏ ⋅=ccw

CV

cwC IeI T

sυ

51

Non-linear transconductance

Io

Io

VCC

iOUT

VEE

E+iOUT

OUTυ̂INυ̂

INυ̂

OUTυ̂

Io

IoVCC

iOUT

VEE

INυ̂

OUTυ̂

E-iOUT

INυ̂

OUTυ̂

Io

T

OUTIN

OUTV

ˆˆ

o eIi

υυ −

⋅=

Positive cell

Negative cell

52

Ioi

IoOUT

υ̂

Io

Io Ioυ̂

i

⎟⎟⎠

⎞⎜⎜⎝

⎛ +⋅=

−⋅=

o

oT

oVˆ

o

IIilnV)i(LOG

I e I)ˆ(EXP Tυ

υ

Implementation of complementary operators

LOG

EXP

53

Log-Domain integrators

iCE-

Io

E+Io

INυ̂

OUTυ̂

Lossless integrator

T

OUT

T

OUTINOUT

CV

oV

o eIeIdtd

Ci

υυυυ

ˆˆˆˆ −

−

⋅−⋅=⋅=

[ ] dt EXPEXPINOUT ∫ ⋅= )ˆ(

1)ˆ( υτ

υ

The time-constant of integrator is:

o

TI

CV=τ

☺ Electronic tuneability using a DC current source.

The time constant is depended from temperature.

∫INυ̂ OUTυ̂

54

Lossless integrator-subractor

E-

Io

E+

Io

C

1INυ̂

2INυ̂ OUTυ̂

∫ OUTυ̂2

ˆIN

υ

+

1ˆ

INυ

1

-1

55

Lossy integrator

∫INυ̂ OUTυ̂+

-1

IoE+

Io

INυ̂ OUTυ̂

☺ Damping is achieved using a DC current source.

( )[ ] ( ) ( )OUTINOUT

ˆEXPˆEXPˆEXPdtd υυυτ −=

56

High-order Log-Domain filters

Operational simulation of all-pole LC ladders

L2

C1 C3 RL

RS

sυ oυ

LC ladder prototype

1

1sRC

−RsL /

12 3

1sRC

−LR

R

V3=Vo

1

1

1

1-V1

sRR

sRR

Vin -I2R

Linear domain Signal Flow Graph (SFG)

57

Transposition to Log-Domain using the following rules:

•A LOG block is placed at the output of each integrator.

•An EXP block is placed at each input of integrators (before scaling).

•A LOG block is placed at the input of the system.

•An EXP block is placed at the output of the system.

iS

LOG

EXP1

1sRC RsL /

12 3

1sRC

1

-1

-1

1

1

-1 -1

iout

58

Implementation using Log-Domain cells

Iois

Io

Io

Io Io

iout

Io

E+

Io

E-

Io

E+

Io

C1

E-

Io

E+

Io

C2

IoE+

Io

C3

59

Operational simulation LC ladders with finite zeros

LC ladder prototypeL2

C2C1 C3 RL

RS

i2

iS iL

1υ 3υ

sυ

)sRC(sRC

1322S

eq,11

υυυυ +′−′=

Differentiation is required:

☺ Alternative form without differentiation:

3eq,1

22S

eq,11 C

C)(

sRC1 υυυυ +′−′=

60

Log-Domain Signal Flow Graph (SFG)

eq,1sRC1

R/sL1

2

eq,3sRC1

1−

1

eq,1

2CC

eq,3

2C

C1

1−

LOG

EXPiS 1

1 1 iout

2υ̂ ′

*3υ̂

*1υ̂

1̂υ

3υ̂

1−

1

1−

61

Implementation using Log-Domain cells

2ˆ

INυ OUT

υ̂

1ˆ

INυ

Io

E-

KIo

E+

KIo

E+

Io

1ˆ

INυ

2ˆ

INυ

OUTυ̂

1:1

1:K

Log-Domain summing block

)ˆ(EXPK)ˆ(EXP)ˆ(EXP21out

υυυ ⋅+=

62

Log-Domain elliptic filter

E-Io

Iois

E-Io

E+Io

E+Io

E-Io

E-

Io

E+Io

Io

Io Io

iout

1̂υ

*1̂υ

2υ̂′

*3υ̂

3υ̂

1Ĉ

2Ĉ

3Ĉ

1:11:K

1:11:K

63

0E+000 1E+007 2E+007 3E+007 4E+007

Frequency, (Hz)

-80

-70

-60

-50

-40

-30

-20

-10

0Gain(dB)

Ideal case

Realistic model

Frequency response of the filter @ modulation index factor 0.8

The frequency response of a Log-Domain filter is evaluated using large-signal transient simulations and FFT analysis.

The AC analysis of HSPICE is valid only for small modulation index factor !!!

64

Non-linear analysis

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Modulation index

-70

-65

-60

-55

-50IMD3(dB)

A two-tone test was performed, in order to measure the third-order intermodulation distortion factor.

☺ The IMD3 was -52dB @ modulation index equal to 1.

65

Noise analysis

0.01 0.1 1

Modulation index

0

10

20

30

40SNR(dB)

☺ The achieved Dynamic Range was 35dB.

66

Log-Domain Wave filters

Wave variables

1A1B

+

−

2A

2B

+

−

1,2)(k R

iA kkk =+=υ

1,2)(k R

iB kkk =−=υ

incident wave

reflected wave

67

Scattering parameters description

Lτ

Passive element Symbol of wave equivalent in the log-domain

⎥⎥⎦

⎤

⎢⎢⎣

⎡⋅

⎥⎥

⎦

⎤

⎢⎢

⎣

⎡

+=

⎥⎥⎦

⎤

⎢⎢⎣

⎡ ⋅

⋅

1

2

1

s 1

1

2 11 A

A

s

L

B

B

L

Ls

τ

ττ1s

1

L+⋅τ1 1

1 -1

-1 1

A1 A2

B1 B2

+

+ +

68

lossy integrator

1Â 2Â

2B̂1B̂

EXP

LOG1 -1

1 1

1-1

+

+ +

Transposition of linear domain SFG to the Log-Domain SFG

Lτ

1B̂ 2B̂

1Â 2Â

69

Io

E+

Io

E-

Io

E+

Io

C

1INυ̂

2INυ̂ OUTυ̂

1INυ̂

2INυ̂ OUTυ̂

1INυ̂

2INυ̂

OUTυ̂

1INυ̂

2INυ̂ OUTυ̂

1INυ̂

2INυ̂

OUTυ̂

INυ̂

OUTυ̂

INυ̂ OUTυ̂

Lossy integration

Subtraction

Summation

Inversion

70

L Lτ

1B̂ 2B̂

1Â 2Â

RL

L 2=τ

Cτ

1B̂ 2B̂

1Â 2Â

RCC 2=τ

C

Prototype Log-Domain wave equivalent

2RC

C =τC

Cτ1Â

2Â

1B̂

INVERTER

INVERTER

2B̂-1

-1

RL

L2

=τL

1B̂ 2B̂

1Â 2Â

INVERTER

INVERTER

Lτ-1

-1

Log-domain wave equivalents of 1st-order blocks

71

Log-domain wave equivalents of 2nd-order blocks

1B̂ 2B̂

1Â 2Â

1B̂ 2B̂

1Â 2Â

1Â2Â

1B̂

INVERTER

INVERTER

2B̂

1B̂ 2B̂

1Â 2Â

INVERTER

INVERTER

Prototype Log-Domain wave equivalent

-1

-1

-1

-1

LC

L

C

L

C

CL

CL

RQ

LC

21

10

=

=ω

LCRQ

LC

2

10

=

=ω

CL

RQ

LC2

10

=

=ω

LCRQ

LC

2

10

=

=ω

ωο Q

ωο Q

ωο Q

ωο Q

72

Log-Domain wave filter

c,outi

EXP

ini

LOG

INVERTER

INVERTER EXP

outi

INVERTER

INVERTER

☺ Modular filter structures are derived.

2C

3L1LSR

LRsυ outυ4C

5L

☺ A quick design procedure is offered.

The circuit complexity is increased in comparison to the leapfrog filters.

73

Effects of non-idealities

Effect of non-zero RE

INV̂OUTV̂

OUTi

0I

0I

EEV

CCV

ER ER

The cut-off frequency is shifted, while the filter shape remains unchanged.

0

ˆˆ

0

IRV

OUT

BT

OUTIN

eII βυυ

+

−

=

74

( ) ( )[ ] ( ) ( ) ( )∫ +−=+ 121100 ˆˆˆˆ

ˆυυ EXPAEXPAEXPEXP

dtd

IVC

VRIV T

T

ET

• Input-output relationship for a lossy integrator

☺ The effect of non-zero RE is compensated by multiplying the value of DC current source by a factor

( )T

ETRE V

RIVk 0+=

-60.0

-50.0

-40.0

-30.0

-20.0

-10.0

0.0

10.0

0.0E+00 5.0E+05 1.0E+06 1.5E+06 2.0E+06 2.5E+06 3.0E+06 3.5E+06 4.0E+06

Συχνότητα (Hz)

Κέρδος

(dB

)

Ω= 0ER

Ω= 30ER

Ω= 60ER

75

Effect of BJT transistor finite beta.

( )∫ dtC .1

1ˆINυ

2ˆINυ0υ̂

EXPLOG

β3k−

β3k

βf−−1

The finite beta introduces a scalar error and an extra feedback path.

The cut-off frequency and the phase response of the filter are changed.

☺ The above imperfections can be electronically removed.

76

E-

E+

E+

1B̂E-

E+

E+

E-

E+1Â

2B̂

2Â

E+

β30 / kI

1̂υ0Ifβ

Ĉ

0I

0I

β30 / kI

β30 / kI

β10 / kI

β10 / kI

β10 / kI

β20 / kI

β20 / kI

β20 / kI

β30 / kI

Wave equivalent of a floating inductance, with additional circuitry for removing the effect of finite beta.

-10.0

-8.0

-6.0

-4.0

-2.0

0.0

2.0

0.0E+00 5.0E+05 1.0E+06 1.5E+06 2.0E+06

Συχνότητα (Hz)

Κέρδος

(dB)

β=100

Αντισταθμισμένη

Ιδανική

77

Effect of non-zero RB.

☺ This deviation is canceled by following the same procedure as in non- zero RE.

INυ̂

OUTυ̂

OUTi

0I

0I

EEV

CCV

BR BR

The cut-off frequency is shifted, while the filter shape remains unchanged.

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0

0.0

5.0

1.0E+05 6.0E+05 1.1E+06 1.6E+06 2.1E+06 2.6E+06

Συχνότητα (Hz)Κέρδος

(dB

)

0=BR

KRB 2=

KRB 5=100=β

0

ˆˆ

0

IRV

OUT

BT

OUTIN

eII βυυ

+

−

=

78

Combined effects

E-

E+

E+

1B̂E-

E+

E+

E-

E+1Â

2B̂

2Â

E+

AVkkkI 3350 / β

1̂υ50, / kIf AVβ

Ĉ

50 / kI

AVkkkI β150 /

AVkkkI 3350 / β

AVkkkI 3350 / β

AVkkkI 3350 / β

AVkkkI 1150 / β

50 / kI

AVkkkI 1150 / β

AVkkkI 2250 / β

AVkkkI 2250 / β

AVkkkI 2250 / β

79

-50.0

-40.0

-30.0

-20.0

-10.0

0.0

10.0

1.0E+05 5.0E+05 9.0E+05 1.3E+06 1.7E+06 2.1E+06 2.5E+06 2.9E+06

Συχνότητα (Hz)

Κέρδος

(dB

)

Μη ιδανική

Ιδανική

Αντισταθμισμένη

100=β

Ω= KRB 1Ω= 30ER

The values of factors are calculated using a fitting algorithm.

80

Square-Root-Domain filters

81

Representation of a Square-Root-Domain filter using complementary operators

A method for designingSquare-Root-Domain filters

IN1in

111

2 n22 INin

OUT out

OUT out

υi

i

i

υ i

O

O

O

O

^

^

^

^

SQ SQ

SQ SQ

Linearoperation

SQRTSQRT

SQRTSQRT

. .. ... .. . ...

Linear system

x - domain cellυ

υ

82

• Definition of operators

oi

υ=

I

K

O

O

O

.

^

VDD

VSSSQRT(i)

o

DD

SS

i=SQ( )

υ

υI

V

KO

O

O

^

^

V

.

( ) oT IVKSQ −−= 2ˆ2

)ˆ( υυ TO VKIiiSQRT ++= )(2)(

SQ[SQRT(i)]=i

83

Square-Root-Domain integrators

O

O

IN

IN

C

OUT

IN a

o

X

Y

Y

Z

XZ1

Wi

i

i

υ

υI

I

.C

OUT

OUT

o

aIN

i

i

IIi

1:1

K

K

MULTIPLIER / DIVIDER # 1

GEOMETRIC-MEAN

^

^

a

X

Y

Z

W

I

MULTIPLIER / DIVIDER # 2

OUTo

ao

iIII

IN

OUT

VDD

V

V

SS

SS

Mc

oI

OUTo iI

OUTo iI

Z2

Z

YXW i

iii =.

X Yi i= .

Zni

Z

YXW i

iii.

.

.

.

.

.

.

=

VDD

1:1

IN OUTυ υOO^ ^SQ SQRT

∫Lossless integrator

OUTOUT

OUT

iIII

iIIi

dtd

Cio

ao

o

aINc −==

υ̂

( )∫ ⋅= dt ˆSQ1)ˆ(SQ INOUT υτυ

a

o

IKIC

2=τ

The time-constant of integrator is:

☺ Electronic tuneability using a DC current source.

84

Lossless integrator-subtractor

IN1

IN2

OUT

υ

υ

++

-υO

O

O

^

^

^

SQ

SQ

SQRT

∫

O

O

IN1

IN1

C

OUT

IN1 a

o

X

Y

Y

Z

XZ1

Wi

i

i

υ

υI

I

.C

OUTi

1:1

K

K

MULTIPLIER / DIVIDER # 1

GEOMETRIC-MEAN

^

^

X

Y

Z

W

MULTIPLIER / DIVIDER # 2

IN1

OUT

VDD

V

V

SS

SS

Mc

Z2

Z

YXW i

iii =.

X Yi i= .

Zni

Z

YXW i

iii.

=

VDD

1:1

O

IN2

IN2

IN2 a

ii

υI

1:1

K^

IN2

VDD

VSS

85

Lossy integrator

IN OUTυ ++

-υOO^ ^

SQ

SQ

SQRT

∫

dampF

O

O

IN

IN

C

OUT

INa

o

X

Y

Y

Z

XZ1

Wi

i

i

υ

υI

I

.C

OUTi

K

K

MULTIPLIER / DIVIDER # 1

GEOMETRIC-MEAN

^

^

IN

OUT

VDD

V

V

SS

SS

Mc

Z2

Z

YXW i

iii =.

X Yi i.Zni =

VSSMF1 MF2

1:1

DD

1:1

V

1: aIIo

( )[ ] ( ) ( )OUTINOUT

SQFSQSQdtd

damp υυυτ ˆˆˆ −=

☺ Damping is achieved using a current mirror.

86

Complete system of current integrator

INOUT

υυ

outin ii . .^

^

SQ SQSQRTSQRT

∫

x - domain cell

ININ

C

OUT

IN a

o

X

Y

Y

Z

XZ1

Yii

i

υ

υ I

I

.C

OUTi

K

K

MULTIPLIER / DIVIDER # 1

GEOMETRIC-MEAN

^

^

a

X

Y

Z

W

I

MULTIPLIER / DIVIDER # 2

V

V

SS

SS

Mc

oI

Z2

K

VSS

VDDI O

ini

K

VSS

VDDIO

outi

x - domain cell

Mout

Min

Z

XW i

iii =

.W

Y

Z

XW i

iii =

.

XZn Yii i= .

VDD DDV

87

IN

C

OUT

a

o

X

Y

Y

Z

XZ1

Y

i

i

υ

I

I

.C

OUTi

K

MULTIPLIER / DIVIDER # 1

GEOMETRIC-MEAN

^

a

X

Y

Z

W

I

MULTIPLIER / DIVIDER # 2

VSS

Mc

oI

Z2

+IO

K

VSS

VDDIO

outi

Mout

Z

XW i

iii =

.W

Y

Z

XW i

iii =

.

XZn Yii i= .

DDV

Simplification of circuit:

88

MOS Translinear principle

∑∑ =ccw

D

cw

DLW

ILW

I//

In the closed loop, the gate-source voltages are in series, with equal number of transistors arranged clockwise and counter-clockwise.

89

Stacked topology

Suffers from a strong influence of the body effect.

☺ Offers simple circuits.

90

Up-down topology

Requires some extra circuitry, in comparison with the stacked configuration.

☺ The body effect is much smaller than that in case of stacked topology.

91

Electronically simulated loop topology

☺ The body effect is completely eliminated.

The achieved bandwidth is limited by the speed of additional circuitry.

A relative large number of elements is required in same cases.

The average of the gate-source voltages of transistors M1 and M2 is forced equal to the average of the gate-source voltages of transistors M3 and M4.

92

Basic SQRD blocksCurrent geometric-mean circuit

M

MM

M M M M

M MM M

.

.

.

.

V

V

I I

I

X' Y

DD

SS

X1 Y Y1XY

c c

c

p p p p

K K4K

K K K K

1:1

K

X XZ

XY

XY

Y

YY i ii

i

i

i

ii

=2

X'Y

X Z1Y

υ

υ

υ P2 P3 P4P1

3 4

MZ

XZ1 Yii i=

M X

K .

MMVDD

1:11 2

Xi

Z1

X'

MMVDD

1:1o o1

Z

Xi Z1i.

Zn

XZn Yii i=

Mon

. .

.

1:1

2:1

Z1

Y

i

Y

X Z1

GEOMETRIC-MEAN

i

i X

XZn Yii i=Zn

Zni

YXXY iii +=

YX ii2iz ⋅=

•The voltage averaging subcircuit produces a gate voltage υX’Y , which is forcedto be equal with the average of the gate voltages of MX, and MY.

MOS translinear principle:

Output current:

93

Current multiplier topology

.

.

.

..

.

...

V

1:1 1:1

II II

I

DD

c c c c

c

pp pp pp pp

K KK KK 4K4K

KK KK KK KK

KK

X

X XY ZW

XY

Y

Y

W

W+

Z

Zi

i i i

ii

i

i

i

i

i

i

X Y W

2A

M M M MM MMM MX Z1 W W1XY ZWYX1 Y1

Z

YXW i

iii =

.

.K

Zi

Z

MZ

VSS

. .

.

I cVSS

It is constructed by two properly connected geometric-mean circuits.

X

Z

Y

i

i

i ZYX

W iiii =

X

YZ

WWi

MULTIPLIER / DIVIDER

.

94

Performance of the proposed multiplier.

Time, (ms)

Error,(μΑ)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5New[11]

•Comparison with a multiplier based on up-down topology.

TH D, (dB)

Amp litude,(μΑ)0 10 20 30 40 50

-76

-72

-68

-64

-60

-56

-52

☺The minimum supply voltage requirement for both proposed circuits is:

GSSATDSVVVDD += ,2min

.

☺ A reduction of about 50% for the required transistor area is achieved in the proposed circuit.

95

High-order Square-Root-Domain filters

Operational simulation of all-pole LC ladders

LC ladder prototype

Linear domain Signal Flow Graph (SFG)

υ

R

Rin

1 3 5S

LCL

i i

LC C1

2

2 4

4

3 5 out

o

o

υ

υ υ υ

υ υ'

υ

υ'

υ υυ

-1 -1

-1 -1

1

1 1 1

1 1in

2

3

4

5out

1

RC s+1 RC s+1RC s(L R) s1 532 41 111 1

+ +

+ +

(L R) s

96

Transposition to Square-Root Domain using the following rules:

•A SQRT block is placed at the output of each integrator.

•A SQ block is placed at each input of integrators (before scaling).

•A SQRT block is placed at the input of the system.

•A SQ block is placed at the output of the system.

i υ'̂ ^

^^υ̂ υ υ

υ'

i

-1 -1

-1 -1

1

1 1

1 1in 2

1 3 5

4

out

RC s+1 RC s+1RC s(L R)s1 5321 111

+ +

+ +

SQ

SQRT

(L R)s41

97

Implementation using Square-Root-Domain cells

o

o

iout

iin

I

I

K

K

O

O .

OUT

OUT

OUT

IN2

IN2

IN2

IN1

IN1

IN1

integrator

integrator

integrator

subtractor#1

#2

#3subtractor

subtractor

OUT

IN2

IN1

integratordamped

subtractor

OUTINdampedintegrator

V

VDD

DD

V

V

SS

SS

.

.

..

.

98

Frequency response of the filter @ modulation index factor 0.8

The frequency response of a Square-Root-Domain filter is evaluated using large-signal transient simulations and FFT analysis.

The AC analysis of HSPICE is valid only for small modulation index factor !!!

Gain, ( dB)

Frequency, (Hz)

Level 1

Level 3

0 25000 50000 75000 100000

-60

-50

-40

-30

-20

-10

0

Gain, (dB)

Frequency, (Hz)

Level 1Level 3

0 10000 20000 30000 40000 50000

-7.4

-7.2

-7.0

-6.8

-6.6

-6.4

-6.2

-6.0

99

0 25000 50000 75000 100000

-80

-70

-60

-50

-40

-30

-20

-10

0Gain, (dB)

Frequency, (Hz)

Iα=6μΑ

Iα=10μΑ

Iα=12μΑ

Electronic tuneability of Square-Root-Domain filters.

100

Non-linear analysis

A two-tone test was performed, in order to measure the third-order intermodulation distortion factor.☺ The IMD3 was -42dB @ modulation index factor equal to 1.

5 10 15 20 25 30 35 40 45 50

-65

-60

-55

-50

-45

-40THD, (dB)

Amplitude, (μΑ)

101

Noise analysis

☺ The achieved Dynamic Range was 49.7dB.

0.1 1.0 10.0

0

5

10

15

20

25

30

35

40

45

50

55

60SN R, (dB)

Amplitude, (μΑ)

102

[1] E. Seevinck and R. Wiegerink, ‘Generalized translinear circuit

principle’, IEEE J. Solid-State Circuits, vol.26, pp.1098-1102, Aug.

1991.

[2] M. Eskiyerli, A. Payne: ‘Square-root domain filter design and

performance’, Analog Integrated Circuits and Signal Processing,

vol.22, pp.231-243, Mar. 2000.

[3] J. Mulder, A.C. Van der Woerd, W. A. Serdjin, A. H. M. Van

Roermud: ‘Current-mode companding x – domain integrator’,

Electron. Lett., vol. 32, pp.198-199, Feb. 1996.

[4] A. J. Lopez-Martin and A. Carlosena, ‘Geometric-mean based

current-mode multiplier/divider’, in Proc. IEEE Int. Symp. Circuits

Syst. (ISCAS), 1999, pp. 342-345.

[5] A. J. Lopez-Martin and A. Carlosena, ‘A 3.3V tunable current-mode

square-root domain biquad’, in Proc. IEEE Int. Symp.Circuits Syst.

(ISCAS), 2000, pp. 5-8.

[6] A. J. Lopez-Martin and A. Carlosena, ‘A systematic approach to the

synthesis of square-root domain systems’, in Proc. IEEE Int. Symp

Circuits Syst.(ISCAS), 1999, pp. 306-309.

[7] R. Wiegerink, ‘Analysis and synthesis of MOS translinear circuits’,

Dordrecht, The Netherlands: Kluwer Academic Publishers Group,

1993.

[1] B. Gilbert: “Translinear circuits: An historical overview”, Analog Integrated

Circuits and Signal Processing’, vol.9, no.2, pp.95-118, Mar. 1996.

[2] D. R. Frey: “Log-domain filtering: an approach to current-mode filtering”, IEE

Proc., Part-G, vol.140, no.6, pp. 406-416, Dec. 1993.

[3] D. R. Frey: “Exponential state-space filters: a generic current mode design

strategy”, IEEE Trans. Circ. Systems-I, vol.43, no.1, pp.290-305, Jan. 1996.

[4] E. M. Drakakis, A. J. Payne and C. Toumazou: “Log-domain state space: a

systematic transistor level approach for log-domain filtering”, IEEE Trans.

Circ. Systems- II, vol.46, no.3, pp.290-305, Mar. 1999.

[5] D. Perry and G. W. Roberts: “The design of log-domain filters based on the

operational simulation of LC ladders”, IEEE Trans. Circuits Syst. II,vol. 43,

no.11, pp.763-774, Nov.1996.

[6] V. W Leung and G. W. Roberts: “Effects of transistor nonidealities on high

order log-domain ladder filter frequency responses”, IEEE Trans. Circuits Syst.

II, vol.47, no.5, pp.373-387, May 2000.

[7] D. R. Frey: “LOG-domain filtering for RF applications”, IEEE J. Solid-State

Circuits, vol.31, no.10, pp.1468-1475, Oct. 1996.

REFERENCES

Log-Domain Square-RootDomain

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