analog integrated circuits lecture 1: mos physics and...

Analog Integrated Circuits Lecture 1: MOS Physics and Current

Mirrors ELC401A – Fall 2013

Dr. Mohamed M. Aboudina [email protected]

Department of Electronics and Communications Engineering Faculty of Engineering – Cairo University

mailto:[email protected]

© Mohamed M. Aboudina, 2013

Contents

• MOS: Device Physics – MOS Structure and Threshold Voltage

– MOS I-V Characteristics

– MOS Non-idealities (Channel length modulation, Body effect)

– MOS Intrinsic capacitance and small-signal model

– 𝜏𝑇

– Velocity Saturation

– Subthreshold Conduction

• Current Mirrors


MOS Structure

• A piece of polysilicon with a width of W and length of L on top of a thin layer of oxide defines the gate area.

• Source and drain areas are heavily doped.

• Substrate usually tied to the most negative voltage.

• Leff = L – 2LD, where LD is the side diffusion of source and drain.


MOS I-V characteristics

• For 𝑉𝐺𝑆 > 𝑉𝑇𝐻 , current flows between source and drain by drift (Resistive current).

• This is a voltage-dependent (nonlinear) resistor.

• For low VDS,

– 𝐼𝐷 = 𝜇𝐶𝑜𝑥𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆



• For higher VDS (General Formulas) – find the current, multiply charge density by charge velocity.

– 𝐼𝐷 = 𝑊𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉 𝑥 − 𝑉𝑇𝐻 𝜇𝑛𝑑𝑉 𝑥

𝑑𝑥

– 𝐼𝐷 = 𝜇𝑛𝐶𝑜𝑥𝑊

𝐿[ 𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆 −

1

2𝑉𝐷𝑆

2 ]

• 𝑅𝑜𝑛 ≅1

𝜇𝑛𝐶𝑜𝑥𝑊

𝐿𝑉𝐺𝑆−𝑉𝑇𝐻



• Voltage across the inversion layer is fixed (independent of the VDS) from that point on.

• Depletion region from the pinch-off point to the drain.

• Device enters “Saturation Region”.

• 𝐼𝐷 =1

2𝜇𝑛𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2 =1

2𝜇𝑛𝐶𝑜𝑥

𝑊

𝐿𝑉𝑒𝑓𝑓

2 (quadratic)

• Voltage-Dependent Current Source


MOS: In Saturation

• In saturation, ID is independent of VDS

• 𝑅𝑜𝑢𝑡 = ∞

• 𝐺𝑜𝑢𝑡 = 0


MOS: Channel length modulation

• Channel length modulation by VDS causes the saturation current to vary with VDS.

–𝜕𝐼𝐷

𝜕𝑉𝐷𝑆=

𝜕𝐼𝐷

𝜕𝐿×

𝜕𝐿

𝜕𝑉𝐷𝑆=

𝐼𝐷𝑆𝑎𝑡

𝛼𝐿 𝑉𝐷𝑆−𝑉𝑒𝑓𝑓

– Where: 𝜕𝐿

𝜕𝑉𝐷𝑆 : Depletion region

modulation.

– 𝛼 =𝑞𝑁𝑑𝑜𝑝

2𝜖𝑠𝑖

–𝜕𝐼𝐷

𝜕𝑉𝐷𝑆=


𝛼𝐿 𝑉𝐷𝐺+𝑉𝑇𝐻

• Non-zero o/p conductance



Region of Operation: Conceptual Visualization

• VDS < VGS-VTH MOS transistor in linear region.

• In linear region, MOS transistor acts as a resistor or a switch.

NMOS PMOS

MOS Transistor


Transconductance (𝑔𝑚)

• Transistor Transconductance:

𝑔𝑚= 𝜕𝐼𝐷

𝜕𝑉𝐺𝑆

=(μ𝐶𝑜𝑥𝑊

𝐿)𝑉𝑜𝑑

=2𝐼𝐷

𝑉𝑜𝑑

= 2(μ𝐶𝑜𝑥𝑊

𝐿)𝐼𝐷

MOS Transistor


Small Signal Model

𝑟𝑜 = 1

𝜕𝐼𝐷𝜕𝑉𝐷𝑆

= 1

λ𝐼𝐷 𝜕𝐼𝐷

𝜕𝑉𝐷𝑆=


𝛼𝐿 𝑉𝐷𝐺+𝑉𝑇𝐻

𝐼𝐷 = 𝐼𝐷𝑆𝑎𝑡

𝜆 ∝1

𝐿

MOS Transistor


Useful Model

• Small Signal:

𝒈𝒎 𝒗𝒈𝒔

𝑣𝒈𝒔

+

-

𝒓𝒐

MOS Transistor


Special Cases

𝒓𝒐 Bias point

𝟏

𝒈𝒎


Contents

• MOS Transistor Physics

• Current Sources – Basics

– Cascode Current Sources

– High-Swing Current Sources (optimum biasing)

– Current Mirror Systematic Mismatch

• Random Transistor Mismatch

Current Sources


Basics

• Compliance Characteristics: – 𝑉 > 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 for I=Ifixed

– For a single MOS transistor: 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 = 𝑉𝑒𝑓𝑓

– 𝑉𝑒𝑓𝑓 =2𝐼

𝜇𝑛𝐶𝑜𝑥𝑊

𝐿

– For a given (I) and a given compliance voltage (Veff), find 𝑊

𝐿.

– 𝐼, 𝑉

Leads to W and L (Geometry is a consequence)

• Output Resistance: (Ideally 𝑅𝑜𝑢𝑡

𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑

∞)

– For a single MOS: 𝑅𝑜𝑢𝑡 = 𝑟𝑜

𝑉

𝐼

𝑉𝐷𝑆

𝐼𝐷

𝑉𝑒𝑓𝑓

Current Source like

Current Sources


Current Mirrors

• Instead of Applying a constant 𝑉𝐺𝑆 and hence suffer from high sensitivity of the current value to 𝑉𝐺𝑆 variations, current mirrors are used.

• 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 = 𝑉𝑒𝑓𝑓

• 𝑅𝑜𝑢𝑡 = 𝑟02 (∝𝐿

𝐼𝐷)

• To copy current from 𝑀1to 𝑀2:

–𝐼2

𝐼1=

𝑊2

𝑊1

– What about 𝐿1 and 𝐿2???

– When we mirror currents, NEVER CHANGE L !!!

– Changing the transistor length “L”, actually changes the transistor itself.

𝑽𝑮𝑺 = 𝑽𝑻𝑯 + 𝑽𝒆𝒇𝒇

Current Sources


How to improve Rout?

• 𝑅𝑜𝑢𝑡 = 𝑟𝑜 ∝𝐿

𝐼𝐷 To improve 𝑅𝑜𝑢𝑡, we can increase L for

fixed I.

• What if this improvement is not enough? – One common idea is to use “Cascoding”.

• 𝑅𝑜𝑢𝑡 = 𝑟0 1 + 𝑔𝑚𝑅 + 𝑅

• Drawback??

– 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 = 𝑉𝑒𝑓𝑓 + 𝐼𝑅

• Solution: Use MOS transistor instead of resistance R.

Current Sources


Cascode Current Sources

• 𝑅𝑜𝑢𝑡 = 𝑟04 1 + 𝑔𝑚4𝑟02 + 𝑟02

• 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 = 𝑉𝑇𝐻1 + 2𝑉𝑒𝑓𝑓

• Voltage 𝑉𝑥 at drain o

• Too large for many applications. – We need to remove the “𝑉𝑇𝐻1“ term.

𝑉

𝐼𝐷

Bo

th in

SA

T

Bo

th in

Tri

od

e

M2:

SAT

and

M4:

trio

de

𝑉𝑒𝑓𝑓 𝑉𝑇𝐻 + 2𝑉𝑒𝑓𝑓

Where is the current mirror? M1-M2

𝑽𝑮𝑺𝟏 + 𝑽𝑮𝑺𝟑 = 𝑽𝑻𝑯𝟏 + 𝑽𝑻𝑯𝟑 + 𝟐 × 𝑽𝒆𝒇𝒇

𝑽𝑮𝑺𝟏 = 𝑽𝑻𝑯𝟏 + 𝑽𝒆𝒇𝒇

𝑽𝒙 = ?

Current Sources


Minimum Compliance Cascode Current Source (Optimum Swing)

• Original Cascdode: VDrain of M2 = Vsource of M4 = VTH+Veff.

• VTH+Veff is more than needed to keep M2 in SAT. • Remember: M4 absorbs the variations on voltage V. • Let’s reduce it to the minimum requirement: Veff.

• 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 = 2𝑉𝑒𝑓𝑓 : 𝑉𝑒𝑓𝑓 can be designed arbitrary small.

• 𝑅𝑜𝑢𝑡 = 𝑟04 1 + 𝑔𝑚4𝑟02 + 𝑟02

𝑉

𝐼𝐷

Bo

th in

SA

T

Bo

th in

Tri

od

e

2𝑉𝑒𝑓𝑓

Current Sources


Alternate Bias Circuits

• Resistors do not track transistors.

• We need to replace the resistor with a device that tracks the transistor MOSFET in triode region.

• Bottom transistor is always in triode region.

• Upper transistor is always in SAT region.

Current Sources


Important Connection for High-Swing Current Sources

• In this circuit, mirroring is happening between M1 and M2.

– 𝑉𝐷𝑆1 = 𝑉𝑇𝐻 + 𝑉𝑒𝑓𝑓

– 𝑉𝐷𝑆2 = 𝑉𝑒𝑓𝑓

• Channel length modulation (finite output resistance) and VDS mismatch Systematic Mismatch.

• We need to equalize drain to source voltage of both transistors.

𝑽𝒆𝒇𝒇

Current Sources


Important Connection for High-Swing Current Sources

• In this circuit: 𝑉𝐷𝑆1 = 𝑉𝐷𝑆2 – No systematic mismatch

• What about 𝑉𝐺? – For optimum (High-Swing):

𝑉𝐺 = 𝑉𝑇𝐻 + 2𝑉𝑒𝑓𝑓

• In general: Limits of 𝑉𝐺are the values that keep M1 and M3 is Saturation region. – M1 SAT: 𝑉𝐺 > 𝑉𝐺𝑆 𝑀3

+ 𝑉𝑒𝑓𝑓 𝑀1= 𝑉𝑇𝐻 + 2𝑉𝑒𝑓𝑓

– M3 SAT: 𝑉𝐺 < 𝑉𝑇𝐻 + 𝑉𝑒𝑓𝑓 + 𝑉𝑇𝐻 = 2𝑉𝑇𝐻 + 𝑉𝑒𝑓𝑓

– Since 𝑉𝑒𝑓𝑓 < 𝑉𝑇𝐻 (In almost all cases) We

have an intersection between both ranges.


Contents

• MOS Transistor Physics

• Current Sources – Basics

– Cascode Current Sources

– High-Swing Current Sources (optimum biasing)

– Current Mirror Systematic Mismatch

• Random Transistor Mismatch

Matching


Transistor Matching

• Ideally, both transistors in a current mirror are identical.

• In real life, we always have mismatches between any pair of transistors.

• Mismatches can be found in: – Geometry

– 𝜇 and 𝐶𝑜𝑥

– 𝑉𝑇𝐻 (Dominant source of mismatch)

• Let’s focus on the VTH mismatch, we can model it as an input referred mismatch (𝑉𝐺𝑆 mismatch) in the form of 𝑉𝑜𝑠.

- 𝑉𝑜𝑠 =𝐴𝑣𝑡

𝑊𝐿

- 𝐴𝑣𝑡 is a technology given parameter.

Matching


Transistor Matching

• 𝐼 =1

2𝜇𝑛𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝐻

2

• Δ𝐼 = 𝐼1 − 𝐼2 = 𝑔𝑚Δ𝑉𝐺𝑆 =2𝐼

𝑉𝑒𝑓𝑓 Δ𝑉𝐺𝑆

•Δ𝐼

𝐼=

2𝑉𝑜𝑠

𝑉𝑒𝑓𝑓=

2𝐴𝑣𝑡𝑊𝐿

2𝐼

𝜇𝑛𝐶𝑜𝑥𝑊𝐿

∝𝐴𝑣𝑡

𝐿 𝐼

• For a fixed I, normalized current mismatch is inversely proportional to L.

- 𝑉𝑜𝑠 =𝐴𝑣𝑡

𝑊𝐿

- 𝐴𝑣𝑡 is a technology given parameter.


Design Hints

• Requirements: 𝐼𝑜𝑢𝑡, 𝑅𝑜𝑢𝑡, 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 and Δ𝐼

𝐼

– 𝑉𝑐𝑜𝑚𝑝𝑙𝑖𝑎𝑛𝑐𝑒 −→ 𝑊

𝐿 for a specific current 𝐼𝑜𝑢𝑡

– 𝑅𝑜𝑢𝑡 −−−−−→ 𝑔𝑚𝑟𝑜 𝑟𝑜 −→ 𝐿

–Δ𝐼

𝐼−−−−−−−→ L


Assignment 1

• Problem 1: – Build a testbench to identify the approximate values of μnCOX and Vth of

the NMOS and PMOS 1.2v and 3.3V devices. There is no single answer to this problem.

• Problem 2: – For an NMOS3V transistor, Drain and Gate connected to VDD=1.2V and

source connected to a current source (100uA) to ground and Bulk connected to GND. Fix L=Lmin and sweep W from W=L to W=100L: • Sketch Vod versus W/L • Sketch Vth versus W/L (Repeat the same with bulk and source tied to gether

and note the difference) • Sketch gm versus W/L • Sketch ro versus W/L • Sketch gm.ro versus W/L • Repeat for L=2Lmin, L=4Lmin and L=8Lmin • Repeat All of the above for PMOS3V but connect Drain and Gate to VSS, Bulk

connected to VDD=1.2V and Source to a current of 100uA from VDD to Source.


Assignment 1

• Problem 3: – Design a simple MOS current mirror to map 10𝜇𝐴 current from an ideal

reference to the output, with 100mV Compliance voltage and Rout of at least 500kΩ ( measured at Vout = 500mV). Use the minimum possible area. [ Rely on hand calculations more] • Note: When you simulate this current mirror, the output current will be

different than the input current by some amount based on the output voltage you choose. This is expected and called systematic error.

– Let Vout =200mV. What is the systematic error in the current mapping ratio?

• Problem 4: – Design a MOS accurate high swing current mirror with the following specs:

• 𝐼𝑖𝑛 = 𝐼𝑜𝑢𝑡 = 10𝜇𝐴, • 𝑉𝑐𝑜𝑚𝑝 <= 300𝑚𝑉,

• 𝑅𝑜𝑢𝑡 ≥ 2𝑀Ω @ 𝑉𝑜𝑢𝑡 = 500𝑚𝑉

•Δ𝐼𝑜𝑢𝑡

𝐼𝑖𝑛≤ 10% (Assume 𝐴𝑣𝑡 = 20 𝑚𝑉. 𝜇𝑚)

analog integrated circuits lecture 1: mos physics and...

Documents