658 IEEETRANSACTIONSONCIRCUITSANDSYSTEMS-1I :ANALOG AND DIGITALSIGNAL PROCESSING,VOL.3Y,NO.9,SEPTEMBER 1992

Analog FIR Filters with an Oversampled 2-A Modulator

Huang Qiuting and George S. Moschytz

Abs@ct-An FIR filter configuration is presented which uses a Z-A modulator as front-end. The modulator converts an analog input into a high-speed binary sequence, which can he delayed and shifted with a binary shift register. Replacing an analog delay line by a binary shift register reduces the cost of silicon area and power, and improves the immunity of the delay line to interferences. The high-frequency quanti- zation noise introduced by the modulator is removed naturally by the FIR filter to be implemented, so that the analog output is reconstructed accurately at the filter output without requiring additional hardware. Experimental results are presented.

Finite impulse response (FIR) filters are very useful in many applications, especially those where filtering with linear phase is required. FIR filtering is typically implemented using either digital or CCD (charge coupled device) circuits. Following the success of switched-capacitor (SC) recursive filters in the last decade, various circuit techniques have recently been proposed to implement analog FIR filters with switched capacitor circuits. The aim is to reduce the cost and to improve on the signal processing speed of digital FIR filters while still using standard digital IC technology [l]-[4]. Examples of applications in which analog FIR filters are very useful include such widely used telecom circuits as (different types’ of) modems implemented using analog techniques. The majority of l inear-phase bandpass and low-pass filters required in modems are currently imple- mented using IIR amplitude filters plus IIR delay equalizers. Analog FIR filters implemented efficiently in terms of hardware can provide a very useful alternative to the IIR approach. Analog FIR filters are also potential contenders for l inear-phase filters required in speech processing applications such as vocoders, where the alignment of signals in time is essential. As the improvements in fine-line CMOS technologies gradually enable analog filters to handle video frequency applications, in which l inear-phase filtering is essential, analog FIR filters can be expected to compliment the digital approach in many video applications in the near future.

An example of an analog SC FIR filter, which is a straightfor- ward adaptation of the digital FIR filter structure, is shown in Fig. 1 [l]. One of the main problems in implementing analog FIR filters is the fact that many accurate analog delay elements are required. An analog delay element implemented as an SC circuit, such as the one shown in Fig. 2, typically requires an op-amp plus a few switches and capacitors. As the analog signal propagates through the analog delay line, various errors such as clock feedthrough, noise, gain deviation due to capacitance mismatch, power-supply noise coupling and offset are accumu- lated, which degrade the signal. Long delay lines require a large number of op-amps and capacitors which consume a large sili- con area and power. Various offset and finite-amplifier gain

Manuscript received March 2, 1992; revised July 25, 1992. This paper was recommended by Associate Editor M. A. Soderstrand.

H. Qiuting was with the School of Information Systems, University of East Anglia, Norwich, NR4 7TJ, UK. He is now with the Institute of Integrated Systems, Swiss Federal Institute of Technology, Zurich, Switzerland.

G. S. Moschytz is with the Institute for Signal and Information Processing, Federal Institute of Technology, Zurich, Switzerland.

IEEE Log Number 9204464.

compensation schemes [ll] tend to increase the complexity of the analog delay element still further, which makes a designer reluctant to use them.

The analog delay elements can be replaced by a bank of sample-and-hold circuits plus a rotating switch matrix [4]. Although the accumulation of errors does not occur, the bank of sample-and-hold circuits is still expensive in terms of silicon area and power. The rotating switch matrix also adds substantially to the silicon area and circuit complexity.

A different approach, which circumvents the analog delay line problem while still implementing an analog transversal filter is to use an oversamljling technique. In [5], lst-order delta modula- tion was proposed for analog transversal filters without analog delay elements. In the following, we shall present a filter struc- ture that employs an oversampled X-A modulator, a binary shift register and an SC summer to implement low-pass and bandpass type FIR filters.

11 .ANOVERSAMPLEDANALOG FIR FILTER STRUCTURE

Fig. 3 depicts the block diagram of the proposed filter struc- ture [6] for low-pass and bandpass applications in which the stopband attenuation requirement equals or exceeds the filtering required by a X-A modulator for noise suppression. This covers, for example, most telecom applications such as modem filters, which often require a minimum of 50 dB stopband attenuation and 60 dB signal-to-noise ratio. The filter proposed in Fig. 3 consists of a X-A modulator, a binary shift register and a switched-capacitor summer. The one-bit hvo level quantizer of the Z-A modulator converts the input analog signal VI, into a string of binary signals representing either plus or minus one. This binary sequence is then shifted down a shift register of n-bit length, which serves as the n-tap delay line. The IZ input capacitors provide the IZ coefficients of the FIR filter and the resulting output V,,, from the SC summer is the filtered version of the input signal. Because the signal propagates down the delay line in binary form, it has all the advantages of a digital signal, i.e., it does not suffer from the various degrada- tions mentioned above for the analog delay line. Since the signal is converted by the X-A modulator into a one-bit digital signal, each delay element in the delay line is only a D-Flip-Flop, which consists of about a dozen minimum sized MOS transistors. This consumes much less silicon area and static power than the analog delay element shown in Fig. 2, or the 8- to 16-bit shift register per tap required for shifting S- to 16-bit words in a digital FIR filter. Compared to both the pure analog and the multibit digital signals however, the binary representation of the analog input in our structure contains a large amount of quanti- zation noise. In order to analyze the noise performance of the FIR filter structure in Fig. 3, it is helpful to briefly discuss the one-bit A/D converter used in the structure, the X-A modula- tor, and its noise shaping property.

III. NOISESHAPINGWITHTHE Z-A MODULATOR

Referring to the frontLend block in Fig. 3, which represents the Z-A modulator, quantization noise is introduced into -the signal at the comparator, which converts the analog signal into two quantum levels. This quantization noise is generally consid- ered random, uncorrelated to the analog input signal and having a white spectrum. The quantizer itself is frequently modeled as a linear summer of its input and a quantization error Q. Although such a model is very crude for describing the behaviour of the

1057-7130/92$03.00 0 1992 IEEE

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 39, NO. 9, SEPTEMBER 1992

Fig. 1. A conventional analog FIR filter configuration based on SC circuits.

659

OUT

Fig. 2. An analog delay circuit based on SC technique.

l-bit quantizer, it is useful in providing an intuitive understand- ing of the noise shaping property of the 2-A modulator. Refer- ring to Fig. 4, which is the linear model for a 2nd-order X-A modulator, the modulator output V’ is related to the signal input V,N and the quantization error Q by the expression

V’ = VI, + Q(l - z-I)‘. (1)

The quantization error Q is generally considered to be uni- formly distributed between - VR and V,, the reference voltage of the modulator. The total rms noise is then VR/d3 [7], which is very large indeed. According to (11, Q is differentiated twice before it appears as part of V’, the output of the C-A modula- tor. The modulator essentially redistributes the quantization noise energy from low frequencies to high frequencies. A typical spectrum of V’ for a sinusoidal input is shown in Fig. 5. In an oversampling Z-A A/D converter, digital filters are used to remove the high-frequency noise in V’ to obtain high quality analog to digital conversion. If an ideal brick-wall low-pass filter is assumed with a cutoff f requency f;, the in-band noise power is then [8]

‘. (2)

Because the modulator is oversampled, f, e f,, the total in-band noise due to quantization becomes much smaller as a result of the noise shaping and low-pass filtering of the binary sequence by the modulator. If our oversampled analog FIR filter is to achieve a noise performance which is similar to that of a Z-A A/D converter, a similar low-pass filter must be used to remove the .quantization noise introduced by the Z-A modulator.

IV. REMOVALOF THE QUANTIZATIONNOISEINTHE OVERSAMPLED FIR FILTER

In the proposed analog FIR filter, the low-pass filtering needed to remove the high-frequency quantization noise is precisely the jilter we wish to implement forfiltekg the analog input. The low-pass or bandpass FIR filter implemented by the SC summing circuit will therefore perform two tasks. One is to attenuate or remove any

signal component in the input that falls outside the filter’s passband. The other is to remove the quantization noise at high frequencies and to reconstruct the in-band inputs to their analog form. If the front-end C-A modulator performs a l-bit A/D conversion to simplify the delay line and to take advantage of the digital signal’s immunity to interference, the SC summing circuit performs the l-bit digital to high-accuracy analog conver- sion by low-pass filtering. Despite the mixed analog-digital con- struction of the oversampled FIR filter, the signal processing it performs is precision analog. Referring to Fig. 3, the binary signals from the taps only control whether the switches connect- ing the reference voltage and input capacitors of the SC summer are on or off. The accuracy of the charge transfer as a result of the delay-line-controlled switching only depends on the accuracy of the reference voltage and the ratios between the input capaci- tors and the feedback capacitor of the SC summer. If the passband edge of the desired FIR filter is sufficiently low com- pared to the sampling frequency, and if there is sufficient attenuation in the stopband, the quantization noise introduced by the front-end modulator can be made negligible in the filter’s final output. The digital pulses that propagate through the binary shift register are then reconverted into a continuous signal whose amplitude is determined by the input signal and the filter transfer function.

.

The following example further illustrates the operating princi- ples of the C-A-modulator based FIR filter. A 2.56-tap FIR filter, based on the configuration in Fig. 3 and designed using the Kaiser window spectral shaping method, has been simulated using a digital computer. The signal spectra at various parts of the oversampled filter are shown in Fig. 6. Figure 6(a) shows the spectrum of the input applied to the Z-A modulator and thus the input of the FIR filter, which consists of two sine waves at 500 Hz and 31 kHz, respectively. The clock frequency is 1 MHz. The desired filter transfer function, shown in Fig. 6(b) and implemented by the SC summer’s input capacitors, has a cutoff f requency at roughly 9 kHz so that the 500 Hz sine wave is within the filter passband and the 31 kHz sinewave outside the passband. The 2nd-order Z-A modulator converts the continu- ous input into a binary pulse train, adding high frequency noise to the signal. Fig. 6(c) shows the power spectrum of the binary pulse train, which contains the spectral peaks representing the sine waves at 500 Hz and 31 kHz, as well as the quantization noise rising with frequency at 40 dB per decade. This pulse train is shifted down the binary shift register. It then multiples 256 FIR filter coefficients before being added together by the SC summer. The spectrum of the summer output is shown in Fig. 6(d). We see that the high frequency noise is indeed suppressed by the FIR filter such that the peak noise spectral density is below - 80 dB with respect to the reference voltage of the Z-A modulator, and the sine wave at 31 kHz is now reduced by nearly 60 dB. The total integrated noise from dc to half the

660 IEEETRANSACTIONSONCIRCUITSANDSYSTEMS-I I :ANALOGAND DIGITALSIGNALPROCESSING,VOL.39,NO.9,SEPTEMBERl992

Fig. 3. An FIR filter configuration with a 8-A modulator.

Fig. 4. A 2nd-order X-A modulator with the quantizer modeled as a linear summer.

Fig. 5. Measured typical spectrum of the pulse train I/’ produced by the second-order H-A modulator for a sine input at 1 kHz.

sampling frequency is 64 dB below the reference voltage. The time-domain signal corresponding to the spectrum in Fig. 6(d) is shown in Fig. 7, where we see that the oversampled FIR filter duly removed the signals outside the passband. The 500 Hz sinewave output is exactly what we expect a conventional FIR filter to produce for the same input. The addition and removal of the quantization noise are entirely internal to the oversam- pled FIR filter configuration.

V. OVERSAMPLED FIR FILTERWITHSYMMETRICAL

COEFFICIENTS

Most FIR filters have symmetrical coefficients, which ensure a linear phase response. This means that the pairs of identical coefficients should share the hardware implementation by adding the two signals before multiplying the tap coefficient they share. In a conventional analog FIR filter such as the one shown in Fig. 1, such hardware sharing can only be done by multiplexing the

SC summer’s input capacitor between the two tap locations sharing the same tap weight. This multiplexing in time incurs a penalty in speed. In our oversampled FIR filter configuration, sharing the coefficients can be easily achieved because the signals from the delay line are binary. The addition of two binary signals has only three possible outputs: 2, 0, or -2. This corre- sponds to twice the charge transfer, no charge transfer, or minus twice the charge transfer from the reference voltage source via the weight capacitor to the SC summer’s feedback capacitor. The same charge transfers can be accomplished by the new FIR filter configuration shown in Fig. 8, where each pair of binary signals sharing a coefficient are combined with an AND and a NOR gate to produce a new pair of switch control signals. Only one input capacitor is now needed for each pair of tap locations, so that the number of input capacitors is halved compared to Fig. 3. When the two tap signals are both digital one, a positive charge transfer takes place from the reference voltage source to the SC summer via the switch controlled by the output of the AND gate. When both signals are digital zeros, a negative charge transfer takes place via the switch controlled by the output of the NOR gate. The value of the reference voltage is doubled in the configuration in Fig. 8, so that the amount of transferred charge is also doubled. When the two digital signals are differ- ent, neither the AND gate nor the NOR gate output is high, both switches they control are off, so that no charge transfer takes place.

Reducing the number of input capacitors not only results in a substantial reduction in the total capacitor area, which now dominates the cost of total silicon area, but also reduces the total capacitive loading to the op-amp for the SC summing circuit.. This, in turn, improves the achievable speed of the summing circuit and the power consumption of the op-amp.

VI. DISCUSSION

The price that the new structure pays for the advantage in silicon area is the requirement for a higher clock rate. Equation (2) indicates that in order to achieve more than 70 dB of signal-to-noise ratio, an oversampling ratio of the order of 50 is require’d in the ideal case. With practical filters, the removal of high frequency noise will be less thorough than with an ideal brick-wall filter, so that the required oversampling ratio will be even higher. On the other hand, state of the art C-A modula- tors implemented in l-pm CMOS technologies operate at up to 50 MHz’ clock frequency [9]. Oversampled FIR filters imple-

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 39, NO. 9, SEPTEMBER 1992 661

-250’ I I III IO’ 104 107

frequency (Hz) (a)

-150' I ' """i ' " '11111 t '14"111 I olitud 102 103 104 105 106

frequency (Hz) (b)

104 frequency (Hz) (4

10’ 104 107

f requency (Hz) CC)

Fig. 6. Simulated results of a 256-tap oversampled FIR filter. (a) Spectrum of the filter input. (b) Amplitude response of the 256~tap low-pass filter based on Kaiser window. (c) Spectrum of the modulator output sequence. (d) Spectrum of the FIR filter output.

-0.6- 0 I 2

- ,“, ,” 1. 3 4 5 6 7

t ime (seconds) x10-”

Fig. 7. Waveform of the oversampled FIR filter output.

mented in standard CMOS technologies can therefore readily handle signal frequencies up to 500 kHz, which is not far from the lower end of video frequencies. As the minimum line width of CMOS processes further decreases, analog FIR filters can be expected to process video signals.

Similar in complexity to a biquadratic filter, the overhead of a 2nd-order 8-A modulator is low even for short FIR filters. The silicon area is now primarily consumed by capacitors forming the filter coefficients in the proposed FIR filter. In order for the filter to have 0-dB dc gain, the sum of the coefficients equals unity. This means that the maximum coefficient value is inversely related to the filter length M. For a 256-tap filter based on the Kaiser window, the maximum coefficient is 0.01 and the spread of the coefficients is less than 100 (65 in our example). The

feedback capacitor for the SC summer must therefore be 10 000 times larger than the smallest input capacitor. This can be reduced by up to a factor of 20 by reducing both the gain of the X-A modulator and the reference voltage at the input of the SC summer with respect to that of the Z-A modulator. Assuming a minimum capacitance of 0.5 pF, the total capacitance for the SC summer is less than 400 pF. For an average double-poly 2-pm CMOS process; the silicon area it takes is less than 1 mm’. An estimate of the total chip area of the complete FIR filter is 4 mm2. This is an order of magnitude lower than a digital FIR filter of comparable length [lo]. The power dissipated by the SC summer can be estimated by that of a 400 pF capacitor for a 2-V signal swing at 1 MHz, which is less than 2 mW. The power consumption of a 256-tap delay line is also less than 2 mW. An SC-based FIR filter therefore consumes less than a fifth of the power consumed by its digital counterpart at 1 MHz [lo]. The above estimates reinforce the earlier statement .that an analog FIR filter consumes much less silicon area and power than its digital counterpart. It is therefore a very useful alternative to compliment the digital approach. Methods to reduce the effect of limited matching accuracy (corresponding to lo-bit coefficient length) of switched capacitor coefficients on the filter perfor- mance are currently under investigation.

VII. EXPERIMENTAL RESULTS

To verity the general ideas described in this paper, a small FIR low-pass filter was built using off-the-shelf devices, such as LF356 op-amps and CMOS switches. Due to the complexity associated with the use of discrete switches and digital gates, the length of the experimental filter was limited to 32-taps. This was implemented as the configuration in Fig. 8, using 16 input capacitors for the SC summer. The value of each input capacitor is made up of up to four off-the-shelf capacitors, which is close

662 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 39, NO. 9, SEPTEMBER 1992

r shift register

Fig. 8. FIR filter structure for symmetrical coefficients.

to within 5% of the design value. The small filter length does not provide sufficient noise attenuation in the stopband. The design of the FIR filter was therefore based on the Kaiser window method to obtain as much stopband attenuation as possible. The cutoff f requency of the filter is about 2 kHz and the sampling frequency is 50 kHz. Fig. 9 shows the measured amplitude and phase transfer functions of the filter. The measured amplitude transfer function, shown in Fig. 9(a), is very close to the design up to the third sidelobe in the stopband. The deviation from ideal above the third sidelobe is partially due to the inaccuracies of the capacitors, and partially due to the high level of quantiza- tion noise compared to the test signal. The oversampling ratio, limited by the speed of the general-purpose op-amps, is only 12.5, which means that the quantization noise is already quite high at a few kilohertz. Although the quantization noise is suppressed by the filter’s stopband attenuation, so is the level of the test signal. This makes the measurement above the third sidelobe appear quite noisy. As both the signal and the noise need to be attenuated at high frequencies, the low signal-to-noise ratio in the stopband does not necessarily mean poor perfor- inance, provided that both are sufficiently attenuated. In a monolithic implementation, the higher sampling rate afforded by faster op-amps would enable better measurement for more sidelobes. The measurement for the filter’s phase response is shown in Fig. 9(b). The linear phase of the symmetrical FIR filter can be clearly seen. Again, the measurement looks noisy at higher frequencies due to insufficient oversampling.

To get an idea of the quantization noise in the output of the short experimental filter, the power spectrum of the FIR filter output is shown in Fig. 10. The input to the filter is a sinewave at 610 Hz. It can be seen that the quantization noise rises at 12 dB/ octave roughly below the 2-kHz cutoff f requency of the filter. Above 2 kHz, the noise spectral density stops rising because of the attenuation of the filter. The short filter length provides only 30 dB attenuation in the stopband, however, SO

that the noise density stays constant at -60 dB rather than falling rapidly as it would for longer filters, such as the 256-tap filter shown in Fig. 6. A higher clock rate for the integrated circuit version of the filter would also reduce the noise density within the filter passband. Despite the limited filter length, the basic idea of the oversampled FIR filter structure is verified by the simple experiments.

(a)

(b)

Fig. 9. (a) Measured amplitude response of a 32-tap oversampled FIR filter-based on Kaiser-window (vert. scale: lOdB/div hor. scale: 1,25kHz/div). (b) Measured phase response of a 32-tap oversampled FIR filter-based on Kaiser-window (vert. scale: 45”/div hor. scale: 200 Hz/div).

VIII. CONCLUSIONS A long line of analog delay elements accumulates noise,

offset, supply-coupled noise, clock feedthrough, and consumes large area and power. It can be replaced by a simple binary shift register if the analog input is first coded by a S-A modulator into a binary sequence. Doing so saves silicon area, reduces circuit complexity and makes the signal immune to delay ele- ment imperfections. The high-frequency quantization noise pro- duced by the S-A ‘modulator is removed by the low-pass or

Fig. 10. Measured power spectrum of the FIR filter output for a sine input at 610 Hz.

bandpass FIR filter being implemented. The price paid for these advantages is that the clock rate in the proposed oversampled FIR structure is about a factor of five times higher than conven- tional SC circuits for similar signal bandwidths.

REFERENCES 111 T. Enomoto et al. “integrated tapped MOS analogue delay line

using switched capacitor technique,” Electron. Lett., vol. 18, pp. 193-194, Mar. 1982.

121 S. K. Sunter et al. “A programmable transversal filter for voice frequency applications,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 367-372, Aug. 1981.

131 K. Matsui et al. “CMOS video filters using switched capacitor 14-MHz circuits,“ IEEE J. Solid-State Circuits, vol. SC-20, pp. 1096-1102, Dec. 1985.

[41 Y. S. Lee and K. Martin, “A switched-capacitor realization of multiple FIR filters on a single chip,” IEEE J. Solid-State Circuits, vol. 23, pp. 536-542, Apr. 1988.

[51 N. S. .Reddy and M. N. S. Swamy, “Switched capacitor realization of FIR filters,” Proc. ISCAS, pp. 69-72, 1984.

161 H. Qiuting and G. Moschvtz, “Analog FIR filters using the Z-A ovcrsampfing technique,” hoc. ISCAf1991, pp. 280-2g3.

171 A. Gersho, ‘!Principles of quantization,” IEEE Trans. Circuits Syst., vol. CAS-25, July 1978.

181 J. Candy, “A usi of double integration in sigma-delta modulation,” IEEE Trans. Comm. vol. COM-33, DD. 249-258, Mar. 1985.

191 B. P. Brandt and B. A. Wooley, “A 50-MHZ multibit sigma-delta modulator for 12-b ~-MHZ A/D conversion,” IEEE J. Solid-State Circuits, vol. 26, pp. 1746-1756, Dec. 1991.

ml Y. Matsuya et at!. “A 16-bit oversampling A-to-D conversion tech- noloav using triple-integration noise shaoina.” IEEE J. Solid-State Circ&, vor SC:22, Deg. 1987.

. -.

1111 A. Dabrowski, U. Menzi, and G. S. Moschytz, “Offset-compensated switched-capacitor delay circuit that is insensitive to stray capaci- tance and to capacitor mismatch,” Electron. Lett., May 1989, vol. 25, pp. 623-625.

Grouping Variables into Multiport Memories for Data Path Synthesis

Imtiaz Ahmad and C. Y. Roger Chen

Abstract-Recently there is a trend for the designer to group registers into register files for efficiently implementing large VLSI chips. Multi- port memories provide an effective way for such an implementation and are actually being used in the design of many recent high-speed RISC

Manuscript received April 9,1992; revised August 25,1992. This paper was recommended by Associate Editor I. Shirakawa.

The authors are with the Department of Electrical and Computer Engineering, Syracuse University, Syracuse, NY 13244-1240.

IEEE Log Number 9204233.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II : ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 39, NO. 9, SEPTEMBER 1992 663

and SuperScalar processors. An efficient design methodology for group- ing variables into multiport memories is presented, which is an essential step for multiport memories based data path synthesis. The proposed technique not only groups variables into a minimum number of multi- port memory modules, but also simultaneousIy minimizes the number of registers in each memory module. The minimization problem has been formulated as a O-l integer linear programming problem. Experiments on benchmarks show very promising results.

I. INTRODUCTION

Grouping variables into multiport memories is an essential step for multiport memories-based data path synthesis. In designing large/complicated VLSI chips, there has recently been a trend for the designer to group registers into register files for an efficient implementation. Multiport memories provide an effective way for such an implementation. Multiport memories have the advantages of enhancing the system performance and reducing the part count by providing simultaneous access to data by more than one functional unit at a time. Recent high-speed computers [l]-[3] are taking advantage of multiple ports of such memories to achieve high system throughput. For example, a 6-ported register file forms one of the core elements of the Intel’s i96OCA SuperScalar processor architecture [2]. Three ports are provided for use by register-to-register function units and the other three by the memory-access function units, allow- ing simultaneous executions of register and memory operations.

A multiport memory-based design will be more structured, modular and dense, and require less chip area because of its regular layout structure as compared to random logic [4]. Due to a smaller number of parts, the generated design can be tested more easily. The demand for the application specific integrated circuits with faster multiport register files [.5] is also becoming apparent. Multiport RAM compilers have been developed [6], [7] for data path synthesis to generate fast compact multiport RAM%. Commercial vendors are currently supplying multiport register files as a part of standard libraries [8]. The availability of high-density and high-speed multiport memories, and all of the above advantages, motivate the use of multiport memories in data path synthesis.

Few approaches have been reported to group variables into multiple memories. Balakrishnan et al. [9] and Sutarwala et al. [lo] have reported a technique to group a maximal number of registers to only one multiport memory at a time. The left-over registers are either synthesized as isolated registers or grouped. into multiport memories by repeatedly applying the same algo- rithm. It is clear that their approach does not result in a minimum number of memory modules. Wilson et al. [ll] have presented an integer linear programming based technique to find a feasible solution and a heuristic in which registers are allocated to available multiport memories one-by-one, which is not an optimal solution.

C. H. Chen et al. [12] have reported a O-l matrix partitioning technique to group registers into multiport memories assuming that multiport memories have an identical type of ports. Recently, C. H. Chen [13] has extended the matrix partitioning technique to allow mixed type of ports but it does not generate optimal results. MAP [14] groups variables into a minimum number of memory modules, but does not consider the minimization of registers in each memory module. All of the above approaches either do not result in a minimum number of memory modules or they do not consider the minimization of registers in each memory module while grouping variables into memories, which

1057-7130/92$03.00 0 1992 IEEE