analog controller

8/4/2019 Analog Controller

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A Simple Analog Controller for Single-Phase Half-Bridge Rectifier and its

Application to Transformerless UPS

Rajesh Ghosh G. Narayanan

Power Electronics Group, Department of Electrical Engineering,

Indian Institute of Science, [email protected] [email protected]

Abstract A simple, low-cost, constant frequency, analogcontroller is proposed for the front-end half-bridge

rectifier of a single-phase transformerless UPS system to

maintain near unity power factor at the input and zero

dc-offset voltage at the output. The controller generates

the required gating pulses by comparing the input

current with a periodic, bipolar, linear carrier withoutsensing the input voltage. Two voltage controllers and a

single integrator with reset are used to generate the

required carrier. All the necessary control operations

can be performed without using any PLL, multiplier

and/or divider. The controller can be fabricated as a

single integrated circuit. The control concept is validated

through simulation and also experimentally on an 800W

half-bridge rectifier. Experimental results are presented

for ac-dc application, and also for ac-dc-ac UPS

application with both sinusoidal and nonlinear loads.

The simulation and experimental results agree well.

I. INTRODUCTION

Single-phase UPS systems are widely used in low powerapplications like data storage, computer systems, medicalfacilities and telecommunications. In many cases the inputside is a diode bridge rectifier, which draws non-linearcurrent from the source. To meet the necessary harmonicstandards, various topologies such as half-bridge and full-

bridge with power factor correction feature have beenreported for the front-end-converter [1]. Compared to full-bridge topology, half-bridge topology offers advantages like

simpler power conversion circuit, fewest switching devicecount, no need for isolation transformer, common groundconnected to input and output etc [2].

A single-phase transformerless UPS system is shown inFig. 1. It has a half-bridge front-end-converter (FEC), toconvert the input unregulated ac to regulated dc, and a half-bridge inverter to convert the dc back to regulated ac powerto feed the load. Both the FEC and the inverter share acommon dc bus. The system has a common input-output

neutral, connected to the mid point of the dc bus.The FEC is required (i) to draw sinusoidal input current

at near unity power factor, and (ii) to maintain equal voltageacross each half of the dc bus. The latter is required to

prevent any dc voltage offset at the output of the UPS. Anumber of controllers have been proposed for the half-

bridge rectifier to achieve the above objectives [1-3].

Input Output

AC-DC DC-AC Filter

L C1

C2

N N

S1

S2

S3

S4

+

+

_

_

Battery

Fig. 1 Single-phase UPS system

These require input synchronization (PLL), DQtransformation [3], and multiplier and divider circuit along

with input voltage sensing [1-3]. These increase both

controller cost and complexity. As the single-phaseconverters are used for low power applications, a low-costcontroller solution is desirable.

Current mode control techniques using modulatorapproach have been reported in [4-7]. The required

switching instants are determined by comparing the inputcurrent/switch current with a suitably generated carrier in

the modulator without using any input PLL, multiplier,divider and input voltage sensor.

The purpose of this paper is to propose a simple, constantswitching frequency based controller for the single-phase

transformerless UPS application that has the simplicity ofthe controllers reported in [4-7] and the performance of the

control techniques reported in [1-3].

II. CONTROL SCHEME

A. Half-bridge rectifier

A half-bridge rectifier system is shown in Fig. 2. In each

switching cycle Ts the converter switches S1 and S2 areturned on and turned off by complementary gating pulses.S2 is turned on for a duration ofDTs and S1 for (1-D)Ts,whereD is the duty ratio. With S2on and S1 off, the voltageapplied across inductorL is (Vg+Vo2). Again, with S1 on andS2 off, the same is (vg-Vo1). The switching frequency (fsw =

1/Ts) is assumed to be high. The duty ratio D is given by thevolt-second balance across the inductor as shown in (1).

13060-7803-9033-4/05/$20.00 2005 IEEE.
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LC 1

C 2

N

S1

S2

+

+

_

_

V o1

V o2

+

_vg

R

R

ig V dc

Io

Ic 1V p

Fig. 2 Single-phase half-bridge rectifier

vg= Vo1 D (Vo1 + Vo2) (1)

One control objective is to modulate the converter switchduty ratioD such that the input current ig is proportional to

the input voltage vg as per (2), where Re is the emulatedresistance of the converter.

ig= vg/Re (2)

In [4 -6], Re is controlled using Vmas shown in (3), whereVmis the output of the PI voltage controller, Rsis the gain inthe current sensing path and Vdcis the dc output voltage.

Vm = (Vdc.Rs)/Re (3)

Since a half-bridge converter has a split dc bus, both the

output voltages Vo1 and Vo2must be controlled. These twomust also be equal in the steady state. A single voltagecontroller for the entire dc bus voltage (Vdc= Vo1+Vo2), withan additional voltage balancing circuit has been reported in

[2]. Instead of such a scheme, this work proposes a PIcontroller each for controlling Vo1and Vo2 as shown in Fig.

3. The outputs of the two controllersPI1 andPI2 are Vm1andVm2 , respectively . The two outputs Vm1and Vm2 are used tocontrol the emulated resistance,Re, of the whole converter.

+_ +_

+_ ++

RClock

Vdc*

1/2 Vo1

Vm1

Vm2

Vo2PI2

PI1

Reset

Integrator

Vc

S2

S1

D

(1-D)

+_igRs

Vc

Comparator

Fig. 3 Proposed controller

These are related to Re and also to their respective outputvoltages as shown in (4) and (5).

Vm1 = (Vo1.Rs)/Re (4)

Vm2 = (Vo2.Rs)/Re (5)

Using (1), (2), (4) and (5) the control equation (6) for theproposed controller is obtained. Note that the left hand side

of (6) is the output of the input current sensor with gainRs.

ig.Rs = Vm1 -D(Vm1+ Vm2) (6)

B. Carrier

For determination of the duty ratio D, in any switchinginterval Ts, consider a carriervc (t) as defined in (7).

Vc(t) = Vm1 - (Vm1+ Vm2)t/Ts ; (0 < t< Ts) (7)

In the beginning of the interval, i.e. at t = 0, vc (t) isequal to (Vm1). It is (-Vm2) at the end of the interval t =Ts.Observe that the carriervc(t) equals igRs at the instant t=DTs

as in (6). Thus the switching instants can be determined bycomparing the input current igRs with vc(t) in an analog

comparator as shown Fig. 3.Because of high switching frequency, in any switching

interval Ts, Vm1, Vm2 and ig can be considered constant. Ineach switching interval the carriervc(t) can be generated bythe analog integration as shown in (8).

+=

t

s

mmmc dt

T

VVVtV

0

211 .1

)()( ; (0 < t< Ts) (8)

C. Generation of gating pulses

A single analog integrator, with reset, generates thecarrier (8) in each switching cycle Ts. The integrator is reset

by the rising edge of the clock as shown in Fig. 3. Equation(6) is solved in an analog comparator forD, whose output

directly drives the switch S2. The complementary pulsesdrive S1. Gating pulses generated by the controller are

shown in Fig. 4.

ClockigRs

Vc

Gate pulse forS2

Fig. 4 Experimental gating pulses ofS2

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m1V

m2-V

''m1V

g si R

2S

1S

''2S

''1S

cV

''cV

ST

0

Fig. 5 Voltage balancing

D. Balancing the output voltagesVo1 and Vo2

Referring to Fig. 5, consider Vc is the required carrier

when Vo1 =Vo2, and Vm1 = Vm2. The corresponding switchinginstants forS1 and S2 are determined by the intersection ofVc with igRs. It should be noted that the positive and thenegative peaks ofVc are (Vm1) and (-Vm2)respectively, as per(7). Now if Vo1 tends to become less than the desiredreference level, while Vo2 is equal to the reference, the

voltage controller, controlling Vo1 will ensure (Vm1= )

>Vm2 (Fig. 6). Now is the modified carrier; and

are the modified gating pulses for S2 and S1 respectively.

Note that S2 is turned on for longer duration. This results intransfer of excess energy, stored in C2, to C1 to balance bothVo1 and Vo2. Similar explanation may be given for otherpossible cases of voltage unbalance.

''1mV

''cV

''2S

''1S

III. SELECTION OFL AND C

A. Input side inductor L

At steady state Vo1=Vo2=Vo. The expression forD is as

shown in (9), where vg=Vgmsin(t) and Mg=Vgm /Vo.

( )

= =

1 11- 1- sin

2 2

g

go

vD M

Vt

(9)

The peak-to-peak ripple in the inductor current ig, in a

switching interval Ts, is given in (10).

+ = =

2

2

g o g sg s o

o

v V v Ti DT V

L V L (10)

It has a maximum value ofig max when vg equals zero, asshown in (11).

=max 2

o sg

V Ti

L (11)

The inductor value L (Henry) is determined using the

highest permissible igmax

as shown in (12), whereIm

is thepeak input current, fsw is the switching frequency (Hz) andPo is the output power.

-15

-10

-5

0

5

10

15

0 60 120 180 240 300 360

g= 0.636

1 2 = 1800-1

Vg

C1

Fig. 6. Variation of capacitor currentIC1

= =

2

max max

2 4

o go s

g g

m o sw m m

V MV TL

i

I P fI I

i (12)

B. DC bus capacitors C1 and C2

Here switching frequency current ripples are neglectedand capacitors are designed for low frequency currents.Referring to Fig. 2, the expression for low frequencycomponent of capacitor currentIc1 is given in (13).

= =

12

(1- ) - sin( ) - cos(2 )C g o og

I D i I I t M

t (13)

Assuming unity power factor operation, the variation of

ic1 over a fundamental cycle is shown in Fig. 6. The zerocrossing instants ofIc1, namely 1 and 2, are given in (14).

= +

2-1 01 2

1sin ( (1 2 ) -1) ; =(180 - )

2g

g

MM

1 (14)

The peak-peak voltage ripple in Vo can be obtained by (15).

= 2

1

11

1o cV I

Cd t (15)

With this, an expression forC1 can be obtained as given in

(16), wherefis the fundamental frequency in Hz.

= +

1 1

2

4cos( ) sin(2 )

4 ( / )

o

go o o

PC

MV f V V 1 (16)

Considering the operating range to be (0.6 < Mg< 0.9),the above expression can be approximated as shown in (17).

= =

1 2 2

0.876 (1 - 0.636 )

( / )

o g

o o o

P MC C

V f V V (17)

IV. SMALL SIGNAL AC MODELS

Small signal ac models are required to design the voltage

controllers. It is assumed that the switching frequency isvery high. In this section the switching cycle average

models of the converter and the controller are described.

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(1-D)2VO1/

1

L

L

R

ST+ 1 C

R

ST+

O1Vd

d

(1 )(1 )

P

L C

G

ST ST + +

O1V

Inverter+

-1/

1

L

L

R

ST+

(1-D)

D

1 C

R

ST++

+

Vo1

Vo2

VdcIg

Vo1 Vo2

VP

D

Vg

1 C

R

ST+(a)

(b) (c)

-

Fig. 7 Small signal ac model of the converter

A. Small signal model of the converter

The switching cycle average model of the converter isshown in Fig. 7(a). This has been derived from Fig. 2. RL isthe inductor resistance and R is the equivalent loadresistance across each half of the dc bus. TL =L/RL and TC =RCare the time constants, where C= C1 = C2. The inverter

has three inputs Vo1, Vo2 andD. The output of the inverter isthe pole voltage VP. Considering Vo1 =Vo2 = Vo the averagepole voltage VPover a switching cycle is shown in (18).

VP= (1 2D) VO = (D, Vo) (18)

Assuming Vo to be a constant voltage the small signal

relationship between VPandD is shown in (19).

( 2 ).OPv V= d (19)

In order to design the voltage controllers it is required tohave a transfer function relating the output voltages Vo1, Vo2to the duty ratioD. In Fig. 7(a) it is shown that there are two

identical paths forVo1 and Vo2. For designing the parameterof the voltage controller it is sufficient to consider any oneof them. The small signal transfer function between Vo1 andD is shown in (20).

1

0

0(1 )(1 )

2 (1 )

o

g

o P

L C

P

L

I

V

V G

ST ST d

Vo D RG

R

=

==

+ +

=

(20)

The derivation of the above transfer function is shown inFigs. 7(a) 7(c).

B. Small signal model of the modulator

Referring to Fig. 8(a) it can be seen that the proposed

controller has a modulator that determines the required dutyratioD. The modulator has three inputs Vm1, Vm2 andIg. The

converter duty ratio D is the output of the modulator.

Equation (6) is used to relate the output D with the inputs asshown in (21).

Vg

Converter

Modulator

D

Vo1Vo2

Vm2

Vm1

IgVo

*

+-

+

-

1mV

2mV

gi

dX1

X2

X3

+-

-

(a) (b)

PI1

PI2

Fig. 8 Small signal model of the modulator

1

1 2( )

m g S

m m

V i RD

V V

=

+(21)

Equation (21) is nonlinear. The small signal model of theabove equation is shown in (22). The linearised modulator isshown in Fig. 8(b).

1 1 2 2 3

2 1

1 22

1 2 1 2

3

1 2

. . .

;( ) ( )

( )

m m g

m g S m g S

m m m m

S

m m

d X V X V X i

V I R V I RX X

V V V V

RX

V V

=

+ = =

+ +

=+

2(22)

C. Voltage loop

Equations (2), (4), (5), (20) and (22) yield the small-

signal transfer function relating Vm1 to Vo1 as shown in

(23a), where Vgm is the peak of the input voltage VgandPo isthe output power. The dc gain H1 is a function of mg asshown in (23b).

2

1 1

1

2 2

1

0

0

( )( ) (23a)

(1 )(1 )( )

.(1 ) ; (23b)8

m

o

m L C

g

gm g g

L S O o

g

VHV S

H SST ST V S

VRH V m m

R R P V

i

=

=

= =+ +

= + =

Over a fundamental cycle mg varies sinusoidally as

shown in (24), where is the supply angular frequency and is the fundamental angle.

mg= (Vgm/Vo).sin( t) = (Vgm/Vo).sin() (24)

The Bode plot ofH(S) (equation (23)) is shown for

different values of in Fig. 9. The parameters are given inTable-I. The two time constants TL and TC are found to be

0.05s and 0.27s, respectively. These are independent of .Hence, the phase plots are identical as seen from Fig. 9.

It can be concluded that over a fundamental cycle the dcgain H1 of the transfer function H(S) (equation (23)) varies

with while maintaining a constant phase. The equivalent

voltage loop is shown in Fig. 10. The voltage controllers canbe designed as given in [6].

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= 900, 1350,1800, 2250,2700

Fig. 9 Bode plot of transfer functionH(s)

Vo*

+-

Vo1

G(s)Vo1

Voltagecontroller

H(s)

Fig. 10 Equivalent voltage loop

D. Current loop

The converter does not have any current loop. It has amodulator, which determines the switching instants for theconverter switches. In this section it is shown that instead ofa physical current loop the modulator can be analyzed to be

an equivalent current loop. This may be required to evaluate

the bandwidth of the current loop. The current loop isderived from Figs. 7 and 8 as shown in Fig. 11(a). Thesimplified current loop is shown in Fig. 11(b). The outputsof both voltage controllers Vm1 and Vm2, set the referencecurrentIg

*for the equivalent current loop. The gain X3 may

be considered to be an equivalent proportional controller.Equations (4) and (5) can be used to simplify (22) as shown

in (25), where Vo1 =Vo2 =Vo. It is shown that at steady stateX3 is a constant.

3

1 2

.

( ) 2

s e e

o o s

R R RX

V V R V = =

+ o(25)

The closed loop transfer function of the equivalentcurrent loop is shown in (26).

1mV

2mV

gidX1

X2

X3

+-

- 2VO1/

1

L

L

R

ST+

1mV

2mV

*

gIX1/X3

X2/X3

+-

-+

gi

X3

gi(2 / )

1

o L

L

V R

ST+

Equivalent current

controller

(a)

(b)

Fig. 11 Equivalent current loop

* (1 )

1;

1 /

g CUR

CURg

eCUR CUR L

L e

I G

STI

RG T T

R R

=+

= =

+ LR

(26)

The bandwidth of the equivalent current loop FBW (Hz)can be obtained by (27). The full load bandwidth of theequivalent current loop is found to be 245 Hz. Bandwidth

increases as the load reduces.

1

2BW

CUR

FT

= (27)

V. EXPERIMENTAL RESULTS

The proposed control concept has been verified through

simulation using MATLAB/SIMULINK and alsoexperimentally on an 800W laboratory prototype. Theexperimental set up is shown in Fig. 12. The arrangementfor sensing the output voltages Vo1, Vo2 and the input currentigare also shown. All measurements are made with respectto the mid-point of the dc bus. Hence no electrical isolationis required. The system parameters are given in Table-I. Theswitching frequency is set at 10kHz. The current transducergain is set at 100mV/A. The converter is tested for twoapplications, namely (A) ac-dc rectification and (B) UPS

application.

Input Output

LC1

C2

N N

S1

S2

S3

S4

+

+

_

_

-igRs

ig

Vo1-Vo2

Rs

R1

R2

R1

R2

G1

G2

-igRs

+

-R3

R5

R6

op1

+

-

R4

R3

R5

R6

op1

Vo1

+

--Vo2

Vo*+

-

+

-

+

-

+

-

+

-

Clock

G2

G1

Comparator

R6

R6

R6

R6

R6

R6 R6

R6

R6

R6

R7

Power circuit

Control circuit

R4

T

C3

C4 C5

C3

C4

Fig. 12 Experimental setup

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Vo1

Vo2

0V level

(b)

Vg

ig

50Hz (a)

Fig. 13. AC-DC application. (a) Input voltage and inputcurrent. (b) Output voltages Vo1 and Vo2.

A. Ac-dc rectification

The test circuit under consideration is same as shown in

Fig. 2 except that a single load resistor of 250 is connectedacross the entire dc bus. The experimental resultscorresponding to 775W output power is shown in Fig. 13.

B. Ac-dc-ac UPS application

The test circuit is same as Fig. 1 except that the battery

interface is not connected. The inverter is operated withsine-triangle PWM (not shown here). Two test conditionsare considered:

(i) Sinusoidal load

An inductive load (R = 25 and L = 10mH) is connected

Voinv

ioinv

50Hz.

(a)

Fig. 14(a) voltage and current across load

Vo1

Vo2

(b)

0V level

Fig. 14 (b) dc bus voltages Vo1 and Vo2

Vg

ig

50Hz(c)

Fig. 14 (c) input voltage and input current

at the UPS output. Output power = 500W, Vg= 110V(rms),Vo1 = Vo2 = 220V, switching frequency 10kHz and inverter

output frequency = 50Hz. Fig. 14 shows the correspondingexperimental results.

(ii) Nonlinear load

A diode bridge rectifier load in series with a 10mHinductor is connected across UPS output. Output power is700W, Vg = 110V(rms), Vo1 = Vo2 = 220V, switching

frequency 10kHz and inverter output frequency = 60Hz.The corresponding results are shown in Fig. 15. Thedifference between the input (mains) frequency and theinverter output frequency causes distortion in Vo1 and Vo2.The non-sinusoidal current drawn by the rectifier load

further adds up to this distortion.

Voinv

ioinv

60Hz.

(a)

Fig. 15(a) voltage and current across load

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Vo1

Vo2

0V level

(b)

Fig. 15 (b) dc bus voltages Vo1 and Vo2

Vg

ig

50Hz

(c)

Fig. 15 (c) input voltage and input current

VI. CONCLUSION

A single-phase transformerless UPS requires connectingthe input and output side neutrals to the mid point of thesplit dc bus. The front-end half-bridge PWM rectifier needsto maintain near unity power factor at the input, holdingequal voltage across each half of the dc bus. The latter is

required to prevent dc voltage offset in the UPS output. Asimple, low-cost, constant frequency analog controller isproposed for the half-bridge PWM rectifier. The proposedcontroller is suitable for operation under continuousconduction mode (CCM). It has two voltage controllers forthe two halves of the dc bus. Instead of a current controller

it has a modulator that provides the necessary gating pulsesto the devices of the half-bridge rectifier. The switchinginstants are determined by comparing the source currentwith a suitably generated periodic, linear carrier. Allnecessary control operations can be performed withoutsensing the input voltage and without using any

multiplication or division operation. The proposed controllercan be fabricated into a single integrated circuit. A designprocedure for selecting the converter parameters L and Cisgiven. The averaged small signal ac models are presented todesign the voltage controller and also to find out the bandwidth of the equivalent current loop. The control

concept is validated through simulation and experiments.

The experimental results are presented.

REFERENCES

[1] Takeshi U, et. Ai., A Study of the High Performance Single-

phase UPS, IEEE PESC, 1998, Vol. 2, pp. 1872-1878.

[2] Gui-Jia Su, and Tetuhiko Ohno, A New Topology for SinglePhase UPS Systems, IEEE Power Conversion Conference,

Aug. 1997, Vol. 2, pp. 913-918

[3] Joan Salaet, et. Al., SVM Based Control of a Single-Phase

Half-Bridge Rectifier Under Power Factor Correction andBalanced Operation, IEEE ISIE 2000, Vol. 1, pp. 130-134.

[4] Maksimovic. D, Jang. Y, R. Erickson, Nonlinear-Carrier

Control for High-Power-Factor Boost Rectifiers, IEEETrans. on power Electronics, Vol. 11, No. 4, July 1996.

[5] S. Chattopadhyay, V. Ramanarayanan and V. Jayashankar, Predictive switching modulator for current mode control of

high power factor boost rectifier, IEEE Trans. On PowerElectron. Vol. 18. No. 1, pp. 114-123, January 2003.

[6] Robert W. Erickson, Fundamentals of Power Electronics,first edition, Chapman and Hall, New York, May 1997.

[7] S. Chattopadhyay, V. Ramanarayanan, A Single-Reset-

Integrator-Based Implementation of Line-Current-ShapingController for High-Power-Factor Operation of Flyback

Rectifier, IEEE Trans. On Industry Applications, Vol. 38,Issue. 2, March-April 2002, pp. 490-499.

Table-I

PARAMETERS AND COMPONENTS OF THE SYSTEM

Po(W)

Vgm(V)

Vo(V)

(Rad/s)

L(mH)

RL

C1, C2F

800 156 220 2**50 10 0.2 2200

S1, S2, S3, S4

IRGT 100 25M12 (25A, 1200V IGBT)

R1 R2 R3 R4 R5 R6

1M 22K 10K 10K 10K 10K

R7 Rs C3 C4 C5

10K 0.01 0.01F 1F 0.01F

Op-amps Comparator Inverter Clock T

TL084 TL084 CD4069 555 2N2222

1312

analog controller

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