an125 design check for the qoriq p2020 processor · optimizes cpu performance on tcp/ip • tcp/ip...

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.

AN125Design Check for the QorIQ™ P2020 Processor

July 2009

Farshid ParandianApplications Engineer NCSG

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2Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.

Session Objectives

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Session Objectives

This session will:

• Provide overview and highlight the new features introduced with the QorIQ™ P2020 processor

• Provide the guidance and tips for developing systems , bring-up and troubleshooting

The information presented in this session will be rolled up intodesign checklist applications note for QorIQ P2020 processor.

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QorIQ™ P2020 Processor Overview

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5Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 5

Dual-core P2020 Block Diagram

Coherency Module

System Bus

32KB I-

Cache

e500 Core

32KB D-

Cache

System Bus

Enhanced Local Bus

64b

Perf Mon, DUART, MPIC2x I2C, Timers

On-Chip Network

32KB I-

Cache

e500 Core

32KB D-

Cache

512KB L2

DDR2/DDR3, SDRAM

Controller

Security Accel

XOR16b

USB2.0

eSPI

eSDHC

3x GE MAC

x4 SerDes

• Dual e500 cores built on Power Architecture®

technology • 800 - 1200 MHz• 512 KB Frontside L2 cache w/ECC, HW cache coherent• 36-bit physical addressing, DP-FPU

• System Unit• 64-/32-bit DDR2/DDR3 with ECC• Integrated SEC 3.1 Security Engine • Open-PIC Interrupt Controller, Perf Mon, 2x I2C, Timers,

16 GPIO’s, DUART• 16-bit Enhanced Local Bus supports booting from NAND

Flash• One USB 2.0 Host Controller with ULPI interface• SPI controller supporting booting from SPI serial Flash• SD/MMC card controller supporting booting from Flash

cards• Three 10/100/1000 Ethernet Controllers (eTSEC) w/

Jumbo Frame support, SGMII interface• Enhanced features: Parser/Filer, QOS, IP-Checksum

Offload, Lossless Flow Control• IEEE® 1588v2 support

• Two Serial RapidIO® controllers with integrated message unit operating up to 3.125 GHz

• Three PCI Express® 1.0a Controllers operating at 2.5 GHz

• Process and Package• 45 nm SOI, 1.05V +/- 50mV, 0C to 125C Tj

• with -40C to 125C Tj option• 689-pin TEPBGAII, 31x31mm

2x DMA PCI Express

Serial RapidIO

PCI Express

PCI Express

Serial RapidIO

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Single-Core P2010 Block Diagram

Coherency Module

System Bus

32KB I-

Cache

e500 Core

32KB D-

Cache

System Bus

Enhanced Local Bus

64b

Perf Mon, DUART, MPIC2x I2C, Timers

On-Chip Network

512KB L2

DDR2/DDR3, SDRAM

Controller

Security Accel

XOR16b

USB2.0

eSPI

eSDHC

x4 SerDes

• Single e500 core, built on Power Architecture®

technology • 800 – 1200 MHz• 512 KB Frontside L2 cache w/ECC, HW cache coherent• 36-bit physical addressing, DP-FPU

• System Unit• 64-/32-bit DDR2/DDR3 with ECC• Integrated SEC 3.1 Security Engine • Open-PIC Interrupt Controller, Perf Mon, 2x I2C, Timers,

16 GPIO’s, DUART• 16-bit Enhanced Local Bus supports booting from NAND

Flash• One USB 2.0 Host Controller with ULPI interface• SPI controller supporting booting from SPI serial Flash• SD/MMC card controller supporting booting from Flash

cards• Three 10/100/1000 Ethernet Controllers (eTSEC) w/

Jumbo Frame support, SGMII interface• Enhanced features: Parser/Filer, QOS, IP-Checksum

Offload, Lossless Flow Control • IEEE® 1588v2 support

• Two Serial RapidIO® controllers with integrated message unit operating up to 3.125 GHz

• Three PCI Express® 1.0a Controllers operating at 2.5 GHz

• Process and Package• 45 nm SOI, 1.05V +/- 50mV, 0C to 125C Tj

• with -40C to 125C Tj option• 689-pin TEPBGAII, 31x31mm

2x DMA PCI Express

Serial RapidIO

PCI Express

PCI Express

Serial RapidIO

3x GE MAC

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QorIQ™ P2020 and P2010 Processors

P2010 P2020

CPU e500 Up to 1200 MHz 32K I/D

Dual e500 Up to 1200 MHz 32K I/D

L2 Cache 512 KB DDR2/3 32/64-bit

512 KB DDR2/3 32/64-bit

10/100/1000 Ethernet (with IEEE1588v2)

3 w/(2) SGMII 3 w/(2) SGMII

PCI-Exp 1.0a 3 controllers w/ 4 SerDes

3 controllers w/ 4 SerDes

sRIO 1.2 2 x1 or 1 x4 2 x1 or 1 x4

USB2.0 1 1

Memory Card eSDHC eSDHC

Other interfaces eSPI, 2xI2C, DUART eSPI, 2xI2C, DUART

Accelerators SEC3.1 SEC3.1

Package 689 TEPBGAII 689 TEPBGAII

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e500v2 Core Architecture Up to 1.2 GHz

L1: 32KB, 8-way set associative, Parity

L2: Front Side: 8-way set associative, ECC

Cache line locking supported

MESI cache coherence

Peak IPC 2 Instructions plus 1 branch

Out of Order Execution

Multiple Book E APUs

16 TLB SuperPages

512-entry 4K Pages

36-bit Physical Address

Instruction Unit

CFX SFX2 LSU

GPRs

RenameBuffers

L1 Data MMUDTLBs

L1 Instruction MMUI-TLBs

Memory Unit

SFX1

L2 Unified MMUs

Book E APUs:Performance

Monitor,SPE, DPFPIsel, BTB,

Cache Line Locking,MachineCheck

Shared512kB Unified

FrontsideL2 Cache

CompletionUnit

Instruction Queue (12)

Branch Processing

Unit

GPR Issue (2)

DispatchUnit

Sequencer Fetcher 32KB

InstructionCacheTa

gsTa

gs 32KBData

Cache

MA

S

Core Complex Bus36-bit Address Bus

128-bit Rd/Wr Data Bus

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e500 Core 1

32KB D-cachew/Parity

RD1 RD2 WR

L2 Cache Controller

Shared 512 KB unified frontside L2 cache w/8-way associativity (each way: 64 KB)

Assignment Granularity :• One, two, four, or all eight “ways” of the cache can

be assigned as the following:• SRAM• Stash-Only• CPU0 L2 Only• CPU1 L2 Only• Both CPU0 and CPU1 L2

Stash-Only regions can now be defined• Prevents stash data from polluting processor data

and vice-versa• One, two or four “ways” of the cache can be

dedicated as Stash-Only

Stash Allocate Disable mode added• Allows update of all resident cache lines without

allocation of new lines

e500 Core 0

32 KB D-cachew/Parity

32 KB I-cachew/Parity

Core Complex Bus

CoherencyModule

e500v2 Core

64

128

128

RD1 RD2 WRRD_IN DOUT WR_IN

512 KBSRAM

Stash OnlyCPU0 L2

CPU0 & 1 L2CPU1 L2

Example

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eTSEC Controller

Optimizes CPU performance on TCP/IP• TCP/IP checksum offload Rx + Tx• IPv6 support in H/W

QoS support for 16 H/W queues (8 Rx + 8 Tx)• Customizable per-packet filing/filtering• 802.1p, IP TOS, Diffserv classification• Support for weighted fair queueing• TCP/UDP port-based flows• Assist firewall through IP/TCP/UDP reject• Ethernet preamble sorting and insertion

FIFO I/F to ASICs + (R)GMII/(R)MII/(R)TBI• 8-/16-bits @ OC-48 rates (155 MHz)

Layer 2 features• VLAN insertion and deletion per frame• 16 exact-match MAC addresses• Lossless Flow Control

Code compatible with PowerQUICC® III e/TSEC controllers

10/100/1000MAC

8b FIFOInterface

TCP/IPOffload

Quality ofServiceRx

FIFO2 KB

TxFIFO10 KB

64-bit DMA

GbE Controller 1

10/100/1000MAC

8b FIFOInterface

TCP/IPOffload

Quality ofServiceRx

FIFO2 KB

TxFIFO10 KB

64-bit DMA

GbE Controller 2

10/100/1000MAC

8b FIFOInterface

TCP/IPOffload

Quality ofServiceRx

FIFO2 KB

TxFIFO10 KB

64-bit DMA

GbE Controller 3

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eTSEC1 eTSEC2 eTSEC3

GMII/TBI/MII/8b FIFO GMII/TBI/MII/8b FIFO SGMII

RGMII/RTBI/RMII/8b FIFO RGMII/RTBI/RMII/8b FIFO/SGMII SGMII

16b FIFO SGMII SGMII

RGMII/RTBI/RMII RGMII/RTBI/RMII/SGMII RGMII/RTBI/RMII/SGMII

eTSEC Controller (continued)

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IEEE® 1588 Timer

IEEE 1588 timer module supports:• 64-bit free running timer running from an external

oscillator or internal clock• Programmable timer oscillator clock selection• Self-correcting precision timer with nano-second

resolution• Time stamp all incoming packets inline• Maskable interrupts on received PTP packet’s filer

rule match• Maskable interrupts on transmit timestamp capture• Maskable interrupts on GPIO timestamp trigger• Programmable polarity of external trigger (GPIO) • Maskable interrupts on alarm• Maskable interrupts associated with each pulse

Ethernet MACEthernet MAC

1588 TimerClock

SFD Detection Rx & Tx

Time StampRegister Array

eTSEC

SELTMRREG

TMRMAC

Rx Pins Tx Pins

Node A:Time = 9:04

NETWORK

Node B:Time = 9:29

Node C:Time = 9:28

Node A:Time = 9:04

Node B:Time = 9:04

Node C:Time = 9:04

NETWORK

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e500

Root Complex/ Endpoint

e500



PCI Express® Interface

Three PCI Express controllers PCI Express 1.0a compatible Supports x1, x2, and x4 link widths @ 2.5 Gbaud, 2.0 Gb/s

• Auto-detection of number of connected lanes Selectable as root complex or endpoint at initialization 32- and 64-bit addressing into PCI Express address space Root complex inbound support for MSI and INTx Endpoint support for outbound MSI Reads/writes carried across ports, but not a switch 256 byte maximum payload size One virtual channel Strong and relaxed ordering rules 8 non-posted, 6 posted transactions 3 inbound + 1 configuration window

• Translates upper 52b of PCI addr to upper 24b of local addr• Window sizes of 4 KB to 64 GB• Settings: read/write type, prefetchable, and target• 1 MB Config window maps to CCSR region

4 outbound + 1 default window• Translates upper 24b of local addr to upper 52b of PCI addr• Select I/O or memory for reads and writes• Window sizes of 4 KB to 64 GB

Switch

Peripheral Endpoint

Peripheral Endpoint

Peripheral Endpoint

ATMUs

Peripheral Endpoint

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Serial RapidIO® Interconnect The RapidIO port supports:

• Small or large size transport information field

• 34-bit addressing• Up to 256-byte data payload• Up to eight outstanding unacknowledged

RapidIO transactions• Hardware recovery only• All transaction flows and all priorities• Hot swap

Implementation• 1x or 4x serial, 1.25, 2.5, and 3.125

GBaud• Read/write bridged between PCI

Express® port• Message Unit RMU supports:• Two outbound and two inbound• message controllers• One outbound and one inbound doorbell

controllers• One inbound port-write controller

RapidIO endpoints supports:• Nine outbound ATMU windows with• each window having up to 32• subwindows except the default window• Five inbound ATMU windows• Logical outbound packet time-to-live• counter to prevent local processor from• hanging when the RIO interface fails• Accept-all mode of operation for failover• Support• RapidIO random bit error injection• Performance monitor interface

Message Unit

Shift Register

RapidIOSignals

OC

N F

abric

SerDesInterface

Block RapidIO Cfg

RapidIOLogical

Serial RapidIO

RapidIOPhysical

RapidIO Portn

OCNPorts

Msg Unit Logical

RapidIO Cfg

OCNPort

OCNPort

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USB Controller

Complies with USB specification rev 2.0• High Speed (HS) = 480 Mbit/s• Full Speed (FS) = 12 Mbit/s• Low Speed (LS)= 1.5 Mbit/s

EHCI Compliant

Hi-Speed, Full-speed, and Low-speed

USB dual role controller• Device Controller

Six programmable USB bi-directional endpoints• Host Controller

USB root hub with one downstream facing portEHCI compatible

Supports external USB PHYs• ULPI (UTMI+ Low Pin Interface)• Full Speed Serial

& Buffer RAM

System Interface

eSDHCController

TxBuffer

System Interface

USBController

Dual-Role Module (DR)

RxBuffer

ULPI

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eSDHC Controller

Works with SD/MMC cards

Supports SD 1-bit/4-bit cards, • SD Memory Card Specification version

2.0, support High Capacity SD Memory Card

• SD Host Controller Std Spec, Ver 2.0

Supports MMC 1-bit/4-/8-bitcards

• Compatible with the MMC System Specification version 4.0

Supports Single Block, Multi Block read and write

Supports Auto CMD12 for multi-block transfer

Host can initiate non-data transfer command while data transfer is in progress

Supports SDIO Read Wait and Suspend/Resume operations

CMD/Data

Channel TX/RX

Handler

CMD

DAT4

SD_CLK

DAT3

DAT2

DAT1

DAT0

SD_CD SD_WP

Status Register &Interrupt Controller

Embedded DMA

Clock Controller &

Reset Manager

SD Bus Monitor & Gating

Controller & Buffer

RAM

Register Bank

Logic Control

CRC

CMD Channel State

Machine

Logic Control

CRC

Data Channel State

Machine

System Interface

eSDHCController

CMD

DAT4

SD_CLK

DAT3

DAT2

DAT1

DAT0

SD_CD SD_WP

Logic Control

CRC

CMD Channel State

Machine

Logic Control

CRC

Data Channel State

Machine

eSDHCController

CMD/Data

Channel TX/RX

Handler

Status Register &Interrupt Controller

Embedded DMA

Clock Controller &

Reset Manager

SD Bus Monitor & Gating

Controller & Buffer

RAM

Register Bank

Logic Control

CRC

CMD Channel State

Machine

Logic Control

CRC

Data Channel State

Machine

System Interface

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eSPI Controller

eSPI Controller supports: Full- and half-duplex

operation eSPI master and RapidS full

clock cycle operation support 32 Byte TX and 32 Byte RX

Buffers 16 and 24 bit Addressing Supports a range from 4-bit to

16-bit data characters Supports back-to-back

character transmission and reception

Supports single master SPI mode

Independent programmable baud rate generator

Programmable clock phase and polarity

4 Chip Selects Local loopback for testing

SPI Signal ControllerSPICLK

SPIMOSI

SPIMISO

SPI Signal Interface

Receive Register &

Buffer

Transmit Register &

Buffer

Clock Controller &

Reset Manager

Baud Rate Generator

ControllerSPI

Register Bank

CounterShift Register

System Interface

SPI Controller

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Security Engine – SEC 3.1 Public Key Execution Unit supports:

• RSA and Diffie-Hellman (to 4096b)• Elliptic curve cryptography (1023b)• Supports Run Time Equalization

DES Execution Unit• DES, 3DES (2K, 3K)• ECB, CBC, OFB modes

AES Execution Unit• Key lengths of 128, 192, and 256b• ECB, CBC, CTR, CCM, GCM,

CMAC, OFB, CFB, and XTS

Message Digest Execution Unit• SHA-1 160-bit digest• SHA-2 256-bit digest• SHA-384/512• MD5 128-bit digest• HMAC with all algorithms

ARC Four Execution Unit• Compatible with RC4 algorithm

Kasumi Execution Unit (KEU)• F8 , F9 as required for 3GPP• A5/3 for GSM and EDGE• GEA-3 for GPRS

Snow 3G Execution Unit (STEU)• Implements Snow 3GPP

CRC Execution Unit• CRC32, CRC32C

XOR acceleration

Random Number Generator

Multi-OS friendly

crypto-channel

crypto-channel

crypto-channel

crypto-channel

Control

PKEU

FIFO

FIFO

DEU

FIFO

FIFO

AESUXOR

FIFO

FIFO

AFEU

FIFO

MDEUFIFO

RNG

FIFO

CRC

FIFO

FIFO

KEU

On-ChipSystem

Interface

FIFO

FIFO

KEU

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Enhanced Local Bus Controller (eLBC)

Multiplexed 32-bit address and 16-bit data operating to 150 MHz

Eight chip selects support eight external slaves

Odd/even parity checking

Atomic operations

Write protection capability

Parity byte-select

General-purpose chip-select machine (GPCM)• Compatible with SRAM, EPROM, FEPROM, and peripherals• Global (boot) chip-select available at system reset• Boot chip-select support for 8- and 16-bit devices• Minimum 3-clock access to external devices• Two byte-write-enable signals (LWE[0:1])• Output enable signal (LOE)• External access termination signal (LGTA)

Three user-programmable machines (UPMs)• Can be programmed to support to ZBT and NoBL SRAMs, NAND and NOR Flash and Compact Flash• Programmable-array-based machine controls external signal timing with a granularity of up to one-

quarter of an external bus clock period• User-specified control-signal patterns can be initiated by software• Support for 8- and 16-bit devices

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Enhanced Local Bus Controller (eLBC) – cont’d

NAND Flash Control Machine (FCM) • Support for small page (512 data bytes + 16 spare bytes) and large page

(2,048 data bytes + 64 spare bytes) parallel NAND flash E2PROM devices• Support for hardware-based ECC checking and generation• Global (boot) chip-select available at system reset, with 4 Kbytes boot block

buffer for execute-in-place boot loading• Boot chip-select support for 8-bit devices• Dual 2-Kbyte/eight 512-byte buffers allow simultaneous data transfer during

flash reads and programming• Interrupt-driven block transfer for reads and writes• Support for user-programmable command and data transfer sequences of

up to eight steps• Support for proprietary flash interfaces through generic command and

address registers• Block write locking to ensure system security and integrity• Support for checking/verifying ECC for NAND flash boot blocks

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Memory Controller

• DDR2 and DDR3• 64-bit (72 bits with ECC)• 32-bit (40 bit with ECC)• 4 chip selects• Support for up to 4 Gb devices,

x8, x16, x32 configurations• Up to 4 GB DIMMs per bank• Up to 16 GB• Supports self-refresh mode• Battery backup• Initialization bypass• Chip-select interleaving• Automatic DRAM initialization• Error injection

ECM

e500 Core

System Bus

DDR2/DDR3, SDRAM

Controller

e500 Core

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GPIO Function

The GPIO features:• 16 input/output ports• All GPIO signals are

configured as inputs when the device comes out of reset and also when HRESET is asserted.

• Open-drain capability on all ports

• All ports can optionally generate an interrupt

GPIO[0:15]

RegisterInterface

GPIO Block Diagram

GPIER/GPIMR/GPICRRegisters

GPDATRegister

GPDIR/GPODRRegisters

gpio_int

To/FromPeripheral Bus

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Power Supply

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Power Supply Voltage

Core VDD = 1.05 V

PLL supply voltage for Core0, Core1, DDR, LBIU, Plat, Srds

AVDDx = 1.05 V

Pad Power supply for SerDestransceivers and PCIE

XVDD = 1.05 V

DDR2 DRAM I/O voltageDDR3 DRAM I/O voltage

GVDD = 1.8 V GVDD = 1.5 V

TSEC I/O LVDD = 3.3 V or 2.5 V

DUART, system control and powermanagement, I2C, and GPIOx8, JTAG I/O voltage

OVDD = 3.3 V

Enhanced Local bus I/O andGPIOx8 voltage

BVDD = 3.3 V, 2.5 V, or 1.8 V

Core Power supply SerDestransceivers

SVDD = 1. 05 V

USB, eSPI, eSDHC voltage CVDD = 3.3 V, 2.5 V, or 1.8 V

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Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power-up:

• VDD, AVDD_n, BVDD, LVDD, OVDD,CVDD, XVDD_SRDS and XVDD_SRDS

• GVDD

NOTE: Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs.

NOTE: If any of the I/O power supplies ramp prior to VDD core supplies, the associated I/O supply may drive a logic one or zero during power- up thus causing excessive current to be drawn by the device.

All supplies must be at their stable values within 50 ms.

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Power Decoupling Recommendations

QorIQ™ P2020 processor requires a clean regulated power source

Large address and data buses, high operating frequencies can cause noise

Recommendations• Place decoupling capacitors at each VDD, OVDD, GVDD, LVDD BVDD CVDD pin

Each capacitor should have short traces to power to minimize inductanceValue and Type required depends on simulation; recommend 0.01 and 0.1 mF

• Place bulk storage capacitors around PCB to feed each power planeEnables quick recharging of the smaller chip capacitors.Use capacitors with low ESR ratingTo minimize inductance, connect through two vias to power and groundValue and Type required depends on simulation; recommend 100-330 mF

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SerDes: Power Supply

There are three different supplies used in SerDes Block

• SVDD: Core power supply for SerDes transceivers16 pins

• XVDD: Pad power supply for SerDes transceivers10 pins, Signals on the SerDes interface are fed from the XVDD power plan. It needs to be taken into consideration for designing XVDD return path on PCB.

• AVDD_SRDS: SerDes PLL supply

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PLL Filter Circuit

Provide independent filter circuit to each of the AVDD pins• AVDD_PLAT, AVDD_CORE[0:1], AVDD_DDR, and AVDD_LBIU, respectively• Independent circuits reduces chance of noise injection between PLLs

• R = 5 W ± 5% • C1 = 10mF ± 10%, 0603, X5R, with ESL <= 0.5 nH• C2 = 1.0 mF ± 10%, 0402, X5R, with ESL <= 0.5 nH

• Circuit will filter noise in 500 KHz to 10 MHz range• Use surface mount capacitors with a low Effective Series Inductance (ESL)• Place as close to AVDD as possible to reduce noise

VDD AVDD

R

C1 C2

GNDLow ESL surface mount capacitors

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SerDes: PLL Filter Circuit

AVDD_SRDS should be a filtered version of SVDD

The AVDD_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDS ball to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDS ball.

All traces should be kept short, wide, and direct.

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SerDes: Power Decoupling (SVDD and XVDD)

SerDes Block Power Supply Decoupling Recommendations• The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD)

to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance.

• First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible.

• Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies.

• Third, between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies (XVDD and SVDD).

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Reset Configuration, Clocking and Initialization

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POR Configuration

QorIQ™ P2020 processor initializes the various device functions by sampling power-on reset (POR) configuration pins during the assertion of HRESET_B.

All POR configuration pins are typical multiplexed with the output signals (such as TX_Data) during the normal operation.

All POR configuration pins have internal pull-up resistor (~20 KW) and those resistors are activated only during the POR configuration; POR pins can be pulled high or low by external resistors for configuration.

During HRESET, all other signal drivers connected to these POR configuration signals must be in the high-impedance state.

• Reason: If other devices also drive POR pin during HRESET, P2020 may sample the wrong POR configuration information from the POR pin.

• For example: P2020 TSEC2_TXD[00] and TSEC2_TXD[07] pins are also POR pins, if the external devices drive those pins accidentally during POR, it may cause the device into a wrong configuration mode.

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POR Configuration Timing

The following timings are found in the respective Hardware Specification

• Required minimum assertion time of HRESET# 100 μs

• PLL configurations (w/stable SYSCLK) must meet a 100 μs set-up time with respect to the negation of HRESET#

• All other POR inputs have a 4 SYSCLK set-up time with respect to the negation of HRESET#

• All configuration inputs have a 2 SYSCLK hold time with respect to the negation of HRESET#

• Minimum assertion time for SRESET# 2 SYSCLK

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Power-On Reset Sequence

Stable PLL configuration input

POR Configuration input

Stable SYSCLK signal

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Clocking Quick Reference

Functional Block Clocked by… Restrictions

Local Bus CCB_clk / [ 4, 8, 16] LBIU PLL bypass mode is recommended when LBIU frequency is at or below 83 MHz; When LBIU operates above 83 MHz, LBIU PLL is recommended to be enabled

PCI Express® and Serial RapidIO® digital logic

CCB_clk/2

SerDes for PCIe, sRIOand SGMII

SD_REF_CLK/SD_REF_CLK_B

100 MHz ref clk for PCIe 1.25 Gbps and 2.5 Gbps100 MHz ref clk for sRIO 1.25 Gbps and 2.5 Gbps125 MHz ref clk for sRIO 3.125 Gbps100 MHz ref clk for SGMII 1.25 GbpsFor PCIe, CCB_clk > (527 MHz x PCI Express link width) / 8For sRIO, CCB_clk > 2×(0.80)×(serial RapidIO interface frequency)×(serial RapidIO link width) /64

I2C CCB_clk / (2* I2CFDR[FDR]ratio)

External source or CCB_clk

The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB clock; The minimum RTC frequency is zero.

Real Time Clock (RTC)

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Clocking Quick Reference (continued)

Functional Block Clocked by… Restrictions

e500 core and L1 cache

Core-complex-bus clock (CCB_clk) times a multiplier

CCB_clk

External clock source

DDR CCB_clk / 2 400 MHz=< DDR data rate =<800 MHz;For DDR3: the minimum data rate is 667 MHz

eTSEC logic layer is clocked by CCB_clk /2;MAC layer is clocked by 125 MHz from PHY or External;

eTSEC FIFO mode TSECn_RX_CLK and TSECn_TX_CLK

For FIFO GMII mode: FIFO TX/RX clock frequency <= platform clock frequency / 4.2For FIFO encoded mode: FIFO TX/RX clock frequency <= platform clock frequency / 3.2

L2 cache and ECM

533 MHz=< core freq =<1.2 GHz

266 MHz=< CCB_clk (platform clock) =<600 MHz

SYSCLK 66.66 MHz=min, & 100 MHz=maxSYSCLK

EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cyclegenerated by the eTSEC GTX_CLK.

eTSECs

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SerDes Reference Clock Guideline

The SerDes reference clock inputs are SD_REF_CLK and SD_REF_CLK_B.

Each differential clock input phase has a 50 ohm termination to GND. The reference clock must be able to drive this termination. The input is AC-coupled on chip following the termination.

The input amplitude of the clock must be between 400 mV and 1600 mV differential peak-peak. In addition, each phase of the input clock must be less than 800 mV peak-peak.

The common mode voltage at the clock inputs must be between 0 and 400 mV.

The differential reference clock (SD_REF_CLK/SD_REF_CLK) input is HCSL compatible DC coupled or LVDS compatible with AC coupling.

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Boot Mode: CPU Boot Mode (Boot Sequencer Disabled)

Configured with POR pins cfg_boot_seq[0:1] =0b11 (default)

Default boot ROM address range to be 8 Mbytes at address 0x0_FF80_0000 to 0x0_FFFF_FFFF. This boot ROM address is assigned to a peripheral interface.

The boot peripheral interface is selected by the POR configuration pins cfg_rom_loc[0:3] to be:

• DDR, SRIO1, or 2, PCIE1,2, or 3 , LBIU_GPCM (8-bit ROM, 16-bit ROM or 32-bit ROM), LBIU_FCM (8-bit NAND flash) and On-chip boot ROM –eSPI or eSDHC.

• POR pins cfg_rom_loc[0:3] =0b111 is default selection for CPU boot mode from local bus GPCM 16-bit ROM

Initial Instruction Fetch• The e500 core always begins execution at fixed virtual address 0xFFFF_FFFC. • The MMU has a default page translation which maps this to the identical physical address.

So, the instruction at physical address. • 0xFFFF_FFFC must be a branch to another address within the 4-Kbyte boot page.

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Boot Mode: Boot Sequencer

Configured with POR pins cfg_boot_seq[0:1]

Enables user to configure memory mapped registers prior to running boot up code. In terms of application, for example, it can be used to:

• Configure local-bus UPM to interface to burst-able flash instead of standard flash memory before the core starts to fetch the 1st instruction

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Boot Mode: CPU Boot Hold-off

Configured with pin cfg_cpu0_boot = 0b0 for Core0 and cfg_cpu1_boot = 0b0 Core1

Allows external masters (Serial RapidIO®, PCI Express® etc.) to configure QorIQ™ P2020 memory mapped registers

Suspends the core from fetching boot code

Resumes reset sequence when EEBPCR[CPU0_EN] for Core0 and EEBPCR[CPU1_EN] for Core1 is set by external masters

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Hardware Considerations

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The following pins must NOT be pulled down during power-on reset, otherwise it may trigger the internal test mode:

• DMA1_DACK[00]

• USB1_STP

• HRESET_REQ

• MSRCID[2:3]

• MDVAL

• ASLEEP

POR Configuration Pins Termination Requirements

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When eTSEC1 and eTSEC2 are used as parallel interfaces, pins TSEC1_TX_EN and TSEC2_TX_EN requires an external 4.7-kW pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven.

TSEC2_TXD[01] is used as cfg_dram_type. It must be valid at power-up, even before HRESET assertion.

Unused eTSEC pin terminationFor I/Os, tie signals high or low through a resistor. Recommended resistor values are 2–10K ohm. For inputs, tie signals to their inactive state through a resistor; clock inputs may be tied high or low. Recommended resistor values are 2–10 K ohm.

eTSEC Pin Termination

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Local Bus Termination

Termination is not needed on output signals.

For bidirectional I/Os, tie signals high or low though a resistor. Recommended resistor values are 2–10 K ohm

For inputs, tie signals to their inactive state through a resistor. Recommended resistor values are 2–10 K ohm.

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DDR Termination

Please refer to Application Note AN2910:

• “Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces”

• MDIC[0:1] are used for automatic calibration of the DDR IOs.

• MDIC[00] is grounded through an 18.2-W (full-strength mode) or 36.4-W (half strength mode) precision 1% resistor.

• MDIC[01] is connected to GVDD through an 18.2-W (full-strength mode) or 36.4 (half-strength mode) precision 1% resistor.

• DDRCLK input is only required when the P2020 DDR controller is running in asynchronous mode. When the DDR controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode.

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Suggestion on Power Supply and Power Supply Test Point For prototype board, suggest isolating power supplies and have independent controls over:

• VDD, AVDDs ( Core and PLLs)• SVDD (SerDes core) • XVDD (SerDes pad)• OVDD (DUART, I2C,JTAG etc...)• LVDD (eTSECs)• GVDD (DDR)• BVDD (local bus)• CVDD (USB,eSPI,eSDHC)

The voltage range should be adjustable. Particularly for VDD, AVDDs, SVDD and XVDD, they should be adjustable at least between 1.0 V to 1.1 V nominal.

Have test points near processor for these power supplies particularly for VDD, AVDDs, SVDD and XVDD.

The resistor is a critical component in the RC filter. For all AVDD except AVDD_SRDS, should be 5-ohms +/-5% resistor, for AVDD_SRDS, 1 ohm.

SD_IMP_CAL_RX is grounded through an 200-Ohm precision +/-1% resistor and SD_IMP_CAL_TX is grounded through an 100-Ohm precision +/-1% resistor.

Incorrect settings of voltage select configuration pins for L/B/CVDD_VSEL can lead to irreversible device damage.

Have visibility of all processor BGA pins on the back of card.

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Test Points and Pin Visibility

For easier debug, recommend to have the test points or at least visibility on the board for the following pins:

• TRIG_OUT/READY (This helps to verify the end of the reset sequence)• TRIG_IN (Trigger in to trigger the watchpoint and trace buffers. Note: this is an active-high rising-edge

triggered signal)• IRQ_OUT (Interrupt output)• ASLEEP (This helps to verify the end of the reset sequence)• HRESET_REQ (This helps to verify proper boot sequencer functions and reset requests)• MSRCID [0:4] (This helps identify the owner of the bus cycle)• MDVAL (This helps identify when the data is valid)• SD_PLL_TPA (SerDes Analog PLL lock indication)• SD_PLL_TPD (SerDes Digital PLL lock indication)• CKSTP_OUT[0:1] (e500 checkstop indication)• CLK_OUT (This helps to verify the CCB clock)• SYSCLK (To verify input clock at the device pin) • DDRCLK ( To verify DDR Clk when in asynchronies mode)• DDR MCK[0:5] and MCK_B[0:5] - visibility of at least one data bit for each clock domain and its

associated clock to check the data eye and signal integrity.• LCLK[0:2] - local bus clock, at least make one of signals visible.• SD_REF_CLK and SD_REF_CLK_B (Reference clocks for SRIO/PCI Express SerDes block)• SerDes Transmission Lanes• Berg connector would be optimum if it is a differential clock

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POR configuration inputs

These configuration signals may be used in the future to control functionality. It is advised that boards are built with the ability to pull-up or pull-down these pins.

• LA[20] - cfg_eng_use[00]• LA[21] - cfg_eng_use[01]• LA[22] -cfg_eng_use[02]• UART_SOUT[00]- cfg_eng_use[03]• TRIG_OUT -cfg_eng_use[04]• MSRCID[01] -cfg_eng_use[05]• MSRCID[04]- cfg_eng_use[06]• DMA1_DDONE[00]- cfg_eng_use[07]

The settings for the following POR pins will determine CPU boot enable, PLL ratios and boot device selection:

• LA[29:31] - cfg_sys_pll[0:2]• LBCTL, LALE, LGPL2 - cfg_core0_pll[0:2]• LWE0, UART_SOUT1, READY_P1 - cfg_core1_pll[0:2]• TSEC1_TXD[6:4],TSEC1_TX_ER - cfg_rom_loc[0:3]• LA[27] - cfg_cpu0_boot• LA[16] - cfg_cpu1_boot• LGPL3, LGPL5 - cfg_boot_seq[0:1]

POR configuration timing. For example, PLL input setup time with stable SYSCLK before HRESET negation need meet 100 microsecond requirement.

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Suggestion on Logic Analyzer connections

• DDR2/3 memory bus• Address bus• Data bus• Control signals (RAS, CAS, etc)• Debug Assist pins• Source ID: MSRCID[0:4]• Data Valid: MDVAL

• Local bus• Address bus• Data bus• Control signals (CS, WE, etc)• Debug Assist pins• Source ID: MSRCID[0:4]• Data Valid: MDVAL

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3rd Party Tool Operability

For 3rd Party Tool operability, /HRESET and /TRST must be able to assert independently of each other

If 3rd party probes are to be used, do not tie /HRESET to /TRST

COP/

JTAG

Hea

der

4

13

From Target Board Sources (If any)

HRESET

MPC

Pro

cess

or

OVDD

OVDD

HRESET

TRST

OVDD

10 KΩ

10 KΩ

10 KΩ

TRST

HRESET

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QorIQ™ P2020 Hardware Platforms

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ATX P2020DS-PA (Development System) P/N: P2020DS-PA (orderable) Availability: June-09 Software: Prototype Linux®

AMP/SMP BSP Memory

• DDR3 – 1GB• NOR Flash – 128 MBN• NAND Flash – 1 GB• SPI ROM – 16 MB • NVRAM: 256B

PCI Express®: Dual x2 slot Ethernet

• eTSEC1: RGMII• eTSEC2: RGMII or SGMII• eTSEC3: RGMII or SGMII

IEEE® 1588• Clock input from DAC / VCXO

circuitry• Accessible via test header

Dual I2C SD/MMC card slot USB Type A connector UARTs: Two DB9 connectors SATA2 GPIO: 16

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P2020RDB (Mini-ITX Reference Design Board) P/N: P2020RDB-PA

Availability: July-09

SW: Linux® BSP

Memory• DDR2 – 1GB • NOR Flash – 16 Mbyte (128Mbit device)• NAND Flash – 32 MByte• SPI ROM – 16 MByte

PCI Express®• One standard PCIe connector (x1)• One mini PCIe connector (x1)

Ethernet• Six 10/100/1000 ports as follows:• 4-ports from L2 switch connected to eTSEC1• 1 SGMII PHY connected to eTSEC2• 1 RGMII PHY connected to eTSEC3

IEEE® 1588• Clock input from DAC / VCXO circuitry• Accessible via test header

Dual I2C

SD/MMC card slot

USB• Option #1 -Mini AB connectors on IO Panel

(default)• Option #2 –Type A connectors (front panel)

UARTs: Two DB9 connectors

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an125 design check for the qoriq p2020 processor · optimizes cpu performance on tcp/ip • tcp/ip...

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