an investigation of fundamental frequency limitations for
TRANSCRIPT
An Investigation of Fundamental Frequency Limitations
for HF/VHF Power Conversion
Chucheng Xiao
Dissertation submitted to the faculty of the Virginia Polytechnic Institute and State
University in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
In
The Bradley Department of Electrical and Computer Engineering
Dr. Willem G. Odendaal, Chairman
Dr. Jacobus D. van Wyk
Dr. Ahmad Safaai-Jazi
Dr. Guo Q. Lu
Dr. Elaine P. Scott
July 12, 2006
Blacksburg, Virginia
Keywords: frequency limitations, high frequency, very high frequency, power conversion
Copyright 2006, Chucheng Xiao
An Investigation of Fundamental Frequency Limitations for HF/VHF
Power Conversion
Abstract
By Chucheng Xiao
W.G. Odendaal, Chairman
The volume reduction in power converters over the past several decades can
chiefly be attributed to increases in switching frequency. It is to be expected that the
trends towards miniaturization will maintain steady pressure to keep this pace of
increasing switching frequencies of power converters. However certain fundamental
limits in high frequency power conversion are being reached as frequencies are being
pushed deeper into the megahertz range, inhibiting substantial further increases.
The work reported in this dissertation is intended to systematically investigate the
fundamental frequency limitations, identify some of the solutions for HF/VHF power
conversion and to provide guidelines and tools to optimize the performance of power
converters by maximizing frequency.
A number of multi-megahertz power converters are examined to evaluate the
present status and future trend of HF/VHF power conversion. An interesting trend
between power level and frequency is observed. A general limitation about the power
level and frequency, independent of design details, is derived from the physics of the
semiconductor devices, which determines the upper bound of the power levels as
frequency increases.
A 250 MHz DC-DC power converter (derived from the Class E power amplifier)
is analyzed and demonstrated with discrete components, which again verifies the trend
between power level and frequency. The power losses in the semiconductor devices are
discussed, and optimization criteria for minimizing the power losses of the devices, are
discussed. By relating the power losses to the semiconductor materials’ properties, a
iii
methodology for selecting proper materials is identified for high frequency and high
efficiency power conversion.
The frequency scaling effects of passive components, still dominating the volume
of the modern power converter, is analyzed. A generic multi-disciplinary methodology is
developed to analyze and maximize frequency and performance of passive components in
terms of power density and efficiency. It is demonstrated how the optimum frequency can
be identified, and how power conversion efficiency deteriorates beyond this optimum
under a fixed maximum temperature.
Power loss measurement is becoming more challenging as higher frequency and
higher efficiency power conversion. To achieve an accurate power loss measurement in a
high frequency, high efficiency power electronics system or component, limitations of
electrical measurement are identified, and various calorimetric methods are surveyed.
Calorimetric methods are more accurate due to the direct heat loss measurement. An
advanced calorimetric system is proposed, analyzed, and tested, demonstrating about 5%
error in total losses up to 25W.
Acknowledgements
iv
Acknowledgements
I would like to express deep and sincere gratitude to those who made this work
possible.
Thank you so much for my advisor, Dr. Odendaal. You have been giving me so
much valuable guidance and continuous support, which has been my source of inspiration
to accomplish this work. From the first day I met with you, I learned so much from the
weekly discussion and I got so much encouragement to solve the research issues one by
one. Without your support, this work would have been simply impossible to accomplish.
It is really fortunate for me to have this opportunity to study under your mentorship.
I would also like to express my appreciation to constant help and encouragement
from my committee members: Prof. van Wyk, Prof. Ahmad S.J., Prof. E.P. Scott and Prof.
G.Q. Lu. Your instructions and suggestions helped me a lot to improve my research and
presentation capabilities.
I would like to thank all the supports and helps from the staff and faculties of
CPES. Without you, things can’t be done smoothly.
I very appreciated the happy times with all my colleagues in CPES and kind helps
and advices from them.
I would forever remember the constant supports, love, encouragement,
understandings and sacrifice from my family for so many years of studying life.
This work made use of ERC Shared Facilities supported by the National Science
Foundation under Award Number EEC-9731677.
Acknowledgements
v
To my father Bingyan & mother Lamei
and
My wife Xiaoyan & sons
Table of Contents
vi
Table of Contents
ABSTRACT .................................................................................................................................. II
ACKNOWLEDGEMENTS........................................................................................................ IV
TABLE OF CONTENTS............................................................................................................ VI
TABLE OF FIGURES ................................................................................................................ IX
LIST OF TABLES.................................................................................................................... XIV
CHAPTER 1 INTRODUCTION............................................................................................... 1
1.1. BACKGROUND ................................................................................................................ 1
1.2. LIMITATIONS OF HF/VHF POWER CONVERSION ........................................................... 2
1.2.1. Introduction ............................................................................................................... 2
1.2.2. Monolithic Integration and Converters-On-a-Chip .................................................. 3
1.2.3. Modeling and Design................................................................................................. 4
1.2.4. Semiconductor Device Technologies ......................................................................... 5
1.2.5. Circuit Toplogies and Control Strategies for VHF Power Conversion..................... 7
1.2.6. Device Characteristics for future HF/VHF conversion technologies........................ 8
1.2.7. Passive Components .................................................................................................. 9
1.2.8. Packaging and Integration Techniques ................................................................... 11
1.2.9. Thermal Management.............................................................................................. 12
1.2.10. Measurement Issues ............................................................................................ 12
1.3. OBJECTIVE OF THIS STUDY .......................................................................................... 13
1.3.1. Chapter 2: HF/VHF Power Conversion Technology Review and Discussion ........ 14
1.3.2. Chapter 3: Analysis and Design of RF Class E DC-DC power converter .............. 14
1.3.3. Chapter 4: Fundamental Frequency Limitations of Passive Components for
HF/VHF Power Conversion ................................................................................................. 15
1.3.4. Chapter 5: Power Loss Measurement Techniques for HF/VHF power conversion
Applications .......................................................................................................................... 15
CHAPTER 2 HF/VHF POWER CONVERSION TECHNOLOGY REVIEW AND
DISCUSSION ............................................................................................................................. 17
Table of Contents
vii
2.1. INTRODUCTION............................................................................................................. 17
2.2. RESONANT SWITCHING TECHNIQUES IN CONVENTIONAL CONVERTERS ...................... 18
2.3. HIGH SPEED SWITCHING DEVICES IN CONVENTIONAL CONVERTERS........................... 19
2.4. MONOLITHICALLY INTEGRATED CONVENTIONAL POWER CONVERTERS BY VLSI ...... 22
2.5. NEW ARCHITECTURE DC-DC CONVERTERS DERIVED FROM CLASS E POWER AMPLIFIER
...................................................................................................................................... 27
2.6. TRENDS OF POWER LEVEL WITH INCREASING FREQUENCY ........................................ 30
CHAPTER 3 ANALYSIS AND DESIGN OF RF CLASS E DC-DC POWER
CONVERTER ............................................................................................................................. 36
3.1. INTRODUCTION............................................................................................................. 36
3.2. ANALYSIS OF CLASS E RF DC-DC CONVERTER.......................................................... 37
3.2.1. Operation principle of Class E inverter .................................................................. 37
3.2.2. Circuit Analysis based on ideal operation............................................................... 39
3.2.3. Practical considerations.......................................................................................... 47
3.2.4. Analysis of rectifier.................................................................................................. 53
3.2.5. Resonant gate driver of Class E inverter................................................................. 58
3.2.6. Discussion of matching network between the inverter and rectifier........................ 65
3.2.7. Experimental results and discussion ....................................................................... 68
CHAPTER 4 FUNDAMENTAL FREQUENCY LIMITATIONS OF PASSIVE
COMPONENTS FOR HF/VHF POWER CONVERSION..................................................... 78
4.1. BACKGROUND .............................................................................................................. 78
4.2. SETTING UP THE MODEL ............................................................................................... 81
4.3. PERFORMANCE OF MAGNETICS AS A FUNCTION OF FREQUENCY................................. 85
4.4. PERFORMANCE OF DIELECTRICS IN A CAPACITOR AS A FUNCTION OF FREQUENCY.... 97
4.5. EXPERIMENTAL VERIFICATION ON FREQUENCY SCALING EFFECTS OF INTEGRATED
INDUCTOR ............................................................................................................................... 112
4.6. SUMMARY .................................................................................................................. 120
CHAPTER 5 POWER LOSS MEASUREMENT TECHNIQUES FOR HF/VHF POWER
CONVERSION APPLICATIONS........................................................................................... 121
5.1. INTRODUCTION........................................................................................................... 121
5.2. LIMITATIONS OF ELECTRICAL MEASUREMENTS FOR POWER LOSS MEASUREMENT ... 122
5.2.1. Background............................................................................................................ 122
Table of Contents
viii
5.2.2. Direct Wattmeter Measurement [139]................................................................... 125
5.2.3. Digital Measurement Techniques .......................................................................... 126
5.3. REVIEW OF CALORIMETRIC METHOD FOR LOSS MEASUREMENT ............................... 129
5.3.1. Introduction ........................................................................................................... 129
5.3.2. Basic Principle of Operation ................................................................................. 130
5.3.3. Open-type Balance Calorimeter ............................................................................ 132
5.3.4. Double-jacketed, Closed Type Calorimeter........................................................... 134
5.3.5. Calorimeter Based on Heat-flux Sensor ................................................................ 137
5.3.6. Summary ................................................................................................................ 138
5.4. PROPOSED CALORIMETER FOR LOSS MEASUREMENT................................................. 139
5.4.1. Introduction ........................................................................................................... 139
5.4.2. Thermal analysis of the proposed calorimeter ...................................................... 143
5.4.3. Calibration and experiment................................................................................... 150
5.5. SUMMARY .................................................................................................................. 152
CHAPTER 6 CONCLUSION AND FUTURE WORK....................................................... 154
6.1. CONCLUSION .............................................................................................................. 154
6.2. FUTURE WORK............................................................................................................ 158
REFERENCES .......................................................................................................................... 160
APPENDIX I IMPLEMENTATION OF RF DC-DC POWER CONVERTER ................. 176
APPENDIX II VOLTAGE MEASUREMENT PROBE........................................................ 185
APPENDIX III DESIGN OF THE PROPOSED CALORIMETER .................................... 188
APPENDIX IV FABRICATION PROCESSING OF THE INTEGRATED INDUCTOR 194
VITA........................................................................................................................................... 198
Table of Figures
ix
Table of Figures
Fig. 1.1 Size evolution of modular telecom power conversion units [2]. ........................... 2
Fig. 1.2 Evolution of power semiconductor devices........................................................... 5
Fig. 1.3 Frequencies of different power supply technologies used in power conversion vs.
time. ............................................................................................................................ 6
Fig. 2.1 Basic structures for soft resonant switching ........................................................ 18
Fig. 2.2 Basic circuit diagram of ZVS QRC in [37]. ........................................................ 19
Fig. 2.3 Experimental results of Buck in [39]................................................................... 21
Fig. 2.4 Parasitic impedances and transistor geometric sizes of Buck converter. ............ 25
Fig. 2.5 Maximum efficiency with low-swing (LS) and full-swing (FS) Buck converters
vs. tapering factors. ................................................................................................... 26
Fig. 2.6 Schematic of DC-DC converter operating at 22 MHz. ....................................... 28
Fig. 2.7 Layout of 4.5 GHz DC-DC converter. ................................................................ 29
Fig. 2.8 Switching DC-DC power converter at 100 MHz. ............................................... 30
Fig. 2.9 Power level vs frequency for selected converters. .............................................. 32
Fig. 2.10 Efficiency vs frequency for selected converters................................................ 32
Fig. 3.1 Block diagram of proposed RF DC-DC converter. ............................................. 36
Fig. 3.2 Class E inverter.................................................................................................... 37
Fig. 3.3 Series resonant circuit.......................................................................................... 38
Fig. 3.4 Waveforms of Class E inverter............................................................................ 39
Fig. 3.5 Equivalent circuit of series resonant circuit at the operating frequency.............. 42
Fig. 3.6 Normalized peak switch current and voltage vs. duty cycle. .............................. 44
Fig. 3.7 Power output capability Cp vs Duty cycle Di. ..................................................... 44
Fig. 3.8 Normalized output power vs duty cycle. ............................................................. 45
Fig. 3.9 Efficiency vs Q (Di = 50%) ................................................................................. 51
Fig. 3.10 Efficiency vs Rds_on/R (Di = 50%). .................................................................... 51
Fig. 3.11 ZVS rectifier ...................................................................................................... 53
Fig. 3.12 Main waveforms of rectifier. ............................................................................. 54
Table of Figures
x
Fig. 3.13 ωCrecRLvs rD ...................................................................................................... 55
Fig. 3.14 Equivalent circuit of the rectifier....................................................................... 56
Fig. 3.15 Ri/RL as a function of Dr.................................................................................... 57
Fig. 3.16 Ci/Crec vs Dr. ...................................................................................................... 58
Fig. 3.17 Simplified equivalent gate drive circuit for the square wave drive. .................. 58
Fig. 3.18 Simplified equivalent resonant gate drive circuit .............................................. 60
Fig. 3.19 Class E inverter with self-oscillating gate driver............................................... 61
Fig. 3.20 General Feedback oscillation............................................................................. 61
Fig. 3.21 Phase shift between gate signal and fundamental of drain-source voltage. ...... 62
Fig. 3.22 Block diagram of basic feedback circuit. .......................................................... 63
Fig. 3.23 Simplified feedback circuit................................................................................ 63
Fig. 3.24 Frequency response of VGS/VDS_fund. ................................................................. 64
Fig. 3.25 Feedback oscillating gate driver. ....................................................................... 65
Fig. 3.26 RF DC-DC power converter.............................................................................. 66
Fig. 3.27 Matching network for Ropt > Rpi. ....................................................................... 66
Fig. 3.28 Series combination conversion into parallel combination................................. 67
Fig. 3.29 Matching network for Ropt < Rpi. ....................................................................... 67
Fig. 3.30 The proposed RF DC-DC power converter....................................................... 69
Fig. 3.31 Prototype of RF DC-DC power converter at 250 MHz..................................... 69
Fig. 3.32 Drain-source voltage of SW at 250 MHz operating frequency. ........................ 70
Fig. 3.33 Gate driver signal of SW in the DC-DC converter............................................ 70
Fig. 3.34 Output voltage of the converter. ........................................................................ 71
Fig. 3.35 Rds_on of SW vs gate-source voltage. ................................................................. 72
Fig. 3.36 Efficiency vs Duty cycle for 18Ω ON-resistance. ............................................. 72
Fig. 3.37 Series mounting of a chip capacitor on the circuit board. ................................. 73
Fig. 3.38 Equivalent circuit model of structure above...................................................... 73
Fig. 3.39 Trend-line between power level and frequency of the selected converters....... 74
Fig. 4.1 Multi-disciplinary issues of passive component frequency scaling investigation.
................................................................................................................................... 80
Fig. 4.2 Structure of the integrated planar passive components. ...................................... 84
Fig. 4.3 Simplified thermal model of integrated passive components.............................. 84
Table of Figures
xi
Fig. 4.4 Heat transfer of the simplified thermal model..................................................... 85
Fig. 4.5 Toroidal inductor and its series equivalent circuit............................................... 86
Fig. 4.6 Frequency dependency the complex permeability. ............................................. 87
Fig. 4.7 Complex permeability of 3F4 as a function of frequency. .................................. 88
Fig. 4.8 Various equivalent integrated planar inductors. .................................................. 89
Fig. 4.9 Maximum current density as a function of frequency......................................... 93
Fig. 4.10 Energy density as a function of frequency. ....................................................... 93
Fig. 4.11 Energy density as a function of kg for different frequency................................ 94
Fig. 4.12 Power density as a function of frequency.......................................................... 95
Fig. 4.13 Power density as a function of form factor kg. .................................................. 95
Fig. 4.14 Power conversion efficiency as a function of frequency................................... 96
Fig. 4.15 Power conversion efficiency as a function of form factor kg. ........................... 96
Fig. 4.16 Form factor kw as a function of frequency. ....................................................... 97
Fig. 4.17 A parallel plate capacitor. .................................................................................. 98
Fig. 4.18 relative permittivity as a function of frequency............................................... 100
Fig. 4.19 Integrated planar capacitor with a pair of parallel plates................................. 102
Fig. 4.20 Current distribution along the plates. .............................................................. 102
Fig. 4.21 frequency-dependent relative permittivity of X5U. ........................................ 105
Fig. 4.22 Surface area changes with frequency. ............................................................. 105
Fig. 4.23 Maximum current density through the cap as a function of frequency. .......... 106
Fig. 4.24 Energy density vs. frequency........................................................................... 106
Fig. 4.25 Energy density vs. form factor kw under different frequencies. ...................... 107
Fig. 4.26 power density as a function of frequency along with the power loss density. 108
Fig. 4.27 power density as a function of form factor kw................................................. 108
Fig. 4.28 power conversion efficiency vs frequency. ..................................................... 109
Fig. 4.29 power conversion efficiency as a function of form factor kw.......................... 109
Fig. 4.30 relative permittivity as a function of frequency............................................... 110
Fig. 4.31 surface area of cap as a function of frequency. ............................................... 111
Fig. 4.32 power conversion efficiency vs frequency. ..................................................... 111
Fig. 4.33 power conversion efficiency as a function of form factor kw.......................... 112
Fig. 4.34 Customized planar core and the inductor under study. ................................... 113
Table of Figures
xii
Fig. 4.35 Inductor sample for experiment....................................................................... 113
Fig. 4.36 Impedance characteristics of the inductor. ...................................................... 114
Fig. 4.37 Diagram of the planar inductor and the chamber. ........................................... 115
Fig. 4.38 Experiment setup. ............................................................................................ 118
Fig. 4.39 Measured power loss density as a function of frequency................................ 118
Fig. 4.40 Measured efficiency as a function of frequency.............................................. 119
Fig. 4.41 Measured temperature vs frequency................................................................ 119
Fig. 5.1 Percentage error of loss measurement vs efficiency for given error of voltage and
current. .................................................................................................................... 125
Fig. 5.2 Automated measurement system for core loss. ................................................. 127
Fig. 5.3 Percentage error caused by sampling uncertainty in phase angle versus phase
angle for different N................................................................................................ 127
Fig. 5.4 Types of calorimeter. ......................................................................................... 130
Fig. 5.5 Block diagram of calorimeter illustrated in [141]. ............................................ 132
Fig. 5.6 Block diagram of DCC in [168]. ....................................................................... 133
Fig. 5.7 Flow calorimeter................................................................................................ 134
Fig. 5.8 Schematic of double-jacket calorimeter. ........................................................... 135
Fig. 5.9 Diagram of calorimetric wattmeter designed in [155]....................................... 136
Fig. 5.10 Schematic of calorimeter based on heat flux sensor........................................ 137
Fig. 5.11 Schematic of the proposed calorimeter. .......................................................... 140
Fig. 5.12 Schematic of a TE module............................................................................... 142
Fig. 5.13 Equivalent thermal model of TE module. ....................................................... 143
Fig. 5.14 Complete thermal model of the proposed calorimeter. ................................... 144
Fig. 5.15 Locations of temperature points of the calorimeter in the thermal simulations.
................................................................................................................................. 145
Fig. 5.16 Thermal model of the power leads into the calorimeter. ................................. 147
Fig. 5.17 Temperature distribution for 3 diameters of the wire: 0.5 mm, 1.09 mm, and 1.9
mm when b=1 mm. ................................................................................................. 149
Fig. 5.18 Total heat loss for 3 diameters of wire: 0.5 mm, 1.09 mm, and 1.9 mm......... 149
Fig. 5.19 Heat leakage as a function of length for given diameters: 0.5 mm, 1.09 mm, and
1.9 mm when b = 1 mm. ......................................................................................... 150
Table of Figures
xiii
Fig. 5.20 Prototype of the proposed calorimeter............................................................. 151
Fig. 5.21 Comparison between measured results and theoretical values........................ 152
Fig. 6.1 Power density and efficiency variation with switching frequency.................... 157
List of Tables
xiv
List of Tables
Table 2.1 Summary of multi-megahertz power converters. ............................................. 31
Table 2.2 Physical properties of several semiconductor materials ................................... 35
Table 3.1 Component values of RF DC-DC power converters. ....................................... 68
Table 3.2 Properties of several semiconductor materials ................................................. 77
Table 4.1 Definition of design constraints. ....................................................................... 92
Table 4.2 Dimensions of customized ferrite core ........................................................... 113
Table 4.3 Dimension and properties of the parts in Fig. 4.37......................................... 116
Table 4.4 Measurement results. ...................................................................................... 117
Table 5.1 SOURCE BANDWIDTH VS. SYSTEM BANDWIDTH ............................. 129
Table 5.2 Date of heat flux sensors................................................................................. 141
Table 5.3 Dimensions of the covers................................................................................ 145
Table 5.4 Simulation results of the apparatus................................................................. 146
Table 5.5 Calibration results ........................................................................................... 152
Chapter 1
1
Chapter 1 Introduction
1.1. Background
Two of the most important performance criteria accompanying the application-
driven trends in DC-DC power convertsion today are power density and efficiency.
Higher frequencies and higher levels of integration are necessary to increase power
density. It is predicted that power densities of about 20 W/cm3 to 30 W/cm3 will appear
around 2015 and switching frequencies 5 to 10 times higher than those of today are
necessary to achieve these goals, according to the survey in [6].
The rationale behind pushing power converter switching frequencies has
historically been connected to the desire to reduce the volumes of the electromagnetic
passive components, i.e. transformers, inductors and capacitors. An evolution of modular
telecommunications power conversion units over a ten-year period is shown in Fig. 1.1
[2]. During that period the switching frequencies have gradually risen from the 75-kHz
range to the 1-MHz range, which resulted in substantially reduced physical sizes of
passive components.
In principle, a higher frequency means that the circuit needs to process a
proportionally smaller amount of energy during each cycle for the same amount of power.
The sizes of energy storage and transfer components such as filters, resonant tanks, AC-
decoupling capacitors, snubbers, power transfer transformers, depending to some degree
on the frequency operation, will scale down as the frequency increases. There are several
exceptions to this rule, for instance the presence of DC or low frequency harmonics (i.e. a
boost inductor with a large DC bias), or other limits on dimensional downscaling, such as
voltage isolation thicknesses and safety requirements, (i.e. transformers having HV
windings), turns and turns-ratio trade-offs, required cooling surfaces, mechanical or
packaging limits, among others.
Chapter 1
2
0
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1986 1990 19940
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VolumeFrequency
0
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1986 1990 19940
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VolumeFrequency
Fig. 1.1 Size evolution of modular telecom power conversion units [2].
Today the power densities of DC-DC power converters are being driven higher by
the application demands more than ever. It is unlikely that demands for smaller volumes,
squeezed into lower profiles over smaller circuit real-estate, with better performance,
lower cost and, above all, higher efficiencies will relax anytime soon. Over the past
several decades, raised frequency has been the dominant factor that enabled dramatic
power density increases [1][2]. It is to be expected that these trends towards
miniaturization and higher levels of integration will also maintain steady pressure to keep
this pace of increasing switching frequencies of power converters.
1.2. Limitations of HF/VHF Power Conversion
1.2.1. Introduction
Power converters are moving towards much higher power densities and lower
profile to accommodate the available real-estate, volume and profile requirements and
cost factors while improving or maintaining efficiency. And more recently there has been
more demand for power converters to provide greatly improved transient response to
Volum
e: in3
Frequency: kHz
Chapter 1
3
meet the needs of fast switching loads. All these present more and more stringent
challenges to power electronics engineers, though a series of improvements in technology
with circuits, materials, packaging and switching frequency have already led to
unprecedented gains in power densities, efficiency, transient response and reliability of
power converters over last decades [1].
1.2.2. Monolithic Integration and Converters-On-a-Chip
The continued miniaturization of power converters by pushing switching
frequencies up to multi-MHz (even up to hundreds of MHz) ranges, could eventually lead
to the ultimate realization of on-chip power conversion. The implementation of power
converter-on-chip may be required with functional integration of the devices, controls,
magnetics and capacitors. This represents the key research challenge for integration into
chip scale package, which will result in the actual mixing integration of analog, digital,
and RF or power circuitry on the same packaging structure. There are several advantages
to VHF power conversion as described below:
Firstly, a miniaturized power converter can be easily placed closer to the
load to reduce voltage drops due to interconnect resistances and
inductances. This can also facilitate the power requirements of high
current, rapidly changing load demanded by the microprocessors and new
generation ICs in the future-computer and in telecom applications.
Secondly, higher operation frequency of the monolithic power converter
can improve the transient response, which is especially beneficial to the
voltage regulator module in the microprocessor. Note that today, the push
for higher frequencies is not only from the standpoint of reducing size, but
also for improvements in the transient response. In the VRM application, a
moderate compromise of efficiency seems to be acceptable if transient
response can be improved sufficiently [1].
Chapter 1
4
Thirdly, a higher operation frequency facilitates tighter voltage regulation
required in modern microprocessors and new generation ICs with smaller
filters.
Fourthly, monolithic power converters can easily be distributed all across
the system to supply different loads, as opposed to having external power
converters [4]. This enables another level of single-chip and on-chip
power conversion. Power supplied from a board-mounted module or
regulator module can be further broken down into smaller chip-like
solutions to optimize the power management. For applications such as
mobile phones, this can be important for various voltage levels required
within the chip [4].
Finally, minimization of the areas occupied by fully integrated power
converters is critical in ultimately reducing the production cost.
1.2.3. Modeling and Design
Improvements in converter performances, size, weight and cost along with the
increasing switching frequency have been achieved mainly through the technological
advances and improvements in devices, materials, components and circuit designs,
packaging techniques, and better thermal management. Therefore the efforts to achieve
higher power density while maintaining or improving efficiency by means of pushing
switching frequencies involves coupled multi-disciplinary issues in electrical, thermal,
mechanical, and material properties of the components and packaging. However, it is also
important to note that further advances are becoming more limited since certain
fundamental limits in high frequency power conversion are being reached as the
switching frequency is becoming higher and higher. These fundamental frequency
limitations should be identified and understood for future high-frequency high-efficiency
power conversion technologies.
Chapter 1
5
1.2.4. Semiconductor Device Technologies
Every major increase in frequency would have been impossible without the
advances in power semiconductor device technologies. From the original mercury arc
devices to the present mainly silicon-based devices, the technology has seen a device
volume reduction of 3~4 orders of magnitude – depending somewhat on power level [3].
Semiconductor devices capable of operating up to GHz range are already available thanks
to the continued advancement of the technology. The evolution and future trend of power
semiconductor devices are shown in Fig. 1.2. Accompanying the advances in
semiconductor devices is the simultaneous increase of the switching frequencies [1]. Fig.
1.3 shows the progression of increases in switching frequencies concurrent with evolution
of semiconductor technologies.
1960 1970 1980 1990 2000 2010 2020
IntegratedCircuit 8-Bit Microprocessor Avionics
DEVICEThyristor
GTO
Si Transistor
BipolarTransistor
PowerMOSFET
IGBTMCT
ASD
SICIII-N
IPEMHybrid & electric
Cars
HVACCustom PowerComputer
Wireless
1960 1970 1980 1990 2000 2010 2020
IntegratedCircuit 8-Bit Microprocessor Avionics
DEVICEDEVICEThyristor
GTO
Si Transistor
BipolarTransistor
PowerMOSFET
IGBTMCT
ASD
SICIII-N
IPEMIPEMHybrid & electric
Cars
HVACCustom PowerComputer
Wireless
Fig. 1.2 Evolution of power semiconductor devices.
Chapter 1
6
Fig. 1.3 Frequencies of different power supply technologies used in power conversion vs. time.
Notably, the introduction of the power MOSFETs in the early 1980’s pushed
switching frequencies into hundreds of kHz, then into MHz ranges with the applications
of soft-switching techniques that later took advantage of the parasitic components in the
circuitry [5] by means of functional integration. Modern device technologies are steadily
bringing us closer to radio frequency power conversion at hundreds of MHz, even up to
GHz, with continuous scaling, i.e., shrinking size (gate length), radical improvements in
processing technology and development of new device structures (such as RF MOSFETs
or MESFETs) [29].
Despite the fact that 3~4 orders of magnitude volume reduction have already been
achieved in power semiconductor devices that can operate up to GHz frequencies under
certain conditions, most power converters still operate well below the low megahertz
range today and only an order of magnitude reduction in the overall volume has been
achieved over the past 50 years [3]. This reflects some of the challenges peculiar to
higher frequency power conversion. Clearly, there are limiting factors that seem to inhibit
Chapter 1
7
further increases in switching frequencies. Exactly what they are and where the limit lies
are not well understood, and not so clear.
1.2.5. Circuit Toplogies and Control Strategies for VHF Power Conversion
Load-Range Requirements
Firstly, power converters must operate efficiently over a wide load range from a
variable input voltage. However, existing circuit topologies and control strategies
commonly used at low frequencies become unsuitable when used at such high
frequencies (tens of MHz ~ hundreds of MHz). The operation of conventional PWM DC-
DC power converters becomes limited due to very short transition times. The resonant,
soft-switching techniques are essential for operation in the HF/VHF ranges. Moreover,
appreciable circuit parasitic values must be cleverly exploited to reduce power losses.
This approach is effective for full load conditions, however, the circulating current losses
are typically unacceptable in systems that must operate efficiently over a wide load range.
Output Regulation
Output regulation represents another challenge for VHF frequency operation.
Controlling and regulation methods employed in conventional power converters are no
longer suitable for VHF power converters. In order to ensure efficient operation and
required regulation under wide load range and variable input, a new system structure is
required to overcome these difficulties, such as the structure proposed in [18][19]. It is
comprised of many cellular switching power converters to increase the total power level.
The output regulation can be implemented by adjusting the number of the operating
converter cells according to the variable load and input. In this way every operating cell
in the structure will always operate at an optimum operating point so that maximum
efficiency can be maintained even under light conditions. The control circuitry can be
implemented in digital micro-controllers.
Converter Dynamics
Chapter 1
8
Moreover, converter dynamics and control circuit implementation complexities
escalate at higher switching frequencies. Therefore , innovative circuit topologies and
control circuitries are needed to solve these problems and make power converters operate
efficiently at HF/VHF.
1.2.6. Device Characteristics for future HF/VHF conversion technologies
Power semiconductor devices with high speed and low loss must be developed in
order to achieve a dramatic increase in switching frequency and still allowing acceptable
efficiencies. The frequency-dependent losses of the power devices in the power
converters, including gate drive losses and switching losses, increase as functions of
frequency. Switching loss is associated with switching when both voltage and current are
changing and energy exchanges taking place with drain-source capacitances that are
discharged during every cycle. To reduce this loss, soft-switching techniques are often
employed. For example ZVS (zero-voltage-switching) can virtually eliminate the losses
associated with the drain-to-source capacitance.
Gate drive loss is the result of energy transfer induced by charging and
discharging the gate capacitance of power devices. Gate drive loss increases almost
linearly with switching frequency. This loss often becomes a limiting factor for high
frequency operation. To reduce the loss, the energy can be recovered and reused in
subsequent cycles by employing resonant gate drivers. Thus, the desired characteristics of
future devices for high switching frequency are smaller gate capacitances and resistances.
Conduction loss is proportional to the on-resistance of the devices. Lower on-
resistance of the devices will result in lower conduction losses. However as frequency is
pushed higher, the conventional power devices are approaching their performance
limitations imposed by their material properties. The inherent design trade-off lowering
ON-resistance AND reducing capacitance in a power device, should be optimized for
high speed and high efficiency operation. The power-frequency products of
Chapter 1
9
semiconductor devices also limit the achievable power densities. Thus a future HF/VHF
power conversion technology will require further advances in the device technologies.
Novel structure and wide band-gap semiconductor devices, such as silicon carbide and
gallium nitride devices, as well as novel silicon devices like a super junction FETs, are
under way for breaking through the device limitations [6] to achieve the low gate
capacitances and resistances while maintaining reasonably low on-resistances.
1.2.7. Passive Components
Compared to the performance improvements in the power devices, it is clearly the
inadequate performance of passive components where we must turn our attention to. In
seeking equal or greater benefit by reducing volumes of passive components more
commensurate with those of the power devices, radical increases in operating frequencies
are required. Unfortunately, no major breakthroughs have been achieved in the passive
materials for high frequency operation, and passive components still dominate the
volumes of power converters.
Magnetic components
In the continued efforts to minimize power converter volume, the miniaturization
of energy storage and transfer passive components is usually the most difficult obstacle,
especially for magnetic components. At lower switching frequencies, the passive
components dominate the volumes of power converters. The losses associated with
capacitive components or magnetic components are small for low frequencies. But at
higher frequencies, the losses become the most important consideration. For most ferrite
materials, core losses increase dramatically with frequency in the megahertz range
because the eddy current losses, hysteresis losses and HF copper losses increase with
frequency. The rapid increases of core losses offset the volumetric utilization and inhibit
the increase of switching frequency due to efficiency or thermal constraints. The
permeabilities of ferrites also depend on frequency. As a result, higher switching
frequencies do not always lead to smaller sizes of magnetic components.
Chapter 1
10
However, the trend to smaller magnetic components at higher frequencies has
driven many new research efforts to develop new magnetic materials and fabrication
techniques [7][8] to optimize the high frequency performance. The thin-film or micro-
fabricated magnetic components usually operate below 10 MHz at present. But the
permalloy, ferrite polymer compounds and other materials appear to be promising for
higher frequency operation [9]. Most of the thin-film magnetic materials to date have
been restricted to low power conversion and limited current handling capability. This
suggests that in order to increase current handling capability and power level, magnetic
materials with high resistivity, low coercivity, and high saturation magnetization are
required along with the capability of being deposited in multi-layers. It is interesting to
note that some soft magnetic materials with such features have been addressed in a 3.3- to
1.1-V, 7A dc-dc converter at frequencies beyond 10 MHz [10]. On the other hand, if the
operation frequency of the power converter can be increased sufficiently, the magnetic
components can be implemented without magnetic cores due to low inductance required.
This provides an opportunity to integrate the magnetic components on silicon wafer,
allowing further integration with power devices and control circuitry within a single
silicon die. Silicon-integrated magnetics should achieve reasonable component size and
quality-factor Q with some improved fabrication techniques such as micromachining
techniques proposed in [11][12].
Therefore, in order to achieve dramatic reductions in magnetic components sizes,
either new magnetic materials that do not suffer frequency-dependent loss limitation are
required, or the operating frequencies of power converters must be sufficiently high so
that air-core magnetics can be employed effectively.
Capacitive components
Compared to the semiconductor devices and the magnetics, capacitor technologies
are already suitable for frequencies of 10 MHz and beyond through advanced
manufacturing techniques and new materials. This has primarily been stimulated by the
improvements in ceramic capacitors with high values of capacitance per unit volume,
ultra-low ESL and ESR. Ceramics can potentially take the lead in this regard, particularly
Chapter 1
11
with the recent advent of new materials and multilayer ceramic capacitors, which have
demonstrated production capacitance scalability (> 10 μF). Capacitor development for
the future will focus on smaller grain size of dielectrics to allow thinner dielectric
processing. A new evolving “nanostructure multilayer” capacitor technology mentioned
in [13], getting inorganic high dielectric constant coatings built up by interleaving
electrodes in a multilayer construction, shows a great potential for HF/VHF power
conversion. Typical examples of such materials are ZrTiO3, TiO2 and CaTiO3, which are
0.1 – 10 μm thick and contain 100 – 10000 layers.
Ultimately, the dielectric materials are also limited due to their frequency-
dependent properties, i.e., the dielectric constant, a complex quantity, that changes with
frequency. A higher switching frequency leads to the increased losses including dielectric
loss and Ohmic loss, and derated performance of a capacitor. In order to achieve higher
frequency operation with higher efficiencies, better materials are required to reduce
capacitor dissipation factor by 1/3 to 1/10 and increase capacitor energy and power
densities 2 to 10 times those available today [13].
1.2.8. Packaging and Integration Techniques
High frequency conduction losses [14] and increased contact resistances in
conductors or interconnections, due to the skin effects, proximity effects or the
distributed effects at HF/VHF, become more pronounced, resulting in distorted
performances and reduced efficiency. Radiation leakage and losses become more severe,
thermal noise must be accounted for, and new scaling laws come into effect. Therefore,
higher levels of integration and packaging techniques are critical to minimize these
adverse effects physically. Merely extending conventional packaging could bring about
modest improvements in electromagnetic characteristics, enabling higher frequencies as a
result of better discrete layout, tighter packing of components, smaller parasitic planning
of interconnections, better heat-sinking, lower profile and modular construction. But it is
not enough to achieve the order of magnitude improvement that is really needed [3]. A
more aggressive packaging approach is necessary to develop higher levels of integration.
Chapter 1
12
A number of technologies, such as the Metal Post Parallel Plate Structure (MPIPPS),
Buried Power Technology, Power Overlay Technology, and Flip Chip on Flex
Technology, have been developed to allow lower inductance interconnection structures,
better thermal management and flat integrated packages. To be one of the promising
candidates in this field, it is essential to develop a 3D integrated system approach in the
form of a highly Integrated Power Electronics Modules to incorporate electromagnetic
integration of passive components, non-wire-bond power stage integration, advanced
materials and thermal management – and eventually advanced power semiconductor
devices for the further development of power conversion.
1.2.9. Thermal Management
More advanced and more efficient thermal management will also be required to
effectively remove the heat through smaller surface areas to satisfy the increasing
demand for faster, smaller, lighter, cheaper and more reliable HF/VHF power converters.
The average power densities and heat dissipation rates have increased nearly two-fold in
the last decade. The common cooling techniques such as heat sink and heat pipe
technologies will no longer be capable of meeting the thermal management demands of
future systems. It is obvious that more aggressive thermal management techniques are
required to handle the increased heat loads at this level of integration. There are many
technologies emerging but the most promising in the near future are liquid cooling,
refrigeration and spray cooling. Other technologies include embedded micro-heat pipes,
micro- or mini-channel heat sinks, and micro-machined air-jet array impingement, among
others [20], to name but a few.
1.2.10. Measurement Issues
The measurements of the electrical quantities are becoming more challenging
with the power converters advancing into higher frequencies, higher efficiency, and
smaller volume. For high frequency signal and highly distorted signals, conventional
Chapter 1
13
measurement equipments are no longer suitable due to their limited bandwidth and
dynamic frequency response limitations. The interferences from high dv/dt or di/dt
signals, the intrusion of probes or oscilloscopes into the circuits, among others, all
contribute to aberrations of the measurements. Among these, accurate power loss
measurements are becoming increasingly difficult as frequency and efficiency are being
pushed higher.
In summary, the implementation of HF/VHF power converters is limited by many
coupled multi-disciplinary issues in electrical, mechanical, thermal, material properties.
These fundamental frequency limitations include:
- Circuit topology and control strategy;
- Power semiconductor device technology;
- Energy storage and transfer capabilities of passive components;
- Packaging, interconnection, and integration techniques;
- Thermal management;
- Measurements.
1.3. Objective of this Study
The objective of this thesis is to systematically investigate the fundamental
frequency limitations for HF/VHF power conversion technology. The main aim is to
provide necessary tools for analysis and design towards optimizing power density and
efficiency by maximizing frequency. The necessary guidelines will be provided to
identify the fundamental reasons of the limitations. Since the investigation involves
complex and coupled multi-disciplinary issues coupled in various ways, a good
qualitative insight into the frequency scaling effects and the tradeoffs between different
performance functions is indispensable in understanding the HF/VHF performances in
order to optimize the design. The dissertation is arranged as follows:
Chapter 1
14
1.3.1. Chapter 2: HF/VHF Power Conversion Technology Review and Discussion
In this chapter numerous multi-megahertz switching converters, that were
demonstrated successfully in the literature, are reviewed, trends are recognized and some
conclusions are drawn from these trends. The topologies and power conversion
technologies suitable for high frequency operation (> 10 MHz) are described. The
implementations and main features of these converters are summarized. In regards to the
development of HF/VHF power conversion, the trade-offs between the power level and
the operating frequency are identified and illustrated. A general relation about the power-
frequency limit is derived from the physics of the semiconductor devices, which show
how the ultimate limitations depend on the material properties of the semiconductor
devices in the converters.
1.3.2. Chapter 3: Analysis and Design of RF Class E DC-DC Power Converter
In this chapter the DC-DC power converter derived from Class E power amplifier
is analyzed. The operating principles and designs of this kind of converter are described
in detail. The Class E DC-DC converter is a promising option for operating at radio
frequencies and beyond due to its excellent soft switching characteristics. A prototype
250 MHz power converter is designed and implemented with discrete surface mount
components along with the experiment results. A theoretical guideline is discussed about
how to optimize the semiconductor devices to reduce power losses incurred in the device
and improve the efficiency for HF/VHF power conversion. A criterrion for comparison,
the product of on-resistance and input capacitance of device, is identified in terms of
semiconductor material properties for high frequency and high efficiency power
conversion.
Chapter 1
15
1.3.3. Chapter 4: Fundamental Frequency Limitations of Passive Components for HF/VHF Power Conversion
The frequency scaling limitations of integrated passive components are discussed
in this chapter. As mentioned earlier, increasing frequency has been the primary approach
for reducing passive component volumes. It is also a well known fact that at some
frequency no further advantage is obtained, and yet it is unclear where this ‘optimum’
frequency (or limit) lies. This chapter addresses this question. A methodology is
developed to theoretically analyze the complex multi-disciplinary interplay of design
parameters, to maximize frequency whilst optimizing performance of integrated passive
components for power conversion in terms of efficiency and power density. Among
others the materials, thermal management, packaging and in-circuits functions are
considered. The performances of integrated planar magnetic components and capacitive
components in terms of power density and power conversion efficiency are evaluated as a
function of frequency scaling. The analysis demonstrate how the methodology can be
used to identify the most optimum power conversion frequency for a given set of
specifications, circuit function, selection of materials and packaging technology and
limitations, and thermal constraints.
1.3.4. Chapter 5: Power Loss Measurement Techniques for HF/VHF power conversion Applications
Finally, measurement techniques are discussed for high frequency applications.
Emphasis is placed on power loss measurement techniques, including electrical and
thermal techniques, along with their advantages and disadvantages. The electrical power
loss measurement techniques are limited by their large errors even with highly
sophisticated digital equipment. In theory higher accuracy is possible by measuring loss
directly. Calorimetric methods provide the means for measuring losses directly and
consequently, it is considered to be the most promising method available for accurate
power loss measurement. This method has the advantage of being able to measure the
power losses under normal operating conditions and being independent of electrical
Chapter 1
16
quantities of the device under test. A calorimeter suitable for accurate power loss
measurement is proposed and described in this chapter. The measurement system is based
on the principle of direct measurement of heat flux. It can implement temperature control
and can measure heatsink-mounted components such as active IPEMs, passive IPEMs,
and integrated magnetics. A prototype is built and the calibration result of this
calorimeter demonstrated about 5% error in total losses.
Chapter 2
17
Chapter 2 HF/VHF Power Conversion Technology Review and Discussion
2.1. Introduction
To examine how switching frequencies in power converters are being pushed
higher and higher, some published literature that discuss power converters having
switching frequencies of 10 MHz and beyond are reviewed in this chapter.
Since 1970’s, there have been major efforts from researchers to achieve high
power density and faster transient response of DC-DC converters by increasing switching
frequency. High efficiency and high switching speed are of critical importance to achieve
the design objectives in these high frequency DC-DC power converters. As a result new
techniques and converter topologies have emerged to realize high frequency operation,
such as ZCS and ZVS resonant switching techniques [30], and of RF Class E resonant
converters [31][32]. The availability of devices and new VLSI processes have enabled
DC-DC converters operating beyond 10 MHz [33][34][35]. Efforts to operate these
circuits beyond 10 MHz have been plagued with a number of problems, limiting the
overall conversion efficiency and power density of converters.
Basically, HF/VHF DC-DC power converters can be implemented in two ways.
One is the improvement of conventional PWM converters such as Buck converters, Boost
converters and Flyback converters. The other method is the introduction of new
topologies and architectures such as Class E converters. These two kinds of methods are
described below.
Chapter 2
18
2.2. Resonant switching techniques in conventional converters
One of the fundamental limitations towards increasing the frequency of
conventional PWM power converters is the presense of parasitic elements in the circuit.
There are two ways to deal with this problem. The first is to minimize the parasitic
elements in the circuit. However, it is impossible to reduce the parasitics beyond a
minimum level, e.g. for offline converters [36]. Another approach is to use resonant
switching techniques to employ the parasitics to the circuit’s advantage and include the
parasitics in the circuit design. Popular methods using this technique are zero-voltage
switching (ZVS) and zero-current switching (ZCS). The basic structures of resonant
switch are shown in Fig. 2.1.
(a) Zero-current switching (b) Zero-voltage switching
Fig. 2.1 Basic structures for soft resonant switching
The essence of ZVS is to shape the drain-to-source voltage waveforms of devices
so they become zero prior to turning on. The ZCS technique shapes the device’s current
waveform so that the device is turned off when its current is zero [30]. Thus the resonant
switching techniques allow very low switching losses and permits efficient operation at
increased frequencies. ZCS is somehow limited to the lower megahertz range since this
Chapter 2
19
technique can not solve the problem of switching loss associated with capacitive
discharge at turn-on [30].
There has ever been intensified efforts on resonant converters to operate in the 2 –
20 MHz range in the mid to late 1980’s [1][37]. In [37] Buck and Flyback ZVS quasi-
resonant converters (QRC’s) were presented. The experimental results of Buck ZVS
QRC (Fig. 2.2a) showed switching frequencies from 6.6 MHz at 25 W to 16.7 MHz at
2.5 W and 80% efficiency at full load. However, a high voltage stress in the order of 8
times the input voltage for a 7:1 load range, was applied to MOSFET. The experimental
Flyback ZVS QRC in Fig. 2.2b operated from 3 MHz at 20 W with Vin = 45 V to 13
MHz at 5 W with Vin = 60 V, Vout = 5V. Efficiency of the converter was typically 70%.
(a) Buck ZVS QRC (b) Flyback ZVS QRC
Fig. 2.2 Basic circuit diagram of ZVS QRC in [37].
In summary, the ZVS technique is suitable for very high frequency operation.
However high voltage stress made single-ended ZVS converters unsuitable for wide load
range applications.
2.3. High speed switching devices in conventional Converters
Conventional MOSFET-based converters may operate at frequencies as high as
10 MHz by using novel switching techniques such as ZVS or ZCS. But increasing
operating frequencies above 10 MHz for such converters necessitates new advanced
power semiconductors with high speed and low losses. Incorporation of such new devices
Chapter 2
20
into conventional power converters for high frequency operation has been successfully
demonstrated in the literature as described below.
High speed GaAs vertical field-effect transistors (VFETs) with less than 2ns
switching have been incorporated in 10 MHz, PWM Boost and Buck 5 W power
converters that demonstrated good efficiency (>85%) and very high power densities (500
W/in3) [33]. Benefits of GaAs VFETs over silicon MOSFETs include: 10-to-1
improvement in switching speeds, and reductions in specific resistances and device
capacitances. GaAs VFET lacks the parasitic diode of a MOSFET, reducing reverse
recovery losses. The two drawbacks of the device technology at present are its normally-
on characteristics caused by depletion mode operation and technological immaturity.
In [38] a PWM boost converter with an operating frequency of 10 MHz was
implemented with GaAs’s HBT’s in hybrid form for a portable wireless transmitter to
meet the requirements of smaller size and higher bandwidth. Power efficiency at 1 W
with 74% efficiency was reported in this literature.
Gallium Arsenide (GaAs) MESFET power switches like MESFET and Schottky
barrier rectifiers applied in Buck [39], Boost [40], Cuk [43], Flyback [44] DC-DC
converters have allowed switching frequencies up to 100 MHz, even up to 250 MHz [42].
The primary advantages for using GaAs over silicon are low ON resistance, low voltage,
fast switching speed, and semi-insulating substrate [39]. This mainly comes from
intrinsically higher electron mobility of GaAs (5000 cm2/Vs for GaAs, 600 cm2/Vs for
silicon with 1017 cm-3 doping density) and higher energy bandgap. Since the on-resistance
to input capacitance factor issonCR is inversely proportional to the electron mobility, GaAs
switches are expected to provide much lower power losses than silicon switches [41].
A 40 MHz to 100 MHz step down 10 V to 5 V (8 V) converter using GaAs power
MESFET was demonstrated with an output power of 2.6 Watts and power efficiency of
77% at 40 MHz in [39]. A prototype based on hybrid circuit technology was
implemented on an alumna subtrate with 1 A – 15 V X-band power MESFET, an X-band
Chapter 2
21
MESFET based gate driver, a 110 nH – HF ferrite based very low loss inductor and
various DC decoupling chip capacitors. Experimental results of the converter are shown
in Fig. 2.3. If a MESFET power transistor with 0.5 Ohm ON state resistance instead of 4
Ohm in the prototype was used, more than 85% efficiency could be achieved at 100 MHz.
Fig. 2.3 Experimental results of Buck in [39].
A GaAs-based 5 V/10 V – 2 W Boost converter operated at 100 MHz was
presented in [40] with 69% efficiency with small passive components: a 23 nH planar
inductor (4×4 mm2) and a 47 nF surface mount capacitor (1×2 mm2). The hybrid
technology prototype Boost converter was assembled on a 10 mil Alumina substrate. A
0.7 μm technology 2 A-12 V commercial MESFET, a 150×150 μm 27 V Schottky
rectifier and a gate driver were carefully mounted with very tight interconnection ribbons
in order to avoid parasitic oscillations.
Two principal limitations of high switching frequencies (>20 MHz) DC-DC
converters are: relatively small breakdown voltage of HF switches, and HF losses of
passive components. Novel large gap III-V power devices such as heterojunction bipolar
transistors (HBTs), high electron mobility transistors and the hetrojunction isolated gate
FETs should be investigated for potential use. Concerning passive components,
especially ferrite based inductors, the limitations are related to the limited cut-off
frequency of UHF ferrite materials (generally < 300 MHz). It should be interesting to
Chapter 2
22
investigate RF techniques by using Transmission Line based components like BALUNs
in order to replace conventional inductors and transformers. Also a smart power
monolithic technology, that involves the gate drivers and the power devices, would allow
us to avoid the effect of the parasitic inductances and reduce the size of the circuit
[41][43]. A more compact design should be possible by using MMIC technology.
A simplified comparative theory in [42] highlighted the intrinsic advantages of
GaAs over conventional silicon devices for very high frequency applications. Taking into
account the maturity and reliability, cut-off frequency of higher than 20 GHz, GaAs
MESFET/HEMT devices constitute a real solution for converters operating up to
hundreds of MHz like the modulated power supply RF amplifiers. The feasibility of
ultrahigh frequency DC-DC converters using GaAs power switches opened new
perspectives in the power electronics domain in terms of compact size and speed.
2.4. Monolithically integrated conventional power converters by VLSI
High switching frequency is the key design parameter that enables full integration
of a high efficiency power converter. By evolving to higher switching frequencies, values
of inductors and capacitors are reduced to values that are suitable for integration. Due to
tight area constraints, integrated capacitors and inductors above certain values are not
acceptable for integration. On the other hand, the VLSI process technology allows us to
integrate both active and passive devices of power converters onto the same die. In a
typical nonintegrated converter, significant energy is dissipated by the parasitic
impedances of the interconnects among the nonintegrated devices (inductors, capacitors,
power transistors, and PWM circuitry). An integrated converter on a chip can potentially
lower the parasitic losses as the lengthes of interconnects between different components
are reduced. Additional energy savings can be realized by utilizing advanced deep
submicrometer fabrication technologies with lower parasitic impedances [46][47][48].
Chapter 2
23
Full integration of power converters is challenging because monolithic magnetics
technology can’t provide high quality inductors. Integrated inductors usually have poor
parasitic impedance characteristics: low Q-values and low self-resonant frequencies,
which can degrade efficiency of power converters. Therefore new magnetic materials or
improved fabrication techniques are required to achieve the desirable characteristics.
New integrated microinductor technology using CoZrTa with relatively small parasitic
impedances and higher cut-off frequencies (> 3GHz) has been reported in [52]. Therefore
on-chip integration of active and passive components of power converters permits
switching frequencies higher than typical switching frequencies found in conventional
converters. Examples of on-chip integrated DC-DC power converters are illustrated
below.
The SiGe BiCMOS process is well suited for portable wireless applications due to
its significant advantages: high speed, low noise figure, excellent linearity, and less
dependence of speed upon high field strength and supply voltage. It has been successfully
applied in a DC-DC power converter for wireless applications. A DC-DC converter
design for on-chip integration with a WCDMA power amplifier has been presented in [35]
to increase transmitter efficiency and improve battery life. The synchronous rectifier (SR)
Buck converter was implemented in IBM’s 0.35 μm SiGe BiCMOS 6HP process.
Simulation results show an average efficiency of 78.8% over power amplifier operating
conditions and a peak efficiency of 86%. The converter was optimized for operation at
88.7 MHz. The inductor value (9.1 nH) is small enough to be integrated on-chip, however
the series resistance of on-chip inductors (1 ~ 2 Ω) is too large for power conversion
applications. Therefore output inductor and capacitor are implemented off-chip [35] in
the converter.
Similarly a 100 MHz two-phase interleaved SR Buck converter was implemented
by the use of 0.18 μm SiGe BiCMOS process for wireless applications, but with high
quality integrated passive devices [45]. The inductor quality factor limits the efficiency of
converter. The inductor quality factor is limited by metal line resistivity, capacitive
Chapter 2
24
coupling to the substrate and magnetic coupling to the substrate. The metal line resistance
is lowered by removing the first few internal turns of the spiral inductor, which do not
contribute too much to the total inductance. By use of thick electroplated copper layer
after the 5th layer of Cu metallization and far above the substrate, a high quality factor
inductor was implemented [45].
On-die switching DC-DC converters can be fabricated in existing CMOS (80 nm
– 180 nm) [47] [51] for future microprocessor power delivery. As pointed out in [51],
increasing input voltage to VRM (voltage regulator module), and moving the VRM
closer to the microprocessor by integrating it either in the package or the die itself
alleviates some problems associated with low voltage, high current distribution networks.
In fact, integrating the DC-DC converter onto the same die as a microprocessor can
improve energy efficiency, enhance the quality of voltage regulation, and decrease the
number of I/O pads dedicated for power delivery on the microprocessor die. Furthermore,
reliability of voltage conversion circuitry can be enhanced, area can be reduced, and
overall cost can be decreased by using an integrated circuit technology [46].
Comprehensive circuit models of the parasitic impedances of monolithic
switching DC-DC converters were presented in [47][48] to analyze the frequency
dependent efficiency characteristics of the Buck converter as switching frequency is
increased to permit full integration. An optimum circuit configuration with maximized
efficiency was derived from this model. The effects of scaling the active and passive
devices and the related switching and conduction losses on the total power characteristics
of a buck converter were examined. The independent variables of the proposed model in
[47] are the switching frequency and inductor current ripple. An estimation of efficiency
from the analytical model is within 2.4% of the simulation results at the target design
point. An efficiency of 88.4% at switching frequency of 477 MHz was demonstrated by
simulation for voltage conversion from 1.2 V – 0.9 V volts while supplying 9.5A current.
The area occupied by the converter is 12.6 mm2 assuming an 80 nm CMOS technology.
By including gate voltages and tapering factors of MOSFETs as independent parameters
in the model proposed in [48], estimation of efficiency is now within 0.3% of circuit
Chapter 2
25
simulation. An efficiency of 84.1% at 102 MHz was achieved by simulation for voltage
conversion from 1.8 V to 0.9 V assuming 0.18 μm CMOS technology.
In order to achieve the desirable efficiencies at such high frequencies, MOSFET
power dissipation reduction techniques were applied to improve the efficiency based on
the parasitic circuit models of the monolithic Buck converter (Fig. 2.4) in [47][48]and
[51].
Fig. 2.4 Parasitic impedances and transistor geometric sizes of Buck converter.
Firstly, an optimum MOSFET channel width exists that minimizes the total
MOSFET related power, due to the fact that increasing MOSFET width reduces the
conduction losses while increasing the switching losses.
Secondly, the impact of tapering factor on maximum efficiency is also analyzed
[48]. As shown in Fig. 2.5, at a certain range of tapering factor, dynamic switching losses
dominate the total losses. The efficiency increases with higher tapering factor in the range
dominated by switching losses. After peak efficiency is reached, increasing short-circuit
losses in the power MOSFET gate drivers begin to dominate. Hence, efficiency degrades
Chapter 2
26
with further increasing tapering factor. The optimum tapering factors are 10 and 16 for
the full-swing and low swing circuits, respectively [53].
Fig. 2.5 Maximum efficiency with low-swing (LS) and full-swing (FS) Buck converters vs. tapering
factors.
Another technique to improve the efficiency, involving low swing MOSFET gate
driving, was investigated in [48] [53] to improve the efficiency of a DC-DC converter.
The total power dissipation of the low swing buck converter is reduced by 24.5% as
compared to the full swing maximum efficiency configuration, resulting in 3.9% higher
in efficiency than that of full swing DC-DC converter (Fig. 2.5). Energy recycling drivers
or ZVS switching can also be employed to reduce switching losses, as illustrated in [51].
DC-DC converter efficiency is strongly dependent on the switching frequency, so
that it is clearly a primary design variable in the analysis. The efficiency was analyzed
over some frequency range varying the circuit configuration. The maximum efficiency
circuit configurations determined by the model was simulated, verifying the circuit
operation and performance characteristics. The global maximum efficiency with a full-
swing converter was 84.1% based on a tapering factor of 10. The switching frequency of
maximum efficiency configuration is 102 MHz.
Chapter 2
27
The integrated 4-phase Buck DC-DC converters implemented in a 90 nm CMOS
technology were demonstrated with off-chip air-core inductors in [49] and [50]. At 480
MHz operating frequency the measured efficiency was 72% for a voltage conversion
from 1.8 V – 0.9 V while supplying 0.5 A load current in [49]. The efficiency of 80%-
87% at switching frequency of 100 to 317 MHz was demonstrated in [50] for a voltage
conversion from 1.2-0.9V while supplying 0.3A output current.
2.5. New architecture DC-DC converters derived from Class E power amplifier
This new family of high switching frequency DC-DC converter has emerged
since 1980’s [54][55][56]. The name “Class E” comes from switching mode RF power
amplifier circuits [57][58]. The idea of Class E DC-DC converter was first published by
Gutmann in 1980 [54]. As the switching frequency increases to VHF range, the
conventional converters with square waveforms become limited mainly due to short
transition times and parasitics. On the other hand, the DC-DC converter derived from the
Class E power amplifier provides a promising option for operation at microwave
frequencies due to its excellent soft switching characteristics. The Class E DC-DC
converter uses the same principles as the class E power amplifier. It is based on
sinusoidal waveform operation and the zero voltage switching technique.
The switching-mode Class E power amplifier is employed as the resonant inverter
due to its high efficiency and simplicity. The rectifier should offer high efficient and high
frequency rectification. The underlying principle of Class E operation is to shape the
voltage and current waveforms of the switch so that two waveforms are displaced in time
from each other. Matching networks can be added to provide both the required voltage-
current waveform displacement and the necessary impedance transformation between the
rectifier and inverter. When Class E conditions are met, the power dissipation during the
switching transitions will be minimized. The parasitics of semiconductor device and
passive components can be incorporated into circuit design. Applications of this RF
circuit design principle to high frequency DC-DC power converters have been reported in
Chapter 2
28
[56][59][60][61]. With the advanced semiconductor devices and processing technologies
available now, high-efficiency operation becomes possible at hundreds of MHz.
The experimental results for a 10 MHz 5 W 25 V to 5 V converter constructed
using RF bipolar switch and a Schottky rectifier verified the basic design approach in
1980 [56] and indicated that efficient load and line regulation could be provided with
narrow band frequency control. An efficiency of 68% was obtained and it was predicted
that 75% efficiency could be obtained with better optimization of inductor Q. Later in
1988 a converter prototype operating at 22 MHz was demonstrated (Fig. 2.6). It consisted
of a self-oscillating, ZVS inverter section that fully utilized internal MOSFET
capacitances. Output voltage was regulated by narrow band frequency control,
implemented with reverse biased varactor diodes in the gate circuit. A peak efficiency of
78% was obtained for 50V nominal input and 5V output.
Fig. 2.6 Schematic of DC-DC converter operating at 22 MHz.
In the work reported in [59] a 4.5 GHz DC-DC power converter was investigated,
the highest frequency DC-DC converter reported to date. The converter consisted of a
switching-mode Class E power amplifier and diode rectifiers (Fig. 2.7). The Class E
amplifier was implemented using transmission lines instead of lumped elements. The
output power of the Class E amplifier could be shared by two half-wave rectifiers using a
3-dB hybrid as shown in Fig. 2.7. The two DC outputs could be connected in series or in
parallel, giving more choices for output voltage or current value. The overall efficiency
of 64% was achieved for a 87 Ω load with an output 2.15 V. The output power of the
Class E power amplifier could be coupled through a 10 dB directional coupler to a single
rectifier circuit. A conversion efficiency of 49% across a 135 Ω load was mentioned in
[59]. The fact that the converter was realized without any discrete magnetic components
Chapter 2
29
provided potential for planar, compact and low-profile realization. The approach was
amenable to monolithic integration, which would enable very small overall dimensions.
Fig. 2.7 Layout of 4.5 GHz DC-DC converter.
The Class E DC-DC converter was shown in [60] to be an excellent candidate for
on-chip switching converters because of high efficiency at high switching frequencies. A
200 mW, 800 MHz integrated Class E DC-DC was designed using a 0.6 μm CMOS
process. A 22 nH spiral inductor was designed on the Metal 3 layer. The 50 pF resonant
capacitor was implemented with a pair of parallel poly silicon plates. An integrated
feedback controller with a VCO was used for output voltage regulation. The layout of the
inverter without its choke inductor, synchronous class E rectifier without output low-pass
filter inductor and capacitor, VCO, and delay circuit were designed. It was pointed out in
this paper that a complete integration could be accomplished by using the second
harmonics class E inverter, which didn’t need a larger inductance for a choke coil [62].
Class E DC-DC converter can be implemented using discrete components, as
described in [61]. The experimental evaluation of prototype with cells operating at 100
MHz was demonstrated (Fig. 2.8). Output power ranged from 2.5 W to 6 W, with an
average efficiency greater than 77.5%. An underlying feature of the design approaches
presented in this paper was that the energy conversion and regulation functions were
partitioned in ways that were compatible with the effective implementation of ultra-high
frequency circuit designs and techniques.
Chapter 2
30
Fig. 2.8 Switching DC-DC power converter at 100 MHz.
2.6. Trends of Power Level with Increasing Frequency
Numerous megahertz switching converters have been reviewed in the previous
section. The topologies, techniques for improving efficiency, and implementation
techniques are all described along with their main performance features. The
implementations of high frequency power converters can be basically classified into two
categories in terms of topologies and system architectures:
- Improvements of conventional PWM converters such as Buck -, Boost -,
and Flyback -converters and others through :
• Resonant switching techniques;
• High-speed semiconductors to replace conventional MOSFETS in the
converters;
- New topologies and architectures suitable for high frequency operation
such as Class E DC-DC converters.
In terms of processing technologies, there are four kinds of ways to implement
power converters:
- Discrete implementation;
Chapter 2
31
- Hybrid integration techniques;
- Monolithically integration by VLSI;
- Distributed implementation based on microwave theory.
The selected multi-megahertz converters are listed in Table 2.1.
Table 2.1 Summary of multi-megahertz power converters.
f Power Efficiency Topology Implementation Device/Process Demo/Simulation Dimension/power
density
10 MHz 5W 68% Class E Discrete MOSFET Demo -
10 MHz 10 W 70%-
80%
Buck,
Flyback Discrete MOSFET Demo -
22 MHz 50 W 78% Class E Discrete MOSFET Demo 0.5′′×4.16′′×2.61′′
50-250 MHz 3 W 60%-80% Boost Hybrid MESFET Demo 10 × 20 mm2
63 MHz 1 W ~70% Flyback Discrete HFET Demo -
100 MHz 6 W 77.5% Class E Discrete LDMOSFET Demo -
100 MHz 50 mW - 2-phase Buck Monolithic 0.18μm BiCMOS Simulation -
100-477
MHz - 80%-88% Buck Monolithic 0.18μm/80nm CMOS Simulation 12.6 mm2
100-317
MHz
270
mW 80%-87% 4-phase Buck Integrated 90nm CMOS Demo
1.26 mm2(inductor
not included)
480 MHz 450
mW 72% 4-phase Buck Integrated 90nm CMOS Demo -
800 MHz 200
mW 72% Class E monolithic 0.6 μm CMOS Simulation -
4.5 GHz 50-120
mW 49%-64% Class E Distributed MESFET Demo 14×7×0.05 cm3
The relationship between the power levels and frequencies of the converters
previously described is depicted in Fig. 2.9. And the plot of efficiency vs frequency is
shown in Fig. 2.10. It is clearly shown that there is a trend towards decreased power level
when the switching frequency increases. It seemed reasonable to suppose that there is an
ultimate limit for the trade-off between the power level and the frequency of a converter.
Considering the the components constituting a converter, it is reasonable to conclude that
it is the capabilities of power semiconductor devices in the converter that ultimately
determines its power level. Therefore, the power-frequency limits of the semiconductor
devices should be considered thereafter to identify the trade-off existing between the
power and the frequency.
Chapter 2
32
0
10410310210 f (MHz)
P (W)
100
10
1
0.1
0.01
Fig. 2.9 Power level vs frequency for selected converters.
104f (MHz)
10310210
100%80%
60%
40%
20%0%
104f (MHz)
10310210
100%80%
60%
40%
20%0%
Fig. 2.10 Efficiency vs frequency for selected converters.
The power-frequency product of the power devices should be derived in a manner
that makes it independent of design details. The objective here is to derive a general
relation about the power-frequency limit that show the performance limits independent of
a converter-specific design and demonstrate its use in evaluating future designs and
developments. This is to establish upper bounds on the performance by developing a
highly idealized and simplified device model whose performance is not likely to be
Chapter 2
33
surpassed by that of any attainable design, no matter how optimized or cleverly
conceived.
Firstly, for a semiconductor junction with a doping density N, the maximum
voltage is given by [63]
NqEV bks
2
2
maxε
= (2.1)
where sε : dielectric constant of the semiconductor;
q : the electron charge;
bkE : breakdown electric field.
The maximum current per gate width flowing through the device is given by
sdqNvI =max (2.2)
where d : thickness of the channel;
sv : the saturated drift velocity of an electron.
For practical applications, the maximum applied voltage is usually kept to be
about one-half of maxV to provide an adequate safety margin. This is the same for the
maximum current through the device. So the maximum power per unit gate length is:
1621
21
21 2
maxmaxmaxdvEIVP sbksε
=⋅⋅= (2.3)
The maximum allowable operation frequency is the cut-off frequency Tf of the
device, given by
g
sT L
vfππτ 21
21
== (2.4)
gL : gate length.
Finally the power-frequency product is derived from (2.3) and (2.4) as
2max )(
32 sbkg
sT vE
LdfP
πε
= (2.5)
d/Lg is the form factor of the device, typically in the range of 3~5.
Chapter 2
34
Therefore, the power-frequency product mainly depends on the product of Ebk and
vs, which agrees well with Johnson’s figure of merit [64]. Ebk and vs are the intrinsic
properties of the semiconductor material. So the power-frequency product ultimately
depends on the properties of semiconductor materials in the devices. This relationship
effectively verify the empirical relationship 1−∝ fP for the power-frequency product of
the present Si-based devices [3][108][111].
The simple analysis above is a reasonable explanation for a trade-off between
power level and frequency existing in power converters. For given semiconductor
material, the energy transfer rate per second must decrease with increasing frequency,
eventually limiting the realization of high density power converter through increasing
frequency. Though raised frequency has been the dominant factor that enabled dramatic
power density increases over the past, it doesn’t mean that power density improvement
could be always achieved by pushing the frequency, under the conditions of given
semiconductor materials. The power density would be decreased because of dramatically
reduced power when the frequency is pushed beyond some limiting value, thus defeating
our original objective for improved power density.
The larger power level can be achieved, in principle, by connecting devices in
parallel within the frequency limits of the device, according to Johnson‘s figure of merit
given below. The price paid is the decreased impedance level. In practice, power output
may be limited more by the problems of cost, device uniformity, and circuitry [64].
JFOMπ2
)( 21
sbTm
vEfXP ==
where X is the reactive impedance of device capacitance.
Due to this limitations mainly imposed by the semiconductor materials, it is
necessary to develop other devices materials to achieve higher power and improve power
density at higher frequency. The physical properties of major semiconductor materials are
listed in Table 2.2. The calculated (Ebkvs)2 in the last row is normalized to that of Si.
Chapter 2
35
Table 2.2 Physical properties of several semiconductor materials
Si GaAs 4H SiC 6H SiC GaN
Bandgap EG (eV) 1.1 1.4 3.2 3 3.4
Ebk (105 V/cm) 5.7 6.4 33 30 40
vs (107 cm/s) 1 2 2 2 2.5
μ (cm2/Vs) 1350 8500 610 340 1200
k (W/cm-K) 1.5 0.5 4.5 4.5 2.1
(Ebkvs)2 1 5 134 110 308
It can be seen that GaN and SiC take a tremendous advantage over conventional
semiconductors Si and GaAs for high power and high frequency power conversion due to
their larger breakdown field and higher saturated velocity. High saturation velocity means
this material suitable for high frequency operation, whereas high breakdown field makes
this material suitable for high voltage application. As a result, it is suitable for high power
and high frequency operation. High thermal conductivity gives it extra advantage for high
power applications.
Therefore GaN and SiC demonstrate high potential for the efforts to improve the
power density by pushing frequency. Their distinguished physical properties give them
much higher performance limits, compared with that of silicon-based power devices.
Thus it is expected that research and development on novel materials, novel structures
and packaging of power devices will help to relieve the current power-frequency limits
imposed by silicon and raise the future power-frequency product to a higher level, so that
higher power densities can be achieved in reality by pushing frequency.
Chapter 3
36
Chapter 3 Analysis and Design of RF Class E DC-DC Power Converter
3.1. Introduction
In the previous chapter, many different techniques that have in the past been
employed to achieve high frequency DC-DC power converter were summarized and
described. In this chapter a RF Class E DC-DC power converter, which is suitable for
operation at Very High Frequency (VHF) range, is described and demonstrated. The
converter consists of a high frequency, high efficient Class E inverter, a resonant rectifier
and an optional matching network as shown in Fig. 3.1.
Fig. 3.1 Block diagram of proposed RF DC-DC converter.
The converter can be implemented by using discrete active and passive
components because these components operating in RF ranges are now commercially
available. It is more easily built and flexible in design for the purpose of investigating the
frequency limitations of high frequency power conversion, compared with that of
monolithic converter on a chip.
The operating principle of the circuit is described along with the derivations of the
design equations. Effects of various circuit parameters on the performance of converter
are analyzed in this chapter. The prototype of the converter is implemented based on the
selected discrete components. Parasitic values of circuit board layout are extracted by
Chapter 3
37
Ansoft Q3D. Experimental results are provided with analysis and discussions at the end
of the chapter.
3.2. Analysis of Class E RF DC-DC converter
3.2.1. Operation principle of Class E inverter
The basic circuit of Class E inverter is shown in Fig. 3.2. It is also called a Class
E power amplifier. The inverter meets the so-called Class E switching conditions: both
the switch voltage DSv and its derivate dtdvDS are zero when the switch SW turns on.
The class E inverter consists of a switch SW, a shunt capacitor sC , a series resonant
circuit rr CL − , and a choke inductor RFC. The parasitic output capacitance of SW, choke
parasitic capacitance and stray capacitances are included in sC . The necessary
capacitance can be provided by the overall shunt parasitic capacitance for high operating
frequency.
Vin SWRVGS
RFCCrLr
VDS
Cs
irIin
is ic
Fig. 3.2 Class E inverter.
The series resonant circuit rr CL − is usually not tuned to the operating
frequency f . To achieve zero-voltage switching turn-on of the switch, the operating
frequency is greater than the resonant frequencyrrCL
fπ2
10 = . Thus the resonant
circuit has a net series reactance jX at operating frequency. It can be considered as a
resonant circuit tuned to the operating frequency in series with a net reactance jX (see
Fig. 3.3).
Chapter 3
38
Fig. 3.3 Series resonant circuit.
The loaded quality factor Q is assumed be high (Q≥2.5) so that the sinusoidal
current flows through the series resonant circuit [65][66]. The choke RFC has large
enough inductance so that its ripple current is much lower than the dc component of the
input current. Fig. 3.4 shows the waveforms of the inverter. The difference between input
current, inI , and resonant current, ri ,flows into sC when the switch is open, and through
the switch when it is closed. When the switch turns on, 0)2( =πDSv means no energy
stored in sC , yielding zero turn-on switching losses. When the switch turns on,
0)()(
2 == πωωω
tDS
tdtdv means that the switch current starts from zero.
Chapter 3
39
Fig. 3.4 Waveforms of Class E inverter.
Optimum operation, 0)2( =πDSv and 0)()(
2 == πωωω
tDS
tdtdv , can be achieved
only at optimum load optRR = [65]. If optRR > , the amplitude of ri through the resonant
circuit is lower than that for optimum operation, voltage drop across shunt capacitor
sC decreases, and the switch voltage DSv is greater than zero at turn on. On the other hand,
when optRR < , the switch voltage DSv is less than zero at turn-on. Both cases
( optRR > and optRR < ) result in turn-on switching losses. If an anti-parallel or a series
diode is added to the switch, the switch can automatically turn on at zero voltage
for optRR ≤ .
3.2.2. Circuit Analysis based on ideal operation
The analysis of the circuit is based on the following assumptions:
Chapter 3
40
a) The active devices act as ideal switches whose on-resistance is zero, off-
resistance is infinite, and switching times are zero.
b) The parasitic capacitances of the switches are included in the shunt
capacitances and are independent of the switch voltages.
c) The current through the series resonant circuit is sinusoidal at the operating
frequency.
d) The choke inductance is large enough that current through it is constant.
e) All passive elements in the circuit are ideal.
The analysis is performed in the interval 0≤θ≤2π, where θ=ωt is the angular time.
Based on the assumptions above, the current through the resonant circuit rr CL − is
assumed to be:
)sin( Φ+= θmr Ii (3.1)
where mI is the amplitude and Φ is the initial phase of current ri .
Refer to Fig. 3.2 and Fig. 3.4, and assume ON duty cycle of SW is iD .
⎩⎨⎧
<<<<
πθππθ
2220
:i
i
DOFFDON
SW
According to Fig. 3.2,
)()()( θθθ rincs iIii −=+ (3.2)
During the time interval iDπθ 20 << , the switch is on and 0=ci .
⎩⎨⎧
<<<<Φ+−
=πθππθθ
θ22020)sin(
)(i
imins D
DIIi (3.3)
During the time interval πθπ 22 <<iD , the switch is off and 0=si .
⎩⎨⎧
<<Φ+−<<
=πθπθ
πθθ
22)sin(200
)(imin
ic DII
Di (3.4)
The voltage across the shunt capacitor sC and switch SW is:
⇒= ∫θ
πθθ
ωθ
iD Cs
DS diC
v2
)(1)(
Chapter 3
41
[ ]⎪⎪⎩
⎪⎪⎨
⎧
<<
+Φ−Φ++−
<<
=
πθπ
πθπθω
πθ
θ
22
})2cos()cos()2({1200
)(
i
imiins
i
DS
D
DIDIC
D
v (3.5)
For ZVS operation,
⇒= 0)2( πDSv
)cos()2cos()1(2
Φ−Φ+−
=i
iinm D
DII
ππ
(3.6)
The voltage slope of DSv is:
⇒== = 0)(2πθθ
θξd
dvDS
⇒=⎥⎦
⎤⎢⎣
⎡Φ−Φ+
Φ−−= 0
)cos()2cos()sin()1(21
i
i
s
in
DD
CI
ππ
ωξ
)2sin()1(21)2cos(
ii
i
DDDtg
πππ+−
−=Φ (3.7)
The average voltage across the choke inductor is zero, so the input voltage is
equal to the average of DSv :
⇒= ∫π
θθπ
2
0
)(21 dvV DSin
)sin()tan()sin()cos()1()1(
ii
iii
s
iinin DD
DDDC
DIVππ
πππω Φ+
+−−= (3.8)
Thus the dc input resistance of the inverter is:
)sin()tan()sin()cos()1()1(
ii
iii
s
i
in
indc DD
DDDCD
IVR
πππππ
ω Φ++−−
== (3.9)
Refer to Fig. 3.3, the series resonant circuit can be equivalent to the net reactance
jX at the operating frequency. Due to the sinusoidal current through the series resonant
circuit, the fundamental component of DSv at operating frequency can be represented as
(see Fig. 3.5)
)sin()cos(1_ Φ++Φ+=+= θθ RxRxDS VVvvv
Chapter 3
42
Fig. 3.5 Equivalent circuit of series resonant circuit at the operating frequency.
R is the load resistance of the inverter, which is driven by the sinusoidal current
through the series resonant circuit. The voltage across the R is also given by
)sin()sin()( Φ+=Φ+= θθθ RmR VRIv (3.10)
The amplitude of the fundamental component )(θRv can be also determined by
the following Fourier integral with respect to phase Φ :
⇒Φ+= ∫π
θθθπ
2
0)sin()(1 dvV DSR
mi
iiinR IR
DDDVV ⋅=
−Φ+
−=)1(
)sin()sin(2π
ππ (3.11)
Similarly, the amplitude of )(θxv can be calculated as the following:
⇒Φ+= ∫π
θθθπ
2
0)cos()(1 dvV DSx
]sincos)1()[cos()1(2]2sin)1(2)[cos(2cos)2cos(cos2)1(21 22
iiiii
iiiiiiin
mx
DDDDDDDDDDDV
IXV
πππππππππππ
+−Φ+−−−Φ++Φ+Φ−−−
=⋅=
(3.12)
Until now the output power of the inverter can be derived from equation (3.11) as
the following:
mRinvout IVP21
_ = (3.13)
Substituting (3.6) and (3.11) into the equation above (3.13), then
inininvout IVP =_
100% efficiency is achieved for an ideal inverter.
Chapter 3
43
Using (3.6), (3.8) and (3.11), the following relationship can be derived:
)1()]sin()cos()1()[cos()sin()sin(2
2i
iiiiiis D
DDDDDDRC−
+−++=
ππππφπφππω
(3.14)
Using (3.6), (3.88) and (3.12), the reactance X can be obtained:
)1(2]2sin)1(2)[cos2(2cos)2cos(cos21)1(2
2
22
i
iiiiiis D
DDDDDDXC−
−−Φ+−Φ+Φ+−−=
πππππππω
(3.15)
Assuming the quality factor of the series-tuned circuit is Q, define
RLQ rω
=
ωRQLr =⇒ (3.16)
The net reactance of series resonant circuit is
rr C
LXω
ω 1−= (3.17)
From (3.16) and (3.17)
XQRC
ir −
⋅=11
ω (3.18)
Substituting (3.6) into (3.3), then differentiating (3.3) with respect toθ , the peak
switch current can be obtained:
])sin()sin(
)1(1[max_ Φ+−
−=ii
iinS DD
DIIππ
π (3.19)
When Φ−= πθ23 for iDπθ 2<
If duty cycle Di is low, the peak switch current occurs at iDπθ 2=
])sin()sin()2sin()1(1[max_ Φ+
Φ+−+=
ii
iiinS DD
DDIIππππ (3.20)
In the same way, from (3.5) the peak switch voltage occurs at
])1(2
)2cos()cos(arcsin[2
i
i
DD
−Φ+−Φ
+Φ−=π
ππθ (3.21)
Chapter 3
44
The normalized peak switch current in
SI
I max_ and voltagein
DSV
V max_ versus duty
cycle iD is shown in Fig. 3.6. When 5.0=iD , 862.2max_ =in
SI
I , 56.3max_ =in
DSV
V .
Di
Is_max/Iin
Vs_max/Vin
Fig. 3.6 Normalized peak switch current and voltage vs. duty cycle.
Power output capability of the inverter is defined as:
max_max_
_
SDS
invoutp IV
PC = (3.22)
Therefore power output capability versus duty cycle can be plotted in Fig. 3.7.
Di
Cp
Cp_max=
0.098@D=0.5
Fig. 3.7 Power output capability Cp vs Duty cycle Di.
From (3.13) and (3.11), the output power is obtained as
Chapter 3
45
22
_ ])1(
)sin(sin[2
i
iiininvout D
DDRVP
−Φ+
=π
ππ
The normalized output power 2_in
invout VRP as a function of duty cycle is shown
below (Fig. 3.8).
Di
R⋅Pout_inv/Vin2
Fig. 3.8 Normalized output power vs duty cycle.
The duty cycle of the inverter can in fact be chosen arbitrarily, however, 50%
duty cycle is the common choice, considering the factors below:
a. maximum power output capability is reached at this duty cycle;
b. optimum trade-off of the voltage stress and current stress of the active switch;
c. convenient for practical implementation and easily obtainable duty cycle value.
For the analysis above, assume 5.0=iD and 0=ξ , the following parameters can
then be derived from the equations above:
From (3.7),
π2)tan( −=Φ (3.23)
42)sin(2 +
=Φπ
(3.24)
4)cos(
2 +−=Φ
π
π (3.25)
Therefore, °=Φ 52.147 (3.26)
Chapter 3
46
From (3.9) and (3.14)
RCI
VRsin
indc 8
41 2 +===
ππω
(3.27)
1836.0)4(
82 =
+=
ππω RCs (3.28)
From (3.11) and (3.12),
ininR VVV 074.14
42
=+
=π
(3.29)
ininx VVV 2378.144)4(
2
2
=+
−=
πππ (3.30)
Fundamental component of DSv at operating frequency f is
)43.163sin(639.1)05.4952.147sin(639.1
)cos(2378.1)sin(074.11_
°−=°+°+=
Φ++Φ+=
θθ
θθ
inin
ininDS
VV
VVv (3.31)
From (3.6),2
42 +=
πinm II (3.32)
ininS III 862.2]2
41[2
max_ =+
+=π (3.33)
ininS VVV 56.3)(2max_ =Φ−= ππ (3.34)
From (3.13), the output power is
222
2
2
_ 5768.04
82 ins
ininRinvout VC
RV
RV
RVP πω
π==
+== (3.35)
The output power is proportional to the frequency, the capacitance across the
drain-source of the switch, and the squared input voltage.
From (3.15)
2116.0)4(2
42
2
=+
−=
ππω XCs (3.36)
1525.116
)4( 2
=−
=ππ
RX (3.37)
Therefore, the load network impedance of Class E inverter is
°° =⋅=°+=+= 05.4905.49 28.0526.1)05.491( j
s
j eC
eRjtgRjXRZω
(3.38)
Chapter 3
47
Power output capability is:
098.0max_max_
_ ==SS
invoutp IV
PC (3.39)
3.2.3. Practical considerations
The previous analysis is based on several simplifying assumptions, which are not
always acceptable. Class E inverter significantly depends on the circuit parameters, such
as choke inductance, load quality factor Q, nonzero active device ON resistance, or duty
cycle. It is important to determine the effect of these factors on the circuit performance.
The ideal choke RFC, which has zero DC resistance and infinite reactance at
operating frequency, is assumed in the previous analysis. Class E operation with a finite
(and small) DC feed inductance is possible and sometimes desirable [67][68]. In practice,
a very large inductance value (larger than normally required) for the RFC choke is
inconvenient considering:
1. Size, weight and cost of RFC choke increases with inductance;
2. DC resistance is also large, increasing power losses;
3. Large number of turns may cause high parasitic capacitance.
Therefore a tradeoff in designing RFC is important. Inductance should be as low
as possible, but still large enough to achieve the desired behavior and performance. A
practical recommendation is that the inductance of RFC choke should ensure current
ripple to be less than 10% of input DC current inI [58][65].
⇒+
=<=Δ4
81.0%1021
2πRVI
fLVi in
inin
RLRFC 55>ω (3.40)
The real switch device in the inverter circuit has non-zero ON resistance, resulting
in the switch conduction loss. Some previous papers have addressed the switch losses in
the Class E power amplifier. A simple approximate method was firstly presented by Raab
Chapter 3
48
and Sokal in 1978 to calculate the power losses introduced by the ON resistance ondsR _
for 50% duty cycle [69]. The power loss was then given by
invoutonds
invoutonds
ondssonds
PR
RP
RR
dRiP
__
__
2
2
2
0 _2
_
365.1)4(2
28
)(21
=+
+=
= ∫
ππ
θθπ
π
(3.41)
The conduction losses in each Class E circuit component was derived and
expressed as functions of duty cycle in [73]. The effect of duty cycle on power losses and
the total efficiency was analyzed. However, the waveforms of the amplifier were not
reformulated. Then a new analysis formulation was presented in [74] to analyze the effect
of the ON resistance with a simple reformulation of the drain waveforms. The efficiency
and optimum component values of a lossy Class E amplifier were solved with relatively
simple calculations. The derivation is summarized in the following. However in most
cases (3.41) is used to estimate the ON-resistance power dissipation due to its simplicity.
In the following analysis of 50% duty cycle, the effect of ON resistance of the
switch will be considered.
[ ]⎪⎪⎩
⎪⎪⎨
⎧
<<
+Φ+Φ++−
<<
=
πθπ
θπθω
πθθ
θ
2
}cos)cos()({1
0)(
)( 0_
_
DSmins
ondss
DS vIIC
Ri
v
)sin()( __0_ Φ+== minondssondsDS IIRiRv π
By applying Class E requirements 0)2( =πsi and 0)2( =πDSv ,
⇒= 0)2( πsim
in
II
=Φsin
⇒= 0)2( πDSv2
2cos π+−=Φ
yII
m
in
where ondss RCy _ω=
Therefore, π+
−=Φy
tg2
2
Chapter 3
49
When πθπ 2<< ,
]23sincos)
2([)( πθθπθ
ωθ −+−+−= yy
CIv
s
inDS
When πθ <<0 ,
]cossin)2
(1[)( θθπθ −++= yIi inS
The average value of )(θDSv needs to be equal to the input voltage:
⇒= ∫π
θθπ
2
0
)(21 dvV DSin
)232(2
2yyC
IVs
inin ++= π
πω
The power dissipation caused by the ON resistance can be calculated as:
∫ ⇒=π
θθθπ
2
0_ )()(21 dviP dssonds
)412
41647( 2
22
__ yyyIRP inondsonds ++++=π
ππ
Therefore the output power of the inverter is:
⇒−= ondsininvout PPP __
0)3(
)1644
92()4
3()4
(422
23
32
4
=+−+
++++++++
kky
kkykyky
ππ
πππππππ
where 2__
in
ondsinvout
VRP
k =
It’s interesting to note that the equation doesn’t have positive roots
above 100152.0≈k . Thus the following requirement must be met in order to operate in
the Class E mode [74]:
invout
inonds P
VR_
2
_ 100152.0<
And also from ⇒−= ondsininvout PPP __
)]4
24164
7()232(2
1[)(sin222
_22 yyyRyy
CR onds
s
++++−++Φ=π
ππππω
Chapter 3
50
The amplitude of the voltage across the net reactance X is:
⇒Φ+= ∫π
θθθπ
2
0)cos()(1 dvV DSx
⇒Φ+Φ+Φ
+Φ
=⋅=
]sin2cos4sin2
sin[ yC
IIXV
s
in
mx
πππω
]sin2cos4sin2
sin[sinΦ+Φ+
Φ+Φ
Φ= y
CX
s
πππω
Assume the ESR of resonant inductor rL is Lr , the ESR of resonant capacitor
rC is Cr . The power losses in Lr and Cr are
invoutCL
CLmLC PR
rrrrIP _2 )(
21 +
=+= (3.42)
The power loss in the ESR RFCr of RFC choke is
invoutRFC
RFCmRFCinRFC PR
rrIrIP _22
22
48
44
+=
+==
ππ (3.43)
Considering the effects of ondsR _ , Lr , Cr and RFCr , the efficiency of Class E inverter
is
Rr
Rrr
RR RFCCLonds
inv
48365.11
1
2_
++
+++
=
π
η (3.44)
For a given ondsR _ and ignoring other parasitic resistances, an increase in load
resistance leads to an increase in efficiency. But at the same time, the output power
decreases, as seen from (3.35); RFC choke reactance increases, according to (3.40); the
required shunt susceptance decreases based on (3.28), meaning that maximum frequency
of the circuit is compromised.
If LrQ is the unloaded quality factor of rL and CrQ is the unloaded quality factor
of rC , the ESR of rL rC is
CrLrCrrLr
rCL Q
XQRQQR
QCQLrr −
+=+=+ω
ω 1 (3.45)
Chapter 3
51
The power loss due to the ESR of inductor usually dominates the power loss due
to the ESR of capacitor, so for an optimally operated Class E inverter when ignoring RFCr ,
the efficiency given by (3.44) can be approximated as
Lr
ondsinv
RR
++=
_365.11
1η (3.46)
The relationship between efficiency invη and the load quality factorQ is shown in
Fig. 3.9 for different RR onds _ (assuming unloaded quality factor of inductor 170=LrQ ).
Fig. 3.10 shows the relationship between efficiency and the ratio RR onds _ for different
load quality factor values.
Q
η
Rds_on/R =0.01Rds_on/R =0.01
Rds_on/R=0.1Rds_on/R=0.1
Rds_on/R=0.3Rds_on/R=0.3
Rds_on/R
ηQ =5Q =5
Q=30Q=30
Fig. 3.9 Efficiency vs Q (Di = 50%) Fig. 3.10 Efficiency vs Rds_on/R (Di = 50%).
Lower Q leads to lower power dissipation in the circuit, thus the efficiency is
increased. Efficiency decreases quickly with increasing ON resistance of the switch when
the load is fixed.
A number of excellent Class E papers have been published to characterize the
effects of Q. The analysis method proposed by Raab [72] assumes that the quality factor
Chapter 3
52
Q of the resonant network is high enough that the current through rL and rC is essentially
sinusoidal at the operating frequency. This method gives quite accurate results for 15≥Q .
Kazimierczuk and Puczko [66] provide a class E amplifier analysis at specific values of
Q and D in the form of tabulation, but they didn’t give continuous function design
equations based on their tabular data. As a result, an accurate design is only available at
any chosen tabulated value of Q. Avratoglou and Voulgaris [71] provided an analysis and
numerical solutions as graphs but no tables of computed values and no design equations
fitted to the numerical results. Precise design values cannot be read from the graphs.
Sokal [70] provides accurate design equations fitted to tabulated values in [66] at 50%
duty cycle. The relationship among output power invoutP _ , load R , Q , inV and transistor
saturation voltage satV is least-squares fitted to the data in Table 1 in [66], over the entire
range of Q from 1.789 to infinity, within a deviation of ±0.15% by a second order
polynomial function of Q . These equations are accurate and simple enough for designers
to easily manipulate.
)402444.0451759.0001245.1(576801.0)(2
2
_ QQRVVP satin
invout −−−
= (3.47)
Hence:
)402444.0451759.0001245.1(576801.0)(2
_
2
QQPVVR
invout
satin −−−
= (3.48)
The design equations for sC and rC are given below.
RFCQQRCs 222
6.0)03175.191424.099866.0()4(
8ωππω
+−++
= (3.49)
RFCQQRCr 2
2.0)7879.1
01468.100121.1(104823.011
ωω−
−+
−= (3.50)
Therefore, the choice of Q involves a trade-off among competing evaluation
criteria. Lower Q means wider operating bandwidth, higher harmonic content and lower
power loss in the parasitic resistance of the resonant circuit.
Chapter 3
53
3.2.4. Analysis of rectifier
Fig. 3.11 shows a Class E zero-voltage-switching rectifier which consists of a
diode D3, a shunt capacitor Crec, and a low pass filter Lf-Cf. DC power is delivered to load
RL. The rectifier is driven by a sinusoidal current source ir from the resonant tank in the
inverter. The Crec shapes the voltage across the diode so that diode turns on and off at low
dv/dt, reducing the loss at both transitions. The diode junction capacitance and winding
capacitance of the filter Lf are absorbed into the shunt capacitance Crec. The low pass
filter should ensure the output voltage ripple within acceptable limits.
RLCf
D3
Crec
Lfic_rec
Iout
vDr
+
-
Vout
ir
iDr
Fig. 3.11 ZVS rectifier
For convenience of analysis, assuming the current through Lf constant and equal
to the output current Iout. The input current of the rectifier is:
)sin( Φ+= θmr Ii
The diode has ON duty cycle Dr. The main operating waveforms are shown in Fig.
3.12.
Chapter 3
54
θ=ωt
0 π 2π 3πvDr
iDr
0
0
ir = Imsin(θ+φ)
Fig. 3.12 Main waveforms of rectifier.
The current through the shunt capacitor Crec:
⎩⎨⎧
≤<−−≤<−Φ+
=πθπ
πθθθ
2)1(20)1(20)sin(
)(_r
routmrecc D
DIIi
At Aθθ = , 0_ =recci
m
outA I
I=Φ+⇒ )sin(θ
Φ−=⇒ )sin(m
outA I
Iaθ
When the diode is off, the voltage Drv across the diode is determined by the
following expression:
∫ −−Φ+
Φ+−Φ+==
θ
θθθ
θθθ
ωθθ
ωθ
AA
A
A
rec
outrecc
recDr C
IdiC
v )]()sin(
)cos()cos([)(1)( _
The peak voltage across the diode can be determined by setting
Chapter 3
55
⇒= 0)(θ
θd
dvDr
)](2)(
2[max_ Φ++−Φ+
= AArec
outDr tgC
IV θπθω
when Φ−−= 2Aθπθ
At the instant that the diode turns on, the voltage 0))1(2( =−+ rADr Dv πθ
⇒rr
rA DD
Dtgππ
πθ2sin)1(2
2cos1)(+−
−=Φ+
The average value of the voltage Drv should be equal to the output voltage outV
∫+
=A
A
dvV Drout
θπ
θθθ
π2
)(21 ⇒
⎥⎦
⎤⎢⎣
⎡−−−+
Φ++−
= 22 )1(22cos1)tan(2sin)1(2
2 rrA
rr
rec
outout DDDD
CIV ππ
θππ
πω
⇒ ⎥⎦
⎤⎢⎣
⎡−−−+
Φ++−
= 22 )1(22cos1)tan(2sin)1(2
21
rrA
rrLrec DDDDRC ππ
θππ
πω
LrecRCω as a function of rD is shown below (Fig. 3.13):
Dr
ωCsrRL
Fig. 3.13 ωCrecRLvs rD .
The input power of the rectifier contains only the fundamental component due to
the sinusoidal input current from the inverter. Therefore it is sufficient to determine the
input impedance of the rectifier at the operating frequency. The input impedance of the
rectifier is equivalent to an input resistance iR in series with an input capacitance iC (as
shown in Fig. 3.14). The voltage )(θDrv can be expanded into the Fourier series in such a
Chapter 3
56
way that the sinusoidal component represents the voltage Riv across iR , and the
cosinusoidal component represents the voltage Civ across iC at the frequency f .
The fundamental component of the voltage )(θDrv can be expressed:
)cos()sin()( Φ+−Φ+=+= θθθ CimRimCiRiDr VVvvv
where RimV and CimV are the amplitudes of fundamental components of voltages
Riv and Civ across the equivalent input resistance iR and iC , respectively.
Ci
Ri
-
+Vci
-
+VRi
ir
Fig. 3.14 Equivalent circuit of the rectifier
The RimV is given by
∫+
Φ+=A
A
dvV DrRim
θπ
θθθθ
π2
)sin()(1
The equivalent input resistance iR can also be derived as the following when
neglecting the power losses.
Output power of the rectifier
Loutout RIP 2=
Input power of the rectifier
imrectifierin RIP 2_ 2
1=
rectifierinout PP _= ⇒ LALm
outi RR
IIR 2
2
2
))(sin(22Φ+== θ
The plot ofL
i
RR versus rD is shown in Fig. 3.15
Chapter 3
57
Ri/RL
Dr
Fig. 3.15 Ri/RL as a function of Dr.
Also rectifierinout PP _= ⇒
)sin(21
Φ+=
ARim
out
VV
θ
The CimV is given by using Fourier formula
∫+
Φ+−=A
A
dvV DrCim
θπ
θθθθ
π2
)cos()(1
Hence the input reactance of the rectifier at the operating frequency is given by
m
Cim
ii I
VC
X ==ω
1
Therefore the equivalent input capacitance of the rectifier is
))](2sin()sin()1(2)2)(sin(2sin21
)(2cos4sin412sin)1([11
2 Φ+−Φ+−−Φ+
−Φ+−+−=
ArArrA
Arrrreci
DDD
DDDCC
θπθππθ
θππππ
Fig. 3.16 showsrec
iC
C as a function of rD . rec
iC
C increases from 1 to infinity
when rD increases from 0 to 1.
Chapter 3
58
Dr
Ci/Crec
Fig. 3.16 Ci/Crec vs Dr.
3.2.5. Resonant gate driver of Class E inverter
As the frequency increases, the power dissipation of gate drive becomes more
significant. Because of the miller feedback effect of the gate-drain capacitance and the
non-linearity of the device capacitance with drain-source voltage, the gate charge
required to turn on a device is the best way to correctly predict the gate drive
requirements. Two types of gate driver schemes are examined here: square-wave gate
drive and sinusoidal resonant gate drive. The two driving schemes have different losses
and current requirements for a given peak gate voltage and switching speed. The peak
current requirements of each system are also different [75].
In the case of square-wave gate drive (Fig. 3.17), the energy stored in the gate
capacitance during the charging process is determined as follows:
ggsgate QVE 21=
Vg
Rd Rg
CissIg
Fig. 3.17 Simplified equivalent gate drive circuit for the square wave drive.
Chapter 3
59
The loss per switching cycle is two times gateE , and given by
sggsg fQVP =
The time ont that charges the gate capacitance to gsV is determined by the time
constant τ of the gate drive path. Typically, it takes a total time equal to τ4 to fully
charge a capacitor up to gsV .
issdgon CRRt )(44 +== τ
The peak current in the gate drive is given by
gd
gspeakg RR
VI
+=_
Thus the power requirement for the square-wave gate drive is independent of the
switching speed, and the switching speed is ultimately limited by the gate resistance.
Thus there is an intrinsic limit to how fast the gate can be charged, which becomes a
factor as the frequency of operation increases [75].
In the case of sinusoidal resonant gate driver (Fig. 3.18), the input voltage is
sinusoidal and the current is also sinusoidal if ignoring the non-linearity of the gate
capacitance. Assuming that the required gate charge is gQ and the sinusoidal gate drive
signal has a frequency sf , then the peak current needed to charge the gate from zero to
gsV during ont is:
)sin()cos(0
ons
sgt
s
gg t
Q
dtt
QI
on ωω
ω==
∫
The peak voltage capability of the gates of the MOSFET will then clearly limit
how fast one can switch the device with a resonant sinusoidal gate drive. The peak
voltage across the gate of the device is given by
)sin(_ons
gspeakgs t
VV
ω=
Chapter 3
60
Because the gate capacitance resonates with the resonant inductor dL , the reactive
impedance of the gate circuit is considered negligible. Thus the required input voltage is
equal to
)( gdgg RRIV +=
and the power dissipation is:
)(21 2
gdgg RRIP +=
Rd Rg
CissIg
Ld
Vg
Fig. 3.18 Simplified equivalent resonant gate drive circuit
In contrast to the square-wave gate drive, the sinusoidal resonant gate drive is not
limited in switching speed by the gate resistance, yet the power requirement is
proportional to the resistances. By increasing gV to increase the peak current gI , the time
it takes to reach a certain gate voltage can be reduced. The power loss of the gate drive
can be reduced by reducing the drive resistance. Because in a resonant configuration, the
energy stored in the gate gets stored for a half cycle in the resonant inductor and is
recovered during the next half cycle. But with square-wave switching, the energy is
always resistively dissipated.
In general the square-wave gate drive has more severe requirements than the
resonant gate drive. The gate drive devices must be very fast and be capable of sourcing
or sinking large currents. For example, to charge a 2000 pF capacitor in 10 ns to 10 V,
total gate drive resistance must be equal to 1.25 Ω, the peak current is 8 A. For the
sinusoidal gate drive, the peak gate current increases with frequency. The maximum
current would occur at the highest operating frequency. For a given switching time, the
highest operating frequency is when the switching time is a quarter of the switching
period. Otherwise, the device never reaches either the fully on or the fully off condition.
Thus the maximum frequency given a 10 ns switching time is 25 MHz. Under this worst
case, the peak current is 3.14 A, less than that of the square-wave gate drive. Also the
Chapter 3
61
lead inductance and leakage inductance can be absorbed into the resonant inductor Ld, but
they have to be minimized for the square-wave drive [75].
Therefore the sinusoidal resonant gate driver is desirable to drive the switch in the
Class E inverter due to the reduced losses and less severe requirements compared with
square-wave gate driver. A self-oscillating resonant gate driver can be employed as
described in [61][76][77][78][79]. The Class E inverter with a self-oscillating gate driver
is shown in Fig. 3.19.
Fig. 3.19 Class E inverter with self-oscillating gate driver.
The design of feedback gate driver should satisfy the oscillation requirement at
the desired operation frequency, i.e., 1)()( =⋅ ffA β as shown in Fig. 3.20. Specific
component values in the feedback circuitry are needed for operation at a desired
frequency and to obtain the required phase shift between the input and output of the
feedback network. The drain-source voltage DSv is employed as the feedback signal. By
properly shifting the fundamental component of the switch voltage DSv , a sinusoidal
gating signal is generated at the gate terminal to sustain the oscillation at the desired
frequency.
Fig. 3.20 General Feedback oscillation.
Chapter 3
62
By referring to the operating waveforms of idealized Class E inverter shown in
Fig. 3.21, the phase difference between the fundamental component of DSv and the gate
drive signal gsv is 163.4°. The fundamental component fundDSv _ is already derived as
shown in (3.31).
)43.163sin(639.1)05.4952.147sin(639.1
)cos(2378.1)sin(074.1)(_
°−=°+°+=
Φ++Φ+=
tVtV
tVtVtv
inin
ininfundDS
ωω
ωωω
0-π π 3π2πθ=ωt
Vt
vGS
vDS
vDS_fund
ir
163.4°
Fig. 3.21 Phase shift between gate signal and fundamental of drain-source voltage.
The sinusoidal gate driver signal can be expressed as follows:
tVVtv mtGS ωω sin)( +=
tV is the bias voltage applied to the gate, equal to the threshold voltage of the
switch and keeping the duty cycle of the inverter at 50%. The basic feedback circuit can
be implemented as in Fig. 3.22 to achieve the required phase shift. The amplitude of
Chapter 3
63
fundamental component of DSv is also attenuated to a value that ensures proper gate drive
and is below the gate breakdown voltage ( max_GSV ). The input impedance of feedback
circuit at DSv should be large enough to ensure that the operation of inverter is not
significantly affected. Therefore a capacitor with small capacitance value is chosen for
3X element in Fig. 3.22. Whether 2X is an inductor or a capacitor depends on the other
parameters in the feedback network and requirement to satisfy the oscillation.
Fig. 3.22 Block diagram of basic feedback circuit.
Therefore a simplified feedback is proposed as shown in Fig. 3.23. The transfer
function of the feedback circuit is given below. Element 2X in Fig. 3.22 needs to be an
inductor to meet the phase and amplitude requirement based on the circuit parameters.
The frequency response of the transfer functionfundDS
GSV
V_
is shown in Fig. 3.24. By
properly adjusting the component values, the required amplitude and phase at the desired
operating frequency can be obtained. The required phase 163.4° is obtained at 250 MHz
as shown in Fig. 3.24. Resistor 2R can be properly adjusted to set the magnitude and the
precise frequency of oscillation. The function of 1L and 1R is to damp the second
resonance apparent in the transfer function [61].
Fig. 3.23 Simplified feedback circuit.
Chapter 3
64
f (Hz)
Amplitude (dB) Phase (°)
f (Hz)
Amplitude (dB) Phase (°)
)(/)( tvtv DSGS ωω
Fig. 3.24 Frequency response of VGS/VDS_fund.
°−∠=
−+
−−+
+
=
4.16364.1
1
2
2
2
2212212
_
m
in
g
gg
g
gg
GS
fundDS
VV
CL
CR
RLj
CL
CCLL
CLL
CL
VV ω
ωωω
A simple control signal which starts and stops the operation of the inverter can be
introduced as in [61] (Fig. 3.25). When control signal turns on the switch in the feedback
circuit, the inverter stops operation due to low gate driving signal GSv ; When the switch in
the feedback circuit is off, bias voltage biasV charges biasC through 2R . When the voltage
GSv exceeds the threshold voltage of the switch in the inverter, oscillation starts through
the feedback network and keeps normal operation of the Class E inverter. Thus a control
signal can be used to activate or terminate the inverter operation. During
operation biasC remains biased close to the threshold voltage of the switch in the inverter,
keeping the duty cycle near 50%. Therefore, the voltage GSv is a DC voltage
superimposed with a sinusoidal voltage generated through the feedback network, which is
exactly the desirable waveform as shown in Fig. 3.21. biasC should be chosen for minimal
impact on the feedback circuit.
Chapter 3
65
Fig. 3.25 Feedback oscillating gate driver.
3.2.6. Discussion of matching network between the inverter and rectifier
Now the complete DC-DC power converter derived from Class E power amplifier
can be shown in Fig. 3.26. As stated in 3.2.1, in order to minimize the switching losses in
the Class E inverter, the equivalent load of the inverter should satisfy the optimum load
condition optRR = or at least optRR < to achieve zero-voltage turning-on in the switch. In
many situations, the load of the inverter is different from the required optimum load.
Therefore a matching network is required between the inverter and the rectifier to provide
the impedance transformation.
There are several methods to design the matching networks [26][80]. At low
frequencies (HF and VHF), the impedance matching network is usually achieved with
lumped element circuits, usually if the circuit size is much smaller than the wavelength
(10λ
<l ). Distributed components are often used at higher frequencies where the
component or circuit size is comparable with wavelength.
The rectifier can be equivalent to iR in series with iC at the operating frequency as
previously stated in Analysis of rectifier. This means that the impedances to be matched
Chapter 3
66
have reactive components. As a general rule, the reactive component of the load
impedance must be compensated by a convenient reactance seen at the input of the
matching network, so the transformed impedance is a purely resistive load.
Fig. 3.26 RF DC-DC power converter.
When the required optimum load optR of the inverter is larger than equivalent
resistance iR of the rectifier, the matching network shown in Fig. 3.27 can be employed.
Fig. 3.27 Matching network for Ropt > Rpi.
The design equations are:
ii
optim CR
RRL 2
111ωω
+−=
opt
pi
opt
m R
RR
C
11
−
=ω
Chapter 3
67
If iopt RR < , firstly the series iR - iC is converted to a parallel resistance-
capacitance combination as shown in Fig. 3.28. The following relations can be obtained:
Fig. 3.28 Series combination conversion into parallel combination.
])1(1[ 2
iiipi RC
RRω
+=
2)(1 ii
ipi RC
CCω+
=
Then the parallel impedance can be converted into the optimum load optR by the L
matching network as shown in Fig. 3.29.
Fig. 3.29 Matching network for Ropt < Rpi.
The design equations are given by
11−=
opt
pioptm R
RRL
ω
pipi
opt
pi
m CR
RR
C −
−
=
11ω
The two-reactance matching network above is the simplest among the various
matching techniques. However it has its own limitations in some cases such as: no
Chapter 3
68
solution for some combinations of matched impedance; impractical values obtained (too
large or too small values of capacitors and inductors); no design flexibility. In such
situations the three-reactance matching networks can be used to realize the impedance
transformation. Usually one of the impedance matching circuits can meet the design
requirements with practical component values. Four-reactance matching networks allow
exact impedance matching at two distinct frequencies and are appropriate for broadband
impedance matching. When the operating frequency is sufficiently high (e.g. > 1GHz),
the use of transmission-line sections as matching network becomes practical due to the
short lengths required.
3.2.7. Experimental results and discussion
The implementation of the converter is referred to Appendix I. For the given
specifications below: f =250 MHz, LR =20 Ω, outV =4.5 V, inV =10 V, the component
values of the circuit are listed in Table 3.1 (refer to Fig. 3.30).
Table 3.1 Component values of RF DC-DC power converters.
Component Value Part number
RFC 120nH Coilcraft:1812SMS-R12
Lr 5nH Coilcraft: A02T
L1 5nH Coilcraft: A02T
L2 5nH Coilcraft: A02T
Lf 120nH Coilcraft:1812SMS-R12
Cbias 1nF ×2 ATC100B102
Cr 24pF×2 ATC100B240
Cf 10 nF AQ125C103
C 0.5pF AQ12EA0R5
R1 200 Ω Standard SMD
R2 4.64 k Ω Standard SMD
SW L8711P
Dr SL02
Chapter 3
69
Fig. 3.30 The proposed RF DC-DC power converter.
The prototype is shown in Fig. 3.31. The dimension of the prototype is L×W×H =
3×2×0.4 (cm).
Fig. 3.31 Prototype of RF DC-DC power converter at 250 MHz.
When the input voltage is 10 V and load is 20 Ω, the measured drain-source
voltage of the switch SW is shown in Fig. 3.32. The corresponding gate driver signal is
measured as shown in Fig. 3.33, the output voltage is shown in Fig. 3.34.
Chapter 3
70
VDS
250MHz
20V
2.7V
Fig. 3.32 Drain-source voltage of SW at 250 MHz operating frequency.
VGS 5.45V
-1.1V
Fig. 3.33 Gate driver signal of SW in the DC-DC converter.
Chapter 3
71
Vout = 4.3 V
Fig. 3.34 Output voltage of the converter.
The switching frequency, 250 MHz, is significantly higher than those found in
conventional DC-DC converters. This is the highest switching frequency implemented by
discrete surface-mounted components. The output voltage across the load 20 Ohm is 4.28
V for 10 V, 0.2 A input. Only 46% efficiency is obtained for this prototype. By
investigating the temperature distribution of the circuit board, the hottest part is located at
the SW which dissipates most of the power. Based on the circuit shown in Fig. 3.35 (a) to
test the ON-resistance of the LDMOS L8711P employed in the prototype, the
relationship between ON-resistance and gate voltage is obtained in Fig. 3.35 (b). The bias
voltage of the self-oscillating gate driver is set at biasV = 2.6V to achieve 50% duty cycle.
The ON-resistance of the SW corresponding to the bias voltage is about 18 Ω from Fig.
3.35 (b). ON-resistance of the switch can be reduced by increasing the bias voltage, but
duty cycle is reduced at the same time, which results in lower efficiency and lower output
power (Fig. 3.36). Therefore a better power device with lower ON-resistance should be
chosen to improve the efficiency. It is expected that the efficiency could be increased up
to around 70%.
Chapter 3
72
2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4
0
2468
10
1214161820
Vgs (V)
Rds
_on
( Ω)
(a) (b)
Fig. 3.35 Rds_on of SW vs gate-source voltage.
Fig. 3.36 Efficiency vs Duty cycle for 18Ω ON-resistance.
Another problem exists with the discrete passive components and interconnects in
the circuit [83][92][93[94][95]. In reality, the passive components, especially the
component in the resonant circuit, are not lumped. They are distributed along the
transmission line on which is placed. The physical size of the passive components can
result in significant errors in estimating the values of components when they are used at
radio frequencies. The interconnects (or traces) between the components are in fact
microstrip transmission lines. Thus all these effects contribute to the deviation of the
designed circuit from the optimum operation condition. Take for example a look at the
chip capacitor mounted as shown in Fig. 3.37. The copper traces on each side of the
Chapter 3
73
capacitor act like a piece of microstrip line having characteristic impedance 0Z . The
capacitor can be considered as a transmission line section (characteristic impedance CZ0 )
along the vertical height h . The actual capacitive part lies in the middle of the structure
shown in Fig. 3.37, which can also be represented by a transmission line model at RF
frequencies. The equivalent circuit model for this configuration is shown in Fig. 3.38.
This circuit model can be incorporated to analyze its effects on the performance of the
converter. There are various configurations for the passive components in RF power
converter. Each configuration and mechanical orientation has different parasitic
parameters, which should be individually analyzed.
h
w
d
εr
Fig. 3.37 Series mounting of a chip capacitor on the circuit board.
Fig. 3.38 Equivalent circuit model of structure above.
In order to improve the efficiency of RF DC-DC converter, it is important to
employ a better LDMOS with lower ON-resistance in the future, which will significantly
increase the efficiency. By operating at lower switching frequency, the efficiency of the
power converter can be increased through reduced switching losses and reduced
Chapter 3
74
distribution effects of the interconnects and passive components. More complete and
complicated analysis of the converter would be required to consider the practical or
nonlinear features of components in the circuit to obtain more desirable performance. For
example, the nonlinear shunt capacitance in the Class E inverter should be included in the
design procedure [96][97][98][99] to obtain optimum component values.
In summary, a 250 MHz, 2 W RF DC-DC power converter based on Class E
inverter was demonstrated with discrete components in this chapter, with a power density
about 14 W/in3 for dimension L×W×H = 3×2×0.4 (cm). The relationship between the
power level and the frequency of this converter follows the trend limited by the power-
frequency product, as illustrated in Fig. 3.39.
10410310210 f (MHz)
P (W)
100
10
1
0.1
0.01
(250 MHz, 2 W)
Fig. 3.39 Trend-line between power level and frequency of the selected converters.
The power device in the converter plays an important role in determining the
overall efficiency. To minimize the power losses in the semiconductor devices, there
have been concerted efforts to reduce the ON-resistance of the device. At present, several
MOSFET devices achieve mΩ values of ON-resistances, but they are limited to low
frequency applications. However for HF/VHF applications, it is necessary to not only
Chapter 3
75
reduce the ON-resistance but the device capacitance as well for higher efficiency. ON-
resistance can be reduced by increasing the device die area, but leading to a
corresponding increase in the input capacitance of the device. For power devices, the
conduction losses are directly proportional to ON-resistance. The switching power losses
depend on the transition times which are proportional to the input capacitance of the
device. Therefore, the efficiency of a power device may be represented by ON-resistance
Ron and input capacitance Cin.
The total power loss in a power device is comprised of conduction losses and
switching losses. Assuming the switching losses are mainly due to the charging and
discharging of the input capacitance in a power device, then the total power loss is given
by
fVCRIP Ginonrmsdis22 +=
ON-resistance and input capacitance can be represented by their specific on-
resistance and specific capacitance, respectively, as [100]
AR
R sponon
,= , and ACC spinin ⋅= , ,
Both sponR , and spinC , are determined by the material properties and design rules of
the device. So
fVACA
RIP Gspin
sponrmsdis ⋅⋅⋅+= 2
,,2
The minimum power loss occurs when the conduction loss is equal to the
switching loss. The minimum value of power loss is
sponsponGrmsdis CfRVIP ,,min, 2=
at a device area given by
fCRR
VI
fCR
VIA
spinsponspon
G
rms
spin
spon
G
rms 111
,,,
,
, ==
A conclusion can be made from equation above that in order to reduce power loss
and improve the efficiency, it is necessary to minimize the product of sponR , and spinC , . For
Chapter 3
76
a given semiconductor material, sponR , and spinC , are also given. So the minimum power
loss increases with increasing frequency f and gate drive voltage VG. The optimum die
area decreases with increasing frequency and gate drive voltage. On the other hand, when
the switching frequency and gate drive voltage are given, the smaller the product of
sponR , and spinC , is, the less the power loss is and the larger the die area is. Therefore, the
best semiconductors for high frequency power conversion should exhibit small product of
sponR , and spinC , .
The product of sponR , and spinC , may be regarded as a criterion to evaluate the
efficiency of a power device. In fact sponR , and spinC , can be expressed in terms of the
material properties [100].
3
2
,4
bks
Bspon E
VRμε
= ,BG
bksspin VV
EC2,
ε=
where VB is breakdown voltage, εs is the dielectric constant, μ is the carrier
mobility, Ebk is the breakdown field. Then
Gbk
Bspinspon VE
VCR 2
5.1
,,2
μ=
2
5.15.12
min,8
bk
BGrmsdis E
fVVIPμ
=
45.1
5.22
min8
bkGs
Brms
EVfVIAμε
=
It can be seen that the product of sponR , and spinC , is inversely proportional to the
product of μ and Ebk2. The power loss will increase with increasing frequency, but
decrease with the increasing product of μ and Ebk2. Therefore in terms of materials, the
best semiconductor devices should exhibit a large breakdown electric field and a large
mobility, which leads to reduced power loss and die area.
Chapter 3
77
In Table 3.2, the products of μ and Ebk2 normalized to Si of several semiconductor
materials are listed. Again GaAs, SiC and GaN power devices demonstrate less power
losses than Si devices due to their better material properties. Among these semiconductor
materials, the distinguished physical properties of GaN again give GaN-based power
conversion technology extremely high potential for HF/VHF power conversion
applications.
Table 3.2 Properties of several semiconductor materials
Si GaAs 4H SiC 6H SiC GaN
Bandgap EG (eV) 1.1 1.4 3.2 3 3.4
Ebk (105 V/cm) 5.7 6.4 33 30 40
vs (107 cm/s) 1 2 2 2 2.5
μ (cm2/Vs) 1350 8500 610 340 1200
k (W/cm-K) 1.5 0.5 4.5 4.5 2.1
(Ebkvs)2 1 5 134 110 308
μEbk2 1 8 15 7 44
Combined with the power-frequency limit described previously, it is clear that the
first fundamental frequency limitations of HF/VHF power conversion ultimately depend
on the material properties of the semiconductors employed in the power converters. The
semiconductor materials with higher breakdown field, higher mobility and higher drift
velocity are desirable for high efficiency, high power and high frequency power
conversion. When the semiconductor material is given, the power-frequency product, and
the product of specific ON-resistance and specific device capacitance are given. When
ON-resistance is lowered, input capacitance of the device becomes larger, which means
that device should operate at a lower switching frequency for keeping the efficiency but
larger output power is possible. Operating at lower switching frequency, on the other
hand, means reduced switching losses, and reduced parasitic effect and distributed effects
of interconnects among the components. Therefore there are optimum power density and
efficiency existing for some frequency range, beyond which the degraded power density
and efficiency will occur. Consequently, it is necessary to develop devices from other
materials in the future in order to maximize the power density and efficiency by pushing
frequency.
Chapter 4
78
Chapter 4 Fundamental Frequency Limitations of Passive Components for HF/VHF Power
Conversion
4.1. Background
Over the past several decades the volume reduction in power converters can
chiefly be attributed to increases in switching frequency. In keeping this trend towards
miniaturization and higher levels of integration to improve the power densities of power
converters (with present dielectric and magnetic materials), higher switching frequencies
will be required while maintaining or improving the efficiency. In theory, an increased
frequency of operation reduces the required amount of pulsed energy storage per cycle,
thus reducing the volume occupied by the dominating magnetic and electric energy
storage elements in power converters. At the same time it is very important to maintain a
high efficiency when raising the switching frequency, without exceeding permissible
temperature rises as the volume or cooling areas decrease.
Improvements in converter performance, size, weight and cost along with the
increasing switching frequency have been achieved mainly through the technological
advances and improvements in devices, materials, components and circuit designs,
packaging techniques, and better thermal management. Therefore efforts to achieve
higher power density while maintaining or improving efficiency by means of pushing
switching frequencies involves coupled multi-disciplinary issues in electrical, thermal,
mechanical, and material properties of the components and packaging [106][107].
Semiconductor device technology has been one of the major enablers for pushing
switching frequencies. Device size has been reduced to a level where it is no longer the
primary determining factor of packaging volume of a converter [3] at present. The
Chapter 4
79
switching losses in the semiconductor devices have also been on a steady decline with the
improvements in device technology, device types, driving and novel circuit techniques.
Clearly devices don’t impose the fundamental limitations inhibiting advances in power
conversion technologies at the present stage, though there are still some limitations to
future development, such as the power-frequency limits and power loss limitations with
increasing frequency that were described in previous chapters.
Compared to the 3~4 orders of magnitude volume reduction and performance
improvements in the power device, it is clearly the inadequate performance of passive
components where we must turn our attention to. In seeking equal or greater benefit by
reducing volumes of passive components more commensurate with those of the power
devices, radical increases in switching frequency are required with today’s materials.
Unfortunately, no major breakthroughs have been achieved in the passive materials for
high frequency operation and passive components still dominate the volumes of power
converters. The dielectric materials in the capacitive components and the magnetic
materials in the magnetic components are frequency-dependent and produce non-linear
energy storage and power dissipation as a function of frequency. It is then also necessary
to investigate the effects of these materials on power conversion performance of power
converter as the switching frequency increases. At the same time developments and
advances in new and improved magnetic and dielectric materials are necessary.
To keep up with the steps brought about by pushing switching frequency,
improvements in packaging, thermal management, integration, EM characteristics,
control and circuitry are all necessary. As the applications drivers continue to raise
demands for reduced profile and increased power density there is also a tendency towards
higher levels of integration and a tendency to push for higher frequencies. Yet, a three-
dimensionally integrated power electronics technology must also be developed to address
major issues and improve the characteristics of high frequency power converters. These
technologies promise great potential in lowering interconnections impedances, improving
thermal management and reducing profile [3][106][107][112]][113]. The technologies
being developed include planar metallization to allow 3D integration of power devices
Chapter 4
80
and control functions, the integration of passive components to increase power density,
and advanced cooling strategies, as these dominate the volumes of power converters.
Given this background it is essential to explore the frequency scaling effects of
integrated passive components for high frequency power conversion [101]-[105]. A
methodology is developed to theoretically analyze and maximize frequency and
performance of passive components for power conversion in terms of efficiency and
power density, considering materials, thermal management, packaging and in-circuits
functions among others. This is also an attempt to answer the question “what is the
optimum power conversion frequency for a particular integrated passive component of a
certain technology in my circuit, given all the specifications and the design freedom that I
have?”
Apparently the investigation of frequency scaling effects in integrated passive
components involves complex and coupled multi-disciplinary issues (see Fig. 4.1).
Successfully addressing this issue will help to identify the tradeoffs between different
performance functions and optimize the design.
Passive Component Frequency
Scaling
Losses
EM Packaging
In-Circuit Function
Materials Properties
Thermal Management
Passive Component Frequency
Scaling
Losses
EM Packaging
In-Circuit Function
Materials Properties
Thermal Management
Fig. 4.1 Multi-disciplinary issues of passive component frequency scaling investigation.
Chapter 4
81
4.2. Setting up the model
Definitions of parameters
Analyzing the effects of frequency scaling on passive components is a complex
multi-disciplinary task, involving many issues such as packaging, materials properties,
thermal-, electromagnetic-, and loss mechanisms and in-circuit functions. In order to
develop a reasonable methodology for analyzing the performance as a function of all
these parameters, it is necessary to constrain the problem in some ways and specify
variables in others that will facilitate the analysis.
For this purpose, three kinds of parameters are defined in the analysis below.
These are:
- inflexible constraints,
- discretized parameters and
- design variables.
The inflexible constraints are usually determined by specifications such as the
rated nominal and boundary electrical values and relationships at the component
terminals, the maximum temperature, operating limits and so on. During the design stage
these parameters must remain fixed in strict adherence to these design specifications.
The next category, discretized parameters, involves a set of parameters that
belong to slightly more relaxed constraints in the design. For instance, the design itself
may not be limited to a specific packaging technology or materials. However, during the
iteration in the design stage it may be convenient to stick to a specific manufacturing
technoology implicitely owning its own set of limitations, or make a selection of
materials that are available only in certain thicknesses, i.e. the thickness of magnetic or
dielectric layers, thickness of copper, number of turns in a winding, the properties of
available materials, real estate dimensions, profile, etc.
Chapter 4
82
The remaining category allows continuous adjustment over a given range, such
range having been set by one of the previous parameter categories. The performance of
passive components can then be evaluated by the few remaining design variables over
which the designer has most control, such as the operating frequency, various component
dimensions or impedance ranges, among others.
Thermal Model
As switching frequency increases, the specific losses in the passive components
materials rise exponentially, resulting in raised temperatures. The temperature is
determined by how efficiently heat generated in the components is removed to the
ambient. Each material used in constructing a capacitor or a magnetic component has a
maximum temperature beyond which its performance will start to deteriorate, and in the
worst instances, destroy the component. Hence the component temperature must be kept
at or below the permissible values for proper operation and reliability. If the temperature
is too far below the maximum value, then the component form factor has usually not been
optimized. In other words, for a given component, there is only one optimum temperature,
and this is a maximum.
In structures and configurations that comprise different materials sharing the heat
flux, the optimum temperatures are assumed to be influenced by one another. The
maximum temperature in the structure is then chosen such that the highest possible
temperature is reached in each material (which may not be its individual optimum
temperature), without exceeding the maximum temperature in any material. This means
that the structure is designed so that the operating temperature of at least one material is
optimized, and the temperatures of the remaining materials will be at or below their
individual optima. In the analysis that follows the components are analyzed by
themselves and the optimum temperature is associated with only one material. These
temperatures can therefore be categorized under either the inflexible constraints or under
the discretized parameters. The thermal limits imposed by the design specifications, for
instance minimum ambient temperature or the maximum temperature of the coolant, are
Chapter 4
83
considered to be inflexible design constraints, as the designer does not have control over
them.
The model will be applied to an example of a packaging technology. In addition,
the simplest components, having only one layer of dielectric or permeable material, and
single layers of conductors, are treated. This severs only to illustrate the methodology,
and it should be kept in mind that the model is completely extendable to other planar
embodiments that are not limited in this way.
The passive components are considered to be in planar form as depicted in Fig.
4.2, with cooling structures such as heat sinks, heat spreaders, air flow or coolant, or
other means for providing the cooling function. A single layer of dielectric or magnetic
material is sandwiched between the copper layers. It is further assumed that the
convection from the top surface is negligible in the analysis and the top surface is
adiabatic. This is reasonable, because the upward heat flowing is relatively small in
relation to the heat flowing downwards towards the cooling surface, especially in a
hermetically sealed packaging or an encapsulated environment, which is usual in
military, space and aerospace applications where spatial volume (or weight) is a luxury.
It is further assumed that power dissipation is uniformly distributed in the copper layers
and in the dielectric or magnetic material. This is not always true, but since we are
aiming at high frequency applications, the real estate occupied by the component is very
small, which also means that the temperature distribution on the cooling surface can be
considered even as the thermal conductivities of the materials don’t scale with the
conceptual size reduction. Due to the large thermal conductivity of copper compared to
the other materials, the temperature gradient inside the thin copper layer can also be
neglected.
Chapter 4
84
cooling
or Dielectric
Heat flowTamb
h
copper wcu
Magnetic
Fig. 4.2 Structure of the integrated planar passive components.
pmat W/m3
pcu W/m2
tc
h w
lc
Fig. 4.3 Simplified thermal model of integrated passive components.
The structure of Fig. 4.2 can now be simplified to an even simpler model as
shown in Fig. 4.3. Here pmat [W/m3] represents uniform volumetric losses in the dielectric
or magnetic material, and pcu [W/m2] represents uniform copper losses per unit area, and
h is equivalent to cooling effects (heat sink, air flow etc.). The maximum temperature
Tmax occurs at the topmost copper layer (x=0) (refer to Fig. 4.4). The differential equation
governing the heat flow [114] is given as
02
2
=+∂∂
c
mat
kp
xT ( 4.1)
The boundary conditions are specified by
ambcs
scucsmatscu TtxThA
AptApAp−==
++ ( 4.2)
Chapter 4
85
0=∂∂
−= xxTAkAp scscu ( 4.3)
The general solution to (4.1) is
212
2)( CxCx
kpxT
c
mat ++−= ( 4.4)
From the boundary conditions,
c
cu
kpC −=1 and amb
cmatcuc
c
cuc
c
mat Th
tpptkpt
kpC +
+++=
22
22
Therefore the maximum temperature at 0=x is
ambcmatcu
cc
cuc
c
mat Th
tppt
kp
tk
pT +
+++=
22
2max ( 4.5)
where ck [W/m⋅°C] is the thermal conductivity of the dielectric or magnetic
material, ambT [°C] is the ambient temperature, ct is the thickness of the dielectric or
magnetic layer, and sA is the surface area. Clearly, the maximum temperature is related to
the power dissipation in the copper layer and dielectric or magnetic layer. It also depends
on the thermal conductivity of the passive layer and its thickness.
x=0 x=tc
pmatpcu pcu
Fig. 4.4 Heat transfer of the simplified thermal model.
4.3. Performance of Magnetics as a function of frequency
Frequency Characteristics of magnetic material
Chapter 4
86
When a magnetic material is subjected to a sinusoidal time-varying magnetic field
it creates a phase shift between the flux density, B, and magnetic field intensity, H, due to
magnetic losses. Therefore, the permeability of magnetic materials is a complex number
having a real part corresponding to energy storage and an imaginary part representing
losses [115]:
imagrealc jμμμ −= ( 4.6)
This is useful for predicting magnetic losses for power applications. Since an
inductor under sinusoidal excitation dissipates some energy, its impedance is given by the
series combination of a resistance sR and inductance sL under sinusoidal excitation:
00 μ
μμωω imagreal
ss
jLjRLjZ
−=+= ( 4.7)
where 0L is the air core inductance, sR is related to the imaginary part of the
complex permeability and represents the losses in the component. For a simple toroidal
core with cross section, Ac, path length, lc, and N turns of winding (Fig. 4.5), we have
c
creal
reals l
ANLL2
00
μμ
μ== ( 4.8)
real
imags
c
cimag
imags L
lANLR
μμ
ωωμμ
ωμ===
2
00
( 4.9)
(a) Toroidal core inductor. (b) Series equivalent circuit.
Fig. 4.5 Toroidal inductor and its series equivalent circuit.
The values of equivalent series circuit parameters sR and sL can be measured
directly by using an impedance analyzer [116]. Then the real and imaginary parts of the
complex permeability can be obtained from (4.8) and (4.9) as functions of frequency.
Chapter 4
87
The complex permeability is frequency-dependent [115][117]-[119]. A relaxation
formula may be used to describe the frequency-dependent behavior of complex
permeability as shown in (4.10).
2
0
)(1r
creal
ff+
=μμ
20
)(1r
rcimag
fff
f
+= μμ ( 4.10)
The loss tangent is given by
real
imagm μ
μδ =tan ( 4.11)
where 0cμ is permeability at low frequency, rf is cut-off frequency, which can
usually be determined by measurement. Behavior of the real and imaginary part of the
complex permeability is shown in Fig. 4.6.
μrealμreal
μimagμimag
f (Hz)
A/m
Fig. 4.6 Frequency dependency the complex permeability.
This simple theoretical model is in a good fit to the measurements [117][118][119]
in some cases. However, it is only in good for some materials with single relaxation time.
As pointed out in [120], the behavior of the complex permeability is interpreted as a
superposition of two relaxation mechanisms: domain-wall motion and magnetic moment
rotation [120]. Also three types of relaxation processes exist: a) electron diffusion; b)
Chapter 4
88
diffusion of cations; c) single ion relaxation [115]. All these phenomena and other
reasons such as grain-size dependence [117] can result in a distribution of relaxation time
constant and inaccurate representation of the complex permeability with (4.10). So the
modification of (4.10) is necessary to match the measured frequency characteristics of the
specific magnetic core. Take 3F4 magnetic core for instance and referring to the
measured complex permeability, for example, as given by Ferroxcube, the real and
imaginary parts of the complex permeability are expressed as (4.12). Fig. 4.7 depicts their
frequency-dependent characteristics.
4
0
)(1r
creal
ff+
=μμ
5.4
5.2
0)6.1(1
)6.1(8.1
r
rcimag
ff
ff
+= μμ ( 4.12)
μrealμreal μimag
μimag
A/m
f (Hz) 108105 106 107
104
103
102
10
3F4
Fig. 4.7 Complex permeability of 3F4 as a function of frequency.
Performances analysis of magnetics as frequency increases
The integrated planar inductors in Fig. 4.8(a) to Fig. 4.8(c) are used as examples
to maximize the power density and efficiency by varying frequency and dimension. The
inductors can be implemented in several types as shown and can be simplified to the
representation in Fig. 4.8(d).
Chapter 4
89
lg Air gap
(a) Toroidal inductor. (b) Integrated planar inductor.
wculg
w
tc
lg
w
tc
Iterminal
Jmax
lc/2 lc/2 (c) Integrated planar inductor.
Itotal
lc/2lc/2 w
lg
tctcu
lc/2lc/2 w
lg
tctcu
Jav
(d) simplified model of integrated planar inductor.
Fig. 4.8 Various equivalent integrated planar inductors.
In these figures, lg is the length of an air gap, lc is the length of the magnetic core,
w is the width of the core, tc is the thickness of the core, tcu is the thickness of the copper
layer, Jmax is the maximum current density in the copper winding, Iterminal is the current
through each winding, Javg is the average current density in the copper plate, and Itotal is
the total current through the copper plate. If the number of winding is N, then
altertotal INI min⋅= ( 4.13)
ccuavtotal ltJI = ( 4.14)
cucualter wtJI maxmin = ( 4.15)
Define the winding factor
Chapter 4
90
c
cucu l
Nwk = ( 4.16)
Then substitute (4.14) and (4.15) into (4.13), we get
maxJkJ cuav = ( 4.17)
From Ampere’s law:
gg
cc
cggcctotal l
BlBlHlHI
0μμ+=+= ( 4.18)
where cμ is the permeability of the core, cB is the magnetic flux density in the
core, gB is the magnetic flux density in the air gap.
The fringing factor fk is defined to take into account the fringing effect in the air
gap as
c
gf B
Bk = ( 4.19)
So from (4.18), (4.19) and (4.14),
cuave
gf
c
cuavc tJ
kktJB μ
μμ
=+
=
0
1 ( 4.20)
where form factor gk is defined as
c
gg l
lk = ( 4.21)
The effective permeability due to the air gap is defined as
0
1μμ
μμ
cgf
ce
kk+= ( 4.22)
imagerealee j __ μμμ −= ( 4.23)
The inductance of the inductor is expressed by
wcreale
reale
c
c ktNltwNL _
2
_
2 μ
μ
=⋅
= ( 4.24)
Chapter 4
91
Form factor wk is defined as
cw l
wk = ( 4.25)
The stored energy in the inductor is
⇒== 2_
22min )(
21
21
NIktNLIE total
wcrealealter μ
ccuavcreale wltJtE 22_2
1 μ= ( 4.26)
The energy per unit area is
ccucurealeccuavrealec
s ttkJttJwlEE 222
max_22
_ 21
21 μμ === ( 4.27)
The total losses in the inductor consist of copper losses in the winding and
magnetic losses in the core, both of these loss values are related to the maximum current
density maxJ . The copper loss per unit area is
σσ 2221
2max
222max
2min
cucu
cucuc
cucu
c
walter
cutJk
twwlNwtwJ
wl
RIp === ( 4.28)
whereσ is the electrical conductivity of copper.
The magnetic loss per unit volume in the inductor is given by
vol
RIp
salter
mag
2min2
1
= ( 4.29)
Here cucualter twJI maxmin = ,c
cimages l
twNR ⋅= 2
_ωμ , cc twlvol ⋅⋅= , thus
22max
2_2
1cucuimagemag tJkp ωμ= ( 4.30)
The total power dissipation in the inductor should keep the temperature below the
allowable maximum value according to (4.5). Substituting the copper loss density
equation (4.28) and the magnetic loss density equation (4.30) into (4.5), the maximum
current density maxJ is derived as
Chapter 4
92
cu
cucu
c
ccucugimage
c
c
c
ambg tk
hkttkkf
ht
kt
TTkfJ
σωμ
2)2(),()
2(
21
),(22
_
2max2
max
+++
−= ( 4.31)
The planar inductor shown in Fig. 4.8 is now taken as a case study. The design
parameters are defined in Table 4.1. Some performance values, such as maximum current
density, energy density, power density and efficiency can be derived and quantified as a
function of frequency or dimension, which will be shown in the following parts.
Table 4.1 Definition of design constraints.
Inflexible constraints Discretized constraints Design variables
Thickness of core: 4=ct mm
10=h W/m2-°C
Properties of magnetic material
CT °= 100max
CTamb °= 25
Numbers of winding turns
Frequency: f
Form factors: gk , wk
Thickness of copper:
( 10=cut μm)
For the following example a 3F4 ferrite core is chosen, where 5=ck W/m⋅°C,
00 900μμ =c , 5=rf MHz. The complex permeability is shown in Fig. 4.7. Winding
factor, c
cucu l
wNk ⋅= , is also taken into account in the analysis and 8.0=cuk in the
example below. The fringing factor fk is set to be 0.9 for the analysis.
According to (4.31), under such constraints conditions the maximum current
density through the winding is plotted in Fig. 4.9. When the switching frequency
increases, the losses in the inductor also increase. The current density then needs to be
derated to keep the temperature rise, which is an inflexible constraint.
Chapter 4
93
104 108
maxJ
[A/m2] ΔT= 75°C
105 106 107
f (Hz)
kg=0.01
kg=0.005
kg=0.001
108
107
106
105
3F4
c
gg l
lk =
Cur
rent
den
sity
Fig. 4.9 Maximum current density as a function of frequency.
The energy density as a function of frequency is plotted for gk = 0.01, 0.005 and
0.001 (Fig. 4.10). For a constant switching frequency, the relationship between the energy
density and the form factor gk is plotted in Fig. 4.11. Energy density is also derated as
frequency increases. For any given frequency, there is a maximum energy density that
depends on gk .
104 108
SE
105 106 107f (Hz)
kg=0.01kg=0.005
kg=0.001
1
10-5
10-6
10-7
10-4
10-2
10-3
10-1
[J/m2] 3F4
Fig. 4.10 Energy density as a function of frequency.
Chapter 4
94
1
10-4
10-2
10-3
10-1
[J/m2]
kg10-5 10-4 10-3 10-2 10-1
f=100 kHz
f=500 kHzf = 1 MHz
SE3F4
c
gg l
lk =
Fig. 4.11 Energy density as a function of kg for different frequency.
The volumetric power density of the inductor is
c
sV t
fEP = ( 4.32)
The volumetric power loss density is
c
cumagVd t
ppP +=_ ( 4.33)
The power conversion efficiency is defined as
VdV
Vd
PPP
_
_1+
−=η ( 4.34)
The power density VP and power loss density VdP _ as a function of frequency are
plotted in Fig. 4.12. Fig. 4.13 shows the relationship between the power density and the
form factor gk for the different switching frequencies. Power conversion efficiency as a
function of frequency and form factor gk is illustrated in Fig. 4.14 and Fig. 4.15,
respectively.
Chapter 4
95
VP
3F4
104 108105 106 107f (Hz)
107
106
105
104
[W/m3]
Pd_V
kg=0.01 kg=0.005
kg=0.001
108ΔT= 75°C
Fig. 4.12 Power density as a function of frequency.
kg10-4 10-3 10-2 10-1
107
106
105
104
[W/m3]
VP
3F4
f=100 kHz
f=500 kHz
f = 1 MHz
108
Fig. 4.13 Power density as a function of form factor kg.
Chapter 4
96
104 108105 106 107f (Hz)
100%80%
60%
40%
20%0%
η kg=0.01
kg=0.005
kg=0.001
3F4ΔT= 75°C
Fig. 4.14 Power conversion efficiency as a function of frequency.
η3F4
100%90%80%70%60%50%
kg10-4 10-3 10-2 10-1
f=100 kHz
f=500 kHz
f = 1 MHz
Fig. 4.15 Power conversion efficiency as a function of form factor kg.
Some important conclusion can be drawn from the analysis above. For constant
temperature rise, the power loss density VdP _ is kept constant, independent of frequency
and form factor gk (Fig. 4.12). A proper operating frequency point can be selected to
achieve the maximum power density for constant gk (Fig. 4.12), while maximizing the
power conversion efficiency (Fig. 4.14). As shown in Fig. 4.12, when 01.0=gk , the
Chapter 4
97
maximum power density is achieved at 820 kHz and the power conversion efficiency
reaches a maximum value 98.5%. When the operating frequency is given, the power
density and power conversion efficiency can be maximized by selecting proper form
factor gk as shown in Fig. 4.13 and Fig. 4.15.
Form factor wk doesn’t play a role in determining the current density, energy
density and power density in the previous analysis. It’s mainly determined by the
required inductance as (4.24). Assuming the inductance is inversely proportional to the
frequency (thus maintaining a constant power throughput) and if the initial inductance at
100 kHz is 100 Hμ for 10 turns of windings, then the form factor wk as a function of
frequency based on (4.24) is illustrated in Fig. 4.16. The form factor wk does not always
decrease as a function of increasing frequency due to frequency-dependent permeability
of the core.
wk
3F4
108105 106 107f (Hz)
kg=0.01
kg=0.005
kg=0.001
1
10-2
10-1
10-3
10
Form
fact
or
Fig. 4.16 Form factor kw as a function of frequency.
4.4. Performance of Dielectrics in a Capacitor as a function of frequency
Chapter 4
98
In this section, we consider an illustrative example of an integrated capacitor
comprised of a pair of parallel copper plates separated by dielectric material. Again this
simple structure was chosen for its simplicity, and because it gives direct insight into the
effects of frequency scaling. More complicated, volume-efficient multi-layer capacitors
can also be analyzed using the same technology.
The relative permittivity of dielectric material in the capacitor is a frequency-
dependent complex quantity. The static dielectric constant is an effect of polarization
under DC conditions. When the applied field, or the voltage across the parallel plate
capacitor, is a sinusoidal signal, then the polarization of the medium under these AC
conditions leads to an AC dielectric constant that is generally different from the static
case. To understand and model the dynamic response of dipolar polarization is quite a
complicated affair. Debye, however, rendered the problem tractable by what’s known
today as the so-called Debye equations [121][122][123]. The Debye equations, in (4.35),
describe the behavior of the frequency dependence of the complex dielectric constant:
ωτεεεεεε
jj rrs
rrrr +−
+=−= ∞∞ 1
''' ( 4.35)
where 'rε is the real part and ''rε is the imaginary part, both being frequency
dependent. ∞rε is infinite relative permittivity as ∞→ω , typically equal to 1; rsε is static
relative permittivity at DC condition; τ is the relaxation time, depending on the material,
but typically for liquid and solid media it is in the gigahertz range.
Consider a capacitor, which has its dielectric medium between a pair of parallel
plates (Fig. 4.17).
Fig. 4.17 A parallel plate capacitor.
Chapter 4
99
The admittance,Y , i.e., the reciprocal of impedance of this capacitor is
dA
dAj
dAj
Y rrr )('')(')( 000 ωεεωωεεωωεεω+==
which can be written as
pGCjY += ω
where
dA
C r '0εε= ,
dA
G rp
''0εεω=
The admittance of the dielectric medium is a parallel combination of an ideal, or
lossless, capacitor, with a relative permittivity 'rε , and a resistance of pp GR /1= . There
is no real electric power dissipated in C, but there is indeed real power dissipated in pR
because
Input power = pR
VCVjYVIV2
22 +== ω
Thus the real part 'rε indicates capability of storage of electric field energy for
non-magnetic dielectrics and represents the relative permittivity used to calculate the
capacitance. The energy loss is determined by ''rε . The imaginary part ''rε is the relative
loss factor, known as Loss Factor in the literature. It should not be confused with
Dissipation Factor or Loss Tangent )tan(δ . )tan(δ is defined as:
''')tan(
r
r
εε
δ = ( 4.36)
(4.35) can be split for real ( 'rε ) and imaginary part ( ''rε ) of the complex
permittivity:
2)(1'
ωτεεεε
+−
+= ∞∞
rrsrr ( 4.37)
2)(1)(
''ωτ
ωτεεε
+−
= ∞rrsr ( 4.38)
22
)(''')tan(
τωεεωτεε
εεδ
∞
∞
+−
==rrs
rrs
r
r ( 4.39)
Chapter 4
100
The real part 'rε decreases from its maximum value )0('rε to 1 at high
frequencies. The imaginary part ''rε is zero at low and high frequencies but peaks
when 1=ωτ or when τω 1= (as shown in Fig. 4.18).
εr′(f)
εr′′(f)
εrs
ω1/τ
Fig. 4.18 relative permittivity as a function of frequency.
It can be interpreted as follows: At low frequencies the dipole moment of the
polar molecules orients in the applied electric field. The real part is approximately
constant and equal to rsε , and the imaginary part ''rε is close to zero, which includes the
contributions from the dipolar, ionic, and electronic polarization mechanisms. At higher
frequencies the dipole can no longer follow the directions of the external applied field.
The dipoles are unable to reorientate with that field and the total polarization falls and
only the ionic and electronic contributions remain. Thus, 'rε and ''rε assume rather low
values. However, at a specific frequency called resonance frequency resω ( 1=τωres ), the
efficiency of the reorientation process is at maximum, as the rate of change in direction of
the applied field matches the relaxation time of dipoles. From the viewpoint of energy,
the rate of energy storage by the field is determined by ω whereas the rate of energy
transfer to molecular collisions is determined by τ1 . When τω 1= , the two processes,
energy storage by the field and energy transfer to random collisions, are then occurring at
Chapter 4
101
the same rate, and hence energy is being transferred to heat most efficiently. Thus ''rε
related to the power dissipated in the dielectric medium peaks when τω 1= [121][122].
An implicit assumption made during the derivation of the Debye equations is that
there is only one relaxation time. While this may be true for some crystalline solids, it is
less likely to be so for amorphous solid such as a glass, where the random nature of the
structure will likely lead to a distribution of relaxation times. In this case, a distribution of
relaxation times is necessary to interpret the experimental data. The empirically-derived
Cole-Cole equation is given to take this effect into account as (4.40) [122]-[124].
αωτεε
εεεε −∞
∞ +−
+=−= 1)(1'''
jj rrs
rrrr ( 4.40)
where α is a constant that has a value in the range 10 ≤≤ α . This fractional power
law frequency-domain behavior is a striking characteristic. Nevertheless, the model
correlates well with measured permittivities data for many materials.
The temperature-dependent characteristics of complex permittivity is mainly
expressed through a temperature-dependent relaxation time )/exp( kTHhττ = . If the DC
conductivity σ of the dielectric material is not negligibly small, then the
conductivityσ will contribute to the imaginary part the complex permittivity [123].
)''('0ωε
σεεε +−= rrr j
00 1'''
ωεσ
ωτεε
εωεσεεε j
jjj rrs
rrrr −−+
−+=−−= ∞
∞
In general dielectrics are grouped into three classes [125]: Class I dielectrics
include ceramics with relatively low ( 'rε <15) and medium ( 'rε :15~500) permittivity and
dissipation factors of less than 0.003. Class II dielectrics are high-permittivity ceramics
having values of 'rε between 2000 and 20000 with δtan below 0.03. Class III dielectrics
Chapter 4
102
contain a conductive phase that effectively reduces the thickness of the dielectric and
results in very high capacitance. Their breakdown voltages are quite low, however.
The power losses in capacitors are attributable mainly to Ohmic losses in the
plates, terminals and leads, and the dielectric losses. The dissipated power is distributed
among the conducting elements and the dielectric, and the extent to which each
contributes is also a function of frequency [126]. The dielectric loss is determined by the
specific properties of the dielectric material. Each dielectric material has an associated
loss factor or loss tangent, which is a common representation of the dielectric loss. This
can be represented by a resistance sdR which is in series with the capacitor, and expressed
as
fCCRsd π
δω
δ2
1tan1tan == ( 4.41)
For the integrated planar capacitor with dielectric layer sandwiched between two
copper plates as shown in Fig. 4.19, the current distribution is illustrated in Fig. 4.20.
d
lcw
I
I
4λ
<<w
Fig. 4.19 Integrated planar capacitor with a pair of parallel plates.
I
0 w
I w
Top metal:
Bottom metal: 0
Fig. 4.20 Current distribution along the plates.
Chapter 4
103
Assuming a sinusoidal current source with amplitude I, the current and current
density are related by equation below:
)(max flJI skincδ= ( 4.42)
where )( fskinδ is skin depth:
cucuskin f
fσμπ
δ 1)( = ( 4.43)
and cuσ is conductivity of copper. Corresponding to the current distribution shown
in Fig. 4.20, the copper loss per unit area of the top or bottom copper plate is:
∫ ⇒=w
skinccuskinc
ccu l
dxlwxJ
wlp
0
2max )(
21
δσδ
cu
skincu
Jpσ
δ6
2max= ( 4.44)
The maximum temperature of the integrated capacitor (Fig. 4.19) due to the
power losses in dielectric and copper plates is still presented by (4.5) based on the
thermal model shown in Fig. 4.3. This equation is repeated below for this case:
ambdielecu
c
cu
c
diele Th
dppdkpd
kpT +
+++=
22
2max ( 4.45)
where dielep is the volumetric dielectric loss density, ck is the thermal conductivity
of the dielectric material, d is the thickness of dielectric layer.
The resistance sdR in (4.41) represents the dielectric loss, so for a sinusoidal
current excitation source with the amplitude I , the dielectric loss per unit volume is:
⇒⋅⋅⋅
==Cdlw
lJvol
RIp
c
cskinsd
diele ωδδ 1tan
212
1222
max
2
w
skindiele kdC
Jp 1tan21 22
max ⋅⋅
⋅=
ωδδ ( 4.46)
The energy stored in the capacitor is given by
Chapter 4
104
ClJ
CCICVE cskin
2
222max
222
2)(1
21
21
ωδ
ω=== ( 4.47)
The energy per unit area is then
w
skin
cs kC
Jlw
EE⋅
=⋅
= 2
22max
2ωδ ( 4.48)
The volumetric power density is given by
dfEP s
V = ( 4.49)
As we did before, let’s assume that the capacitance is inversely proportional to the
operating frequency, i.e., =⋅ fC constant, which means that the rate at which energy is
transferred is constant. The inflexible constraints imposed on the following analysis
include maximum temperature maxT at 85°C, and ambient temperature CTamb °= 25 ;
Those parameters that can be discretized include thickness of the dielectric layer,
dielectric material properties, and the cooling coefficient 10=h W/m2-°C. Operating
frequency f and form factor c
w lwk = are variables that can be varied to analyze the
performances of the integrated capacitor shown in Fig. 4.19.
For this example we selected a high-permittivity dielectric X5U with rsε = 4400,
relaxation time 9102.0 −×=τ S, and the thermal conductivity 5.1=ck W/m-°C. The
frequency-dependent complex permittivity is shown in Fig. 4.21. Assuming a specific
capacitance value of 100 nF at 1 MHz, so 1.0=⋅ fC (F⋅Hz). The surface area of the
integrated capacitor is then given by (4.50). Fig. 4.22 shows the surface area as a function
of frequency for two dielectric layer thickness values. It is clear that at first the surface
area will become smaller with increasing frequency, but it will again become larger
beyond some frequency because it then becomes necessary to derate the frequency-
dependent real part of the permittivity.
'0 r
dCAεε⋅
= ( 4.50)
Chapter 4
105
f (Hz)108 1010109107106
1
2000
4000εr′(f)
εr′′(f)
Effective relative permittivity
X5U
Fig. 4.21 frequency-dependent relative permittivity of X5U.
f (Hz)
[cm2]
d=0.25mm
d=0.5mm
108 10101091071060.01
0.1
1
10
100
Surfa
ce a
rea
)( fA X5U
Fig. 4.22 Surface area changes with frequency.
From (4.44), (4.45) and (4.46), the maximum current density is derived as (4.51)
and is plotted in Fig. 4.23 as a function of frequency.
)6
14
tan)(2(),( 2
max2max
cuwc
ambw
kChkd
TTkfJ
σδ
ωδδ
+⋅⋅
+
−= ( 4.51)
Chapter 4
106
f (Hz)
108 109107106
108
107
106
[A/m2]
maxJ
X5U
kw=0.5kw=1
kw=4
Fig. 4.23 Maximum current density through the cap as a function of frequency.
Then from (4.48) the energy density as a function of frequency is plotted in Fig.
4.24 for several form factorsc
w lwk = . And the energy density versus the form factor
cw l
wk = is illustrated in Fig. 4.25. When the frequency increases, the stored energy
density decreases. The energy density doesn’t strongly depend on the form factor wk .
f (Hz)
108 10910710610-7
10-1[J/m2]
10-610-510-4
10-3
10-2SE
X5U
kw=0.5
kw=1
kw=4
Fig. 4.24 Energy density vs. frequency.
Chapter 4
107
SE
X5U
0.1 1 10kw
f=1 MHz
f=5 MHz
f = 10 MHz10-4
10-3
10-2
10-1
[J/m2]
Fig. 4.25 Energy density vs. form factor kw under different frequencies.
The total volumetric power loss density VdP _ can be derived from both the
volumetric dielectric loss density (4.46) and the copper losses per unit area (4.44), given
by
dppP cu
dieleVd +=_ ( 4.52)
The power density VP (4.49) of the integrated capacitor is illustrated in Fig. 4.26
as a function of frequency along with its power loss density VdP _ . Fig. 4.27 plots the
power density as a function of form factor wk . When the frequency increases, the power
density decreases with a slope nearly -20 dB/dec. Under these conditions, the form factor
wk doesn’t seem to play much role in this process. Power loss density is also kept
constant for constant temperature rise, independent of frequency and form factor wk .
Chapter 4
108
f (Hz)
108 109107106
106
105
109
[W/m3]
Pd_V
VP kw=0.5
kw=4
X5U
107
108
ΔT= 60°C
f (Hz)
108 109107106
106
105
109
[W/m3]
Pd_V
VP kw=0.5
kw=4
X5U
107
108
ΔT= 60°C
Fig. 4.26 power density as a function of frequency along with the power loss density.
109
[W/m3]
VP
X5U
106
107
108
0.1 1 10kw
f=1 MHz
f=5 MHzf = 10 MHz
Fig. 4.27 power density as a function of form factor kw.
The power conversion efficiency as a function of frequency, according to (4.34),
is illustrated in Fig. 4.28. Fig. 4.29 plots the power conversion efficiency as a function of
form factor wk .
Chapter 4
109
100%
60%
20%0%
80%
40%
f (Hz)108 109107106
η kw=0.5
kw=4
BA
X5U
Fig. 4.28 power conversion efficiency vs frequency.
0.1 1 10kw
f = 10 MHz
100%
94%
90%
96%
92%
f=1 MHz
f=5 MHz
η
X5U
98%
Fig. 4.29 power conversion efficiency as a function of form factor kw.
As shown in Fig. 4.28 when the maximum temperature is fixed at 85°C, at point
A when 5.0=wk , energy lost per cycle exceeds the amount of energy stored per cycle at
=f 125 MHz, i.e. that power conversion efficiency is below 50%. In order to ensure the
Chapter 4
110
power conversion efficiency larger than 90% when 5.0=wk , we learn here that the
operating frequency should not exceed 13.6 MHz (at point B).
In our next analysis we have selected the low-permittivity dielectric Silicon
Nitride (SiN). It has a static relative permittivity rsε of 7.8, relaxation time τ= 0.1×10-11 S,
and its thermal conductivity 25=ck W/m-°C. The frequency-dependent relative
permittivity is shown in Fig. 4.30. The capacitance is again assumed to be inversely
proportional to the frequency and the initial capacitance is set to a value of 1 nF at 100
MHz. The thickness of the dielectric layer =d 100 μm. The maximum temperature
maxT is still 85°C for 25°C ambient temperature. The surface area as a function of
frequency is plotted in Fig. 4.31. As before, the relationship between the power
conversion efficiency and frequency or form factor wk is derived, and shown in Fig. 4.32
and Fig. 4.33 respectively. For wk =0.5, the power conversion efficiency is 50% at 24
GHz (point A in Fig. 4.32); the power conversion efficiency reaches 90% when the
operating frequency is 1.9 GHz at point B in Fig. 4.32. It is clear that low permittivity
dielectrics are more suitable for very high frequency operation due to its lower tangent
loss, but at the expense of larger volume.
f (Hz)
εr′(f)
εr′′(f)
Effective relative permittivity8
6
2
0
4
108 1010109 1011 1012
SiN
Fig. 4.30 relative permittivity as a function of frequency.
Chapter 4
111
f (Hz)
Surface area )( fA[cm2]
108 1010109 1011
d=0.1mm
102
10
10-2
10-1
1SiN
Fig. 4.31 surface area of capacitor as a function of frequency.
100%
60%
20%0%
80%
40%
f (Hz)1010 1011109108
η
kw=0.5
kw=4
B
A
SiN
Fig. 4.32 power conversion efficiency vs frequency.
Chapter 4
112
0.1 1 10kw
f = 1 GHz
100%
70%
50%
80%
60%
f=100 MHz
f=500 MHz
η SiN
90%
Fig. 4.33 power conversion efficiency as a function of form factor kw.
4.5. Experimental Verification on Frequency Scaling Effects of Integrated Inductor
The purpose of this chapter is to verify the frequency scaling effects of the
integrated magnetic components based on the model setup previously through the
experiments. An integrated planar inductor will be made as the sample for the
experiments. 3F3 is chosen as the magnetic material. The customized ferrite cores from
Elna Magnetics Co. are chosen as the parts to make a planar integrated inductor. The
shape of the customized planar ferrite cores PLT64/50/5 is shown in Fig. 4.34(a). The
planar inductor is comprised of two ferrite cores, shown in Fig. 4.34(b).
Chapter 4
113
a
wcwc
wc
b
w
c
wc
wc
wca
lg
(a) Customized planar core. (b) Planar inductor comprised of two cores.
Fig. 4.34 Customized planar core and the inductor under study.
The practical dimensions of the ferrite core in Fig. 4.34 are listed in Table 4.2.
The width wcu of the copper windings wrapped around the ferrite core is 6.5 mm. The
number of the copper winding turns N is 20. The average magnetic path length is lc = 256
mm.
Table 4.2 Dimensions of customized ferrite core
a b wc t (core thickness) tcu wcu
62 mm 48 mm 15 mm 5 mm 50 μm 6.5mm
The fabrication process of the sample is described in Appendix IV. After the
processes as described in Appendix IV, the final inductor is shown Fig. 4.35, consisting
of two ferrite cores.
Fig. 4.35 Inductor sample for experiment.
Chapter 4
114
The impedance of the inductor is measured by impedance analyzer 4294A and
shown in Fig. 4.36. The frequency-dependent permeability of 3F3 can be modified to
match the measured impedance. The kg can be obtained from (4.24), kg = 0.0013. The
fringing factor is chosen as kf = 0.7. The winding factor kcu = 0.47.
Fig. 4.36 Impedance characteristics of the inductor.
The planar inductor is put inside of the calorimeter chamber built in Chapter 5, as
shown in Fig. 4.37. In order to prevent heat escaping from the top of the inductor, the top
of the inductor is covered with thermal insulation material - fiber glass. The dimensions
and thermal properties of all the parts in the Fig. 4.37 are shown in Table 4.3. The
thermal contact resistances exist between surfaces. We cannot ignore thermal contact
resistances, but they are very difficult to quantify. In the design process a 1 K-cm2/W
contact thermal resistance coefficient is assumed [127].
Impedance
Phase
Chapter 4
115
(a)
(b)
Fig. 4.37 Diagram of the planar inductor and the chamber.
Chapter 4
116
Table 4.3 Dimension and properties of the parts in Fig. 4.37.
Dimension (L×W×t) (mm) Thermal Conductivity
W/m-K
Plate VII 140×160×10 167
Plate VI 50×50×10 167
Plate V 26×30×10 167
HFS-4 26×30 ×0.23 3.5 (K/W)
Plate IV 50×50×10 167
Plate III 50×50×10 167
Plate II 80×80×10 167
Plate I 240×240×10 167
Gap Pad 96×62×0.25 3
Polyimide Thickness:0.064 × 3 0.12
Magnetic layer Thickness: 5 3
Copper layer Thickness:50 μm 385
In the experiment, a sinusoidal waveform generated by Agilent 33120A waveform
generator is amplified by power amplifier (AR amplifier Model 1000L) to the inductor
inside the chamber. Differential probe P5205 measures the voltage across the input
terminals of the inductor, TCP202 current probe records the current flowing into the
inductor. And Data Acquisition Unit 34970A is used to record the measured temperatures
and the output of the heat flux sensor HFS-4 inside the calorimeter (refer to Chapter 5).
The experiment setup is shown in Fig. 4.38.
In order to verify the performances of the inductor as a function of frequency,
experiments at several frequency points are carried out. In these experiments, the input
power (Vmax⋅Imax) into the inductor is kept constant, with regard to the difficulty of
controlling the power losses generated in the inductor to keep constant temperature rise.
The power loss densities and efficiencies at several operating frequencies are identified.
The Table 4.4 shows the measurement results. The measured data points are marked in
Fig. 4.39, Fig. 4.40, Fig. 4.41 along with the theoretic curve predicted from the model. It
Chapter 4
117
is clear that the measured results match the expected curve very well.
Table 4.4 Measurement results.
f PV (W/m3) Imax (A) Vmax (V) Tmax (°C) Pd (W)
Theory 0.35 244 72 9.9
Measured 1 MHz 3.5×105
0.35±3% 236±3% 75.6 ±2 10 ±5%
Theory 0.29 145 55 6.1
Measured 800 kHz 3.5×105
0.31±3% 136±3% 54.3 ±2 6.2 ±5%
Theory 0.44 190 45 3.8
Measured 700 kHz 3.5×105
0.43±3% 192±3% 44.5 ±2 3.6 ±5%
Theory 0.53 159 35 1.85
Measured 500 kHz 3.5×105
0.58±3% 146±3% 34.2 ±2 1.86 ±5%
Theory 0.6 142 31.1 1.1
Measured 400 kHz 3.5×105
0.67±3% 126±3% 31.9 ±2 0.94 ±10%Theory 0.84 100 26.4 0.25
Measured 200 kHz 3.5×105
0.95±3% 88±3% 27 ±2 0.23 ±10%
Chapter 4
118
Power Amplifier
Input to inductor
Calorimeter
Waveform Generator
Sinusoidal waveform
Waveform Generator
Sinusoidal waveform
Digital Scope
Voltage & Current Probe
Data Acquisition Unit
Measurements
Data Acquisition Unit
Measurements
Fig. 4.38 Experiment setup.
1 MHz800 kHz
VdP _
[W/m3]
f (Hz)
700 kHz
500 kHz
105 106 2×106
3F3
107
106
105
104
103
Constant input power
400 kHz
200 kHz
Fig. 4.39 Measured power loss density as a function of frequency.
Chapter 4
119
f (Hz)104 106 2×106
Efficiency η
0%
20%
40%
60%
80%
100%3F3
1 MHz800 kHz
700 kHz
500 kHz
400 kHz
200 kHz
105
Fig. 4.40 Measured efficiency as a function of frequency.
[°C]
Temperature
1 MHz
800 kHz
700 kHz
500 kHz
3F3
f (Hz)105 106
40
60
80
100
252×106
400 kHz
200 kHz
Fig. 4.41 Measured temperature vs frequency.
Chapter 4
120
4.6. Summary
A generic multi-disciplinary model was developed in this chapter to analyze the
performance of passive components in terms of power density and power conversion
efficiency as a function of frequency scaling. The material characteristics, thermal
management and temperature constraints, circuit specifications and packaging techniques
are all incorporated into this model.
For magnetic components (single layer planar inductor in the examples), power
density and power conversion efficiency can be optimized by selecting proper operation
frequency or form factor during the design procedure. It was demonstrated how the
optimum frequency can be identified, and how power conversion efficiency deteriorates
beyond the optimum under a fixed maximum temperature. The analysis also shows how
frequency dependencies of material properties are responsible for today’s capacitor
technologies being more suitable for high frequency operation than magnetic components.
Therefore for very high frequency operation, even at hundreds of megahertz, air-
core magnetic components are necessary. But the price paid to it is the substantially
raised volumes, defeating our original objective for reduced volume and increased power
density.
It should be noted here that the self-resonant frequency of the passive components
due to parasitic is not considered in the analysis. In practice, self-resonant frequency,
depending on the structure and manufacturing technology, also plays a role in limiting the
highest operation frequency.
Lastly, the examples demonstrate how the methodology can be used to identify
the most optimum power conversion frequency for a given set of specifications, circuit
function, selection of materials and packaging technology and limitations, and thermal
conditions.
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Chapter 5 Power Loss Measurement Techniques for HF/VHF power conversion Applications
5.1. Introduction
It is important to measure the high frequency signals accurately for the purpose of
verifying design, characterizing and debugging the design if problems are found.
In previous chapter, a VHF DC-DC power converter was designed and it became
necessary to visualize the converter to ensure its proper operation through the
measurements. However the task of measuring at such high frequencies is really a big
challenge for engineers. Accurate measurement of such high frequency signals requires
very sophisticated instrumentation to acquire useful information about its operation. The
instrument should have a bandwidth sufficiently beyond the highest frequency contained
in signals being measured. This very sophisticated instrument must also be able to
measure signals without interfering with the operation of the circuits and systems.
Therefore it is necessary to use high performance current or voltage acquisition systems
to obtain the current or voltage waveforms. Limited by bandwidth, interference or
sensitivity, no suitable current sensing techniques [128] are available for this 250 MHz
power converter at present. So only the voltage measurement is possible and a voltage
probe is discussed and in Appendix II.
A model was established in Chapter 4 to investigate the performances of
integrated passive components in terms of power density and efficiency by varying
frequency or dimensions. It is clear that accurate determination of losses is required to
validate the design and verify the model. Also accurate estimates of these losses in these
integrated passive components are important to characterize their thermal behavior,
which is driven by the demand for reducing volume, pushing frequency higher and
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122
improving efficiency. The accurate measurement of losses, presenting many difficulties,
can be approached by electrical measurement and calorimetric measurement.
It is realized that the losses measurement by electrical method could yield errors
of 100% and more. It is well known that the measurement of high efficiency systems is
difficult, and the difficulty increases as the efficiency increases. The effects of switching
transients, non-linearity of components, high frequencies and so on make the accurate
measurement of losses more difficult. Errors larger than 100% are not uncommon, even
using very sophisticated digital instruments. Digital instruments are notoriously
susceptible to EMI/RFI and the main sources of error include: sampling errors and phase
shifts between channels; delays, parasitic effect introduced by probes; mismatched
bandwidth; errors introduced by AD conversion. Therefore losses measurement by the
electrical instruments is most suitable for pure DC and low frequency systems.
To overcome the limits of electrical measurement, the calorimetric method is an
alternative for loss measurement since it is based on the heat effect caused by the power
dissipation and independent of the electrical quantities in the systems. It is suitable for
measurement under high frequency and non-sinusoidal conditions. Calorimetric method
is the most popular and the most promising method to accurately measure losses in
magnetic losses or dielectric losses. It can achieve high accuracy but be limited to steady
state and be time-consuming.
5.2. Limitations of electrical measurements for power loss measurement
5.2.1. Background
The need of a quantitative knowledge of power loss in any power electronics
system is self-evident. Driven by recent advances toward integration, higher operating
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123
frequencies and improved efficiency in power electronics systems, accurate estimates of
power losses is becoming more challenging and important to ensure proper thermal
management and reliable operation. Although sophisticated numerical modeling methods
are often available to predict power losses, validity of the models need to be verified
experimentally, especially where complex loss mechanisms exist in some parts, for
instance magnetic materials for power conversion.
Typically there are two kinds of techniques to measure the power losses:
- electrical methods;
- calorimetric methods.
The electrical measurement [131][132][133][134][135][136] uses the product of
voltage and current, which gives an electrical quantity equivalent to power. Power
measurement can be performed by measuring the voltage drop across the device and the
current flowing through it using electrical instruments. In DC and low frequency AC
circuits it is common to measure power directly by using analog electronic equipments:
voltmeters for voltage measurements and ammeters for current measurements, or a
combined measurement using a wattmeter. However for high frequency signal and highly
distorted signals, such as pulse width modulation, conventional meters are no longer
suitable because of their limited bandwidth and dynamic frequency response. Digital
instruments have gained popularity for obtaining the required resolution. This kind of
digital meter takes simultaneous samplings of voltage and current waveforms, digitizes
these values, and provides arithmetic multiplication and averaging using digital
techniques to obtain a power measurement. An appealing advantage of the electrical
methods is that they are easy to perform and to reproduce a measurement. It is suitable
for steady state as well as transient measurements. However, high di/dt and dv/dt’s
introduce serious RFI/EMI problems, since digital instruments are very sensitive to noise.
The accuracy of digital measurement is also affected by the delays introduced between
probes, phase shifts between sampling channels of digitizer, sampling errors and non-
linearities of A/D converters. No instrument known to man can accurately record the
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124
hard-switched output voltage waveforms when dv/dt is very high [137]. Therefore the
electrical measurement methods are most suitable for pure DC or low frequency systems.
Loss measurements in power electronics systems become especially difficult for
components or systems having high power conversion efficiencies. The conventional
output-input electrical method can produce very large errors, regardless of the technique
used for measuring input and output power, because a considerable error always exists
when two nearly equal numbers are measured and subtracted in such a high efficiency
system.
For example, 1 kW converter with an efficiency η=93%, input power Pin
=1000 W,
output power Pout
=930 W, Ploss
= Pin
- Pout
=70 W, and assuming IVP ⋅∝ , and a ±1.5%
error distribution in voltage and current measurement for the input and output power,
then the maximum error of loss measurement can be ±57.9 W with respect to nominal 70
W. In other words under these idealistic conditions the absolute percentage error of loss
is 83%. If the efficiency increases to 95%, the maximum error percentage can be 117%
(Fig. 5.1)! Clearly, there is a high degree of inaccuracy, which makes the loss figure
totally unacceptable. In order to achieve a maximum absolute error of 5% in the total loss
measurement using this method, an error as small as 0.09% in each of the voltage and
current measurements is required. Such a small error is difficult to achieve, even
employing the most sophisticated metering instruments.
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125
Fig. 5.1 Percentage error of loss measurement vs efficiency for given error of voltage and current.
Note that measurement uncertainties are usually expressed in terms of a standard
uncertainty, which is evaluated by either statistical methods or an assumed probability
distribution. Since definitions of measurement uncertainty are often subjective and even
unique among different standards, the discussion herein will focus more on the
independent sources of error than their interpretations and distributions.
5.2.2. Direct Wattmeter Measurement [139]
In this method the traditional electromechanical wattmeter has been used to
directly make measurements of the electrical power of device under test. At higher
frequencies the wattmeter accuracy becomes quickly deteriorated, especially when
voltage and current waveforms are non-sinusoidal and contain high frequency harmonics.
Usually this kind of wattmeter has low bandwidth and poor frequency response, therefore
it is only applicable to DC and low frequency sinusoidal measurement, and unsuitable for
high frequency and non-sinusoidal conditions.
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126
5.2.3. Digital Measurement Techniques
Today digital instruments, especially digital oscilloscopes, are some of the most
widely used measuring tools in power electronics systems. Estimating losses digitally is
based on the high frequency sampling of voltage and current waveforms. For periodical
power signals with voltage )(tv and current )(ti , having a period of T , determine the
average power 0P of
∫ ⋅=T
dttitvT
P00 )()(1 ( 5.1)
The voltage and the current waveforms are simultaneously sampled at a sampling
rates
s Tf 1= , and converted to digital values. The instantaneous power is the product of
the digital values. If )(tv and )(ti are the instantaneous samples of the voltage and current
at time NiTti = , then the average power 0P can be approximated by
∑−
=
=1
0)()(1 N
niid titv
NP ( 5.2)
where N is the number of samples used in the average.
High-speed digital acquisition of voltage and current data using modern digitizers
along with PCs makes this technique a powerful tool for power loss measurement. This
method has been used for high frequency magnetic core loss measurement [157][158]. In
[157] an automated measurement system for core loss characterization, under sine wave
or square wave voltage excitation, is presented (see Fig. 5.2). The core loss of a toroidal
core in a temperature-controlled chamber is obtained by computing the mean of the
product between primary current (through current-sensing resistor or current probe) and
open circuit secondary voltage referred to the primary over an integer number of acquired
cycles. Under sinusoidal excitation, the core loss is given by
θcos)()(10
VIdttitvT
PT
== ∫ ( 5.3)
where θ is phase angle between voltage and current. The percentage error in the
loss measurement due to uncertainty in the phase is obtained as
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127
%100tan),( ×Δ⋅=Δ
= θθθPPNf ( 5.4)
The phase error per data sample, Ne °= 360 , causes a maximum phase difference
error e2=Δθ , where 0f
fN s= denotes the ratio of sampling rate to excitation frequency.
Fig. 5.3 shows the percent error involved in core loss measurement versus phase angle for
different sampling number N over a cycle.
Power Amplifier
Function Generator
Current ProbeAmplifier
Digital Oscilloscope
Data AcquisitionUnit
Temperature
Temperature Chamber
N:N
CUT
Open circuit secondary voltageCSR voltage drop
GPIB PC
CSR
Fig. 5.2 Automated measurement system for core loss.
Fig. 5.3 Percentage error caused by sampling uncertainty in phase angle versus phase angle for
different N.
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128
Fig. 5.3 illustrate that when θ is close to 90° the percent error can be quite large,
even for high sampling rate. The graph shown in Fig. 5.3 represents the maximum
percentage error in the loss estimate due to the limited phase resolution only. If the
amplitude error caused by the resolution of the digitizer and the delay introduced between
current and voltage waveforms due to the probe and the cable are considered, the error
will be larger [158].
A computer-based data acquisition system coupled with a digital oscilloscope to
create a virtual instrument for instantaneous and average power measurements on
resistors, capacitors, AC/DC power converters and BJT inverters is described in [159].
The same technique was adopted in [160] to measure the power loss of transformer. This
kind of instrument shows good accuracy for operating frequencies up to 100 kHz.
However, when a digital oscilloscope is used for measuring losses in high frequency
switching power devices, large errors may occur [161][162[163][164]. During high-speed
measurements, parasitic parameters that exist within the measurement system introduce
significant aberrations into the measured waveforms. Firstly, different propagation delays
due to the physical construction of voltage and current probes are noticeable for MHz
signals [165]. Although compensation and correction are recommended to reduce these
delays, it is pointed out in [165][166] that compensation alone is not sufficient for
overshoots and distortions introduced by probes and cables, especially when the probe’s
input capacitance is of the same order of magnitude as the capacitance of the device
under test. Secondly, the bandwidth and risetime of oscilloscope/probe system also affect
measurement accuracy. The equations used to approximate scope/probe system rise time
and bandwidth [167] are:
2 scope
2 probe trtrrisetime System +≈ ( 5.5)
2 scope
2 probe trtr
4.0bandwidth System+
≈ ( 5.6)
Table 5.1 shows how the ratio of source bandwidth to system bandwidth affects
amplitude attenuation of the measured waveforms. As seen from this table, for reasonable
Chapter5
129
accuracy Probe/Scope system bandwidth should always be 3 to 5 times larger than
measured signal bandwidth.
Table 5.1 SOURCE BANDWIDTH VS. SYSTEM BANDWIDTH
Ratio of Source Bandwidth to
Probe/Scope System Bandwidth Risetime Slowing Amplitude Attenuation
1:1 41%1:2 12%1:3 5% 1:5 2%
Finally the ground lead and probe input capacitance could adversely affect the
accuracy of measurement by inducing high frequency resonance. Common mode noise
may also intrude the measurement system through the ground lead. Susceptibility to
RFI/EMI is therefore another important source of uncertainty.
5.3. Review of Calorimetric method for loss measurement
5.3.1. Introduction
In theory higher accuracy is possible by measuring loss directly. Since the total
power losses dissipate as heat, the effect caused by the heat can be measured to determine
the losses. This can be achieved by calorimetric methods. Consequently, calorimetric
method based on direct loss measurement provides a more accurate measurement
technique. Calorimetric methods have been widely used in power electronics to measure
the power losses of magnetic components [138]-[142], capacitors [143], switching
semiconductors [144][145], power converters [146] and electrical machines [137][147]-
[155]. Consequently, the calorimetric principle is the most promising of the methods
available for accurate power loss measurements [155][156]. This method has the
advantage of being able to measure the power losses under normal operating conditions
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130
and being independent of electrical quantities of the device under test. Disadvantages are
that it is usually limited to steady state and that the measurement procedure is time-
consuming.
The electrical methods discussed above are all based on indirect loss
measurements. Consequently, good accuracy is not easily achieved. Calorimetric
methods provide the means for measuring losses directly and are therefore expected to
have better accuracy. In addition, they are less dependent on electrical peculiarities of the
devices being tested. One challenge is then to measure losses of power electronics
modules, components or sub-systems under actual operating conditions.
5.3.2. Basic Principle of Operation
The calorimetric method is essentially aimed at measuring the Ploss which the
DUT (device under test) dissipates as heat within a measurement chamber. If the heat is
completely absorbed by the coolant surrounding the DUT, under steady state the power
dissipated by the DUT can be calculated, from measured values of the mass flow rate ( m& )
and temperature rise ( TΔ ) of the coolant, as follows:
Tmcdt
TmcP p
ploss Δ⋅⋅=
Δ⋅⋅=
•
( 5.7)
where pc is the specific heat of the coolant. The calorimeter can take an open or
closed form as in Fig. 5.4.
TinTout
Ploss
DUTPloss
TinTout
DUT
a) open type calorimeter; b) closed type calorimeter.
Fig. 5.4 Types of calorimeter.
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131
The open type calorimeter exchanges heat directly with the surrounding air,
whereas the primary coolant is circulated in a closed loop inside the closed type
calorimeters that require heat exchangers to remove the heat. The closed type calorimeter
is much more accurate than the open type [147].
Some calorimeters based on the equation above have been presented in [140][141]
for transformer loss measurement and in [154] for loss measurement of electrical
machines. In [140], the transformer is placed in thermal contact with a calorimeter block
having known mass and specific heat values. Assuming that the system is isolated from
the environment, the transformer loss can be calculated based on an energy increment of
the block, which is a product of the mass, specific heat and temperature rise of the block
in a specific time interval. However, in practice the calorimeter block and transformer are
not perfectly isolated from the environment. It is therefore necessary to compensate for
the energy that leaks to the surrounding through insulation and through transformer leads.
The thermal connection between two bodies is also critical since the error caused by poor
thermal contact can’t be compensated.
In [141], the coolant of dielectric fluid FC40, is circulated in the closed cooling
system, which consists of the reservoir, pump and, cooling coils near an adiabatic
calorimeter tube (Fig. 5.5). A delta-T thermocouple pile is used in this system for a
temperature difference measurement and a flow meter for measuring the flow rate. It is
important to maintain a constant flow rate through the chamber, minimize the heat
leakage through the walls of the chamber and control the temperature of the FC-40 fluid
in the reservoir.
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132
Calorimeter Reservoirreservoir pump andfluid cooling fluid
DUT
Calorimeter tube
pump
flow valve/meter
TΔ
FC40 fluid
Fig. 5.5 Block diagram of calorimeter illustrated in [141].
5.3.3. Open-type Balance Calorimeter
A single chamber calorimeter was demonstrated by Turner et al. [20] for the
measurement of losses in a 5.5 kW induction motor. This open type calorimeter uses air
as the coolant and loss measurement is based on the balance method. Determination of
the unknown losses takes place in two parts ⎯ the DUT test and the balance test.
Essentially, the input power in the balance test is adjusted until the coolant temperature
rise is the same as the value obtained during the DUT test. This method eliminates the
need to measure the specific heat, coolant flow rate. However, the cooling fluid has to
keep the same properties (such as temperature, relative humidity, pressure, and flow rate.)
in the two tests. In [20] a worst-case accuracy of 1.45% was reported at full load. The
DUT test and the balance test lasted between 6 and 8 hours. This simple balance
calorimetric technique has also been successfully implemented for measuring the losses
of power electronic systems in permanent magnetic machines [137] and magnetic
components in power converters [139] with good accuracy.
The balance calorimeter is easy to implement. However it is time-consuming. It is
difficult to maintain the same measurement conditions for both tests. Generally,
expensive equipment and advanced control are required to maintain the same airflow,
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133
temperature and humidity between two tests. As described in [152][153], an improved
calorimeter with advanced computer control was designed. Air temperature, humidity,
pressure and volume flow rate are accurately measured with high precision instruments
and are provided as feedback signal to computer to correct the difference between two
tests. Thus very good accuracy is achieved, but at the expense of complicated control,
large and complex configuration, and cost. Due to the high repeatability and accuracy,
there is no further need for the balance test once calibrated. An accuracy within as little
as 0.2% was reported for a loss measurement of a 30 kW induction motor.
Another balance calorimeter presented by Turner is an open type double chamber
calorimeter (DCC) [168] shown in Fig. 5.6. The DCC can perform a motor test and a
calibration test simultaneously. The ratio of the measured losses to the reference heat
losses is proportional to the ratio of the respective air temperature rise. Since the same air
is used for both tests, errors are reduced by removing the uncertainty of air’s thermal
properties between tests. Also the DCC simplifies the calorimeter operations and shortens
the test time, but it doubles the chamber size. An overall accuracy of ±15 W was obtained
in [168] for 1 kW losses in a 7.5 kW machine, and ±2% error based on the 600 W total
losses was reported in a flow calorimeter [169], a variation of DCC technique with
labyrinth structure to improve mixing of the air, shown as in Fig. 5.7.
The DCC method is an improved technique, which reduces the testing time
compared with the balance test of the single chamber. However, the problem of different
heat leakage between two chambers still exists. Once again there is no guarantee that the
airflow conditions inside two chambers are similar.
ΔT1 ΔT2
Fan
Air inlet Air outlet
Fig. 5.6 Block diagram of DCC in [168].
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134
HG A
B
C
D E F
I
BD
E
F
G
Fig. 5.7 Flow calorimeter
a) front view cross section; b) cross-section view of the labyrinth from the top.
A: temperature equalizer; B: inlet room; C: test room;
D: outlet of test room; E: reference heater; F: outlet of reference heater;
G: regulated fan; H: supply, control and readout; I: cable feed through.
5.3.4. Double-jacketed, Closed Type Calorimeter
As mentioned before, it is very important to minimize the heat leakage through
the chamber walls and other parts of the calorimetric chamber. The concept of a double-
jacket calorimeter was presented by P.D. Malliban in [147][148][149]. This is essentially
a closed type calorimeter that directly measures the power losses according to the basic
equation mentioned above, but a second thermally insulating enclosure is introduced to
prevent the heat leakage through the walls, and also to ensure that all heat from the DUT
is completely absorbed by the coolant. Therefore, the power lost through the chamber
walls can be set less than the required absolute accuracy accP . In theory, the heat leakage
in the closed type calorimeter shown in Fig. 5.4(b) can be eliminated if the temperature
inside the calorimeter is the same as that of ambient. Thus, a significant improvement in
the accuracy of losses measurement is possible by spending half of the time that is
typically required by balance calorimeter. The schematic of the double-jacketed
calorimeter is depicted in Fig. 5.8.
The outer insulating enclosure isolates the calorimeter from the ambient. The air
gap temperature eT is controlled to be equal to the temperature iT inside the calorimeter. To
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135
ensure that power loss through the inner calorimeter walls is less than required absolute
accuracy accP the following relation should be satisfied:
DUT Ti
TinTout
Pfan(i)
Pheater(i)
Pheater(e) Pfan(e)
Ta Te
Ploss
Fig. 5.8 Schematic of double-jacket calorimeter.
)(calthaccei RPTT <− ( 5.8)
where )(calthR is the thermal resistance of the inner walls.
Although the calorimeter of [147] was originally designed to test a motor up to
1.1 kW, it can also be used to perform tests on a 2.2 kW induction motor [148]. An
air/water heat exchanger placed inside the chamber is used to absorb the heat dissipated
by the test motor and DC fans are used to force air through the heat exchanger. A water
tank is located above the calorimeter. The flow rate is measured by weighing the water at
fixed intervals of time and is adjusted by throttling the valve. The insulating wall and
motor support structure were carefully designed to reduce the heat leakage. Heaters and
fans were evenly placed in the air gap to ensure uniform temperature distribution on the
surface and to avoid local cold or hot spots. With special attention paid to the potential
sources of error and improved design, 0.5 W accuracy on a full scale of 300 W was
achieved by using this calorimeter. It is claimed in [148] that an accuracy of 0.1 W over
200 W is possible with smaller and more accurate calorimeters.
A calorimetric wattmeter (shown in Fig. 5.9) constructed at Aalborg University is
also a double-jacketed closed-type calorimeter [155][156]. It consists of two concentric
thermally insulated boxes. The surfaces of the inner test chamber are coated with glass
fiber and epoxy. It is equipped with an internal heating system that serves the dual
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136
purposes of creating a desired test temperature and for calibration. An array of 68 light
bulbs in the air gap regulates the surface temperatures to minimize the heat flux through
the walls. These bulbs also lead to faster response by radiating the heat to the surface. A
gear pump controls water flow rate and a flow meter senses the flow rate. A refrigeration
unit combined with a heater before the inlet controls the inlet coolant temperature. The
heat dissipated from the DUT is absorbed by the flowing water through the heat
exchanger. Numerous temperature sensors are installed in the measurement system for
measuring temperatures in different locations. A PC with LabViewTM is used to control,
regulate and store all the data. An empirical formula was presented to compute the inlet
temperature and mass flow in advance by using a predicted value of the power loss as an
input. This calorimeter can measure power losses in the range of between 1W and 50W
with an error of less than ±0.2% at full load. The physical size of the DUT was
200×200×300 mm, but could be up to 1000×1000×700 mm for measuring losses of
between 200~1500 W.
DUT
Balance Heater
Heat exchanger
Tin Tout
Heater
RefrigerationUnit
pump
Vessel
Fig. 5.9 Diagram of calorimetric wattmeter designed in [155].
These tests demonstrate that the implementation of a double-jacketed enclosure in
the calorimeter could increase the accuracy considerably by active control of the air gap
temperature and by implementing automatic computer control.
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137
5.3.5. Calorimeter Based on Heat-flux Sensor
A simple and accurate apparatus for measuring the losses in a magnetic
component is presented in [138] (Fig. 5.10). A heat flux sensor is embedded inside a
pedestal on which the DUT is mounted. A liquid-cooled base plate serves as the heat
exchanger. The heat passing through the sensor generates a temperature difference
between the two sides of the sensor. The temperature difference is proportional to the
heat flux through the sensor and is converted to a voltage signal. A heat spreader
distributes the heat over the sensor area. The apparatus is designed such that almost all
the heat generated in the DUT passes through the heat flux sensor. Accuracy of the
instrument depends on how well this condition is satisfied.
1 2
3
5
47
6
7
Fig. 5.10 Schematic of calorimeter based on heat flux sensor.
1: aluminum base plate; 2: heat flux sensor; 3: heat spreader;
4: DUT; 5: aluminum cover; 6: fitting; 7: lead wires.
The liquid-cooled base plate allows most of the heat to flow downwards through
the heat flux sensor. The chamber is evacuated to minimize convection heat loss and
inside surfaces are polished to minimize the radiation heat loss through the cover. Factors
that affect the measurement accuracy were analyzed by using thermal analysis software.
The apparatus is suited for measuring power losses of relatively small components to
within ±5% error. This method is easier to implement and operate in comparison with the
calorimetric methods described above. It doesn’t need a liquid bath or a liquid flow
system and the thermal time constants are significantly shorter.
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138
5.3.6. Summary
From the discussion of various calorimeters above, it’s clear that every method
has its own features and advantages.
The open type calorimeter uses air as coolant, thus eliminating the risk of leaking
fluids. The cooling system is very simple, however, properties of air such as density and
specific heat are easily affected by ambient temperature, pressure and humidity. Air as
coolant is also more prone to uneven temperature distributions inside the chamber.
Therefore the open type calorimeter is unsuitable for a direct calorimetric measurement.
Although the balance calorimeter and the DCC calorimeter facilitates the applications of
the calorimetric method by eliminating the need for direct measurements of air density
and flow rate, problems such as heat leakage between two tests or chambers and great
temperature gradients still exist. These problems were addressed in [152], but at the
expense of significant increase in complexity and cost.
For the closed type calorimeter water or another fluid is used as coolant. The
density and specific heat of such coolants can be determined more accurately and are not
affected much by the changes in the environment. The volume and flow rate can also be
determined easily. Since the density and specific heat of such coolants are much larger
than those of air, the volume flow rate is much smaller for a given power loss, resulting
in smaller duct sizes and slower flow velocities. This method may therefore be used for a
direct calorimetric measurement or a balance test with better accuracy than that of the
open type calorimeters. Active temperature control by adding another insulating
enclosure and automatic computer control increases the measurement accuracy
considerably. However, liquid coolant and a heat exchanger are needed in the closed
cooling system, making this system complex and expensive.
The dry calorimeter based on heat-flux sensor is an effective and simple
construction. Fewer accessories are required compared to the other calorimeters, and the
testing time can be reduced because of small time constants.
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139
5.4. Proposed calorimeter for loss measurement
A new dry calorimeter with a heat flux sensor, but combining the features of the
double-jacketed, closed-type calorimeter, is presented for measuring power loss of the
active IPEMs, passive IPEMs and other integrated modules [170]. The DUT (device
under test) is placed in an air-tight chamber. The temperature difference between two
polished covers in the apparatus is controlled in order to reduce the heat escape caused by
convection and radiation. A heat flux sensor placed under the highly conductive pedestal
senses the total heat generated in the DUT. A pair of thermoelectric modules is
introduced to cool the DUT and control the operating temperature of the DUT. The heat
sink, TE modules and heat flux sensor together therefore replace the liquid cooling
systems that characterize the other calorimetric measuring methods. Compared with the
conventional cooling systems, thermoelectric modules have advantages such as the
absence of any moving parts, no need for coolant, no position-dependent, small size, high
reliability, and easy for control. The proposed calorimeter is easy to setup and operate,
losses up to 25 W can be measured with an expected error of less than 5%.
5.4.1. Introduction
A schematic diagram of the proposed calorimeter is shown in Fig. 5.11. The DUT
is mounted on a thermally conductive aluminum plate (plate I), under which a heat flux
sensor is mounted for sensing the overall heat generated in the DUT. Another aluminum
plate (plate II) is mounted beneath the heat flux sensor as a heat spreader. Below the plate
II are two thermoelectric (TE) modules well contacted with the heat sink. During
operation, the TE modules keep the temperature of plate II at a constant value, so the TE
modules are used to direct the heat flow through the heat flux sensor. The value of power
loss in the DUT can be obtained from the output voltage of the heat flux sensor. Two
highly polished aluminum covers minimize the radiation. Heaters are mounted on the
outer cover for the temperature control so that the temperature difference between two
covers can be reduced to minimize the heat escaping via the two covers. Fiberglass fills
Chapter5
140
the space between the two covers and surrounds the whole chamber. This apparatus is
designed so that all the heat generated in the DUT flow through the heat flux sensor. The
accuracy of the apparatus depends on how well this requirement is met.
1
6
12
7
9
10
2
3
4
5
8
Power Supply
Power Supply
TemperatureControlCircuits
11
Aluminum Fiber Glass PEEK
Fig. 5.11 Schematic of the proposed calorimeter.
1: DUT; 2: Inner Al cover; 3: Outer Al cover; 4: Al Base Plate I;
5: Al Base Plate II; 6: Heat sink; 7: Heater; 8: Thermocouple;
9: Fins; 10: Insulated material; 11. Heat flux sensor; 12: TE module.
Heat flux sensor
This sensor measures the rate of thermal energy flow per unit area (heat flux). In
the proposed apparatus, the sensor is placed between two aluminum plates with good
thermal contact. When heat flows through the sensor, a small temperature difference
develops across the multi-junction thermopile. Each thermocouple pair of the thermopile
produces a voltage proportional to heat flux. The total voltage across the thermopile is the
sum of these voltages and indicates the direction and magnitude of heat flux. The sensor
has the following advantages:
• low profile
• low thermal resistance
• easily attached to curved and flat surfaces
• wide temperature range
• fast response time
Chapter5
141
• conveniently interfaces with voltmeters or recorders
There are two types of heat flux sensors to choose from. One is HFS-4 from
Omega. The other one is BF-03 produced by Vatell Corporation .Some information of the
two sensors is listed in Table 5.2. HFS-4 was chosen as the heat flux sensor in our
proposed calorimeter.
Table 5.2 Date of heat flux sensors
Model Sensitivity
mV/(W/cm2)
Response
time (sec)
Thermal Resistance
K/(W/m2)
Thickness
(mm)
Size
(mm) Manufacturer
HFS-4 20.62 0.7 0.00352 0.23 35×28.6 Omega
BF-03 50 0.9 0.0008 0.2 51×51 Vatell Corp.
To take full advantage of the low thermal resistance of the heat flux sensor, it
should be mounted so that there is a good thermal contact between the sensor and the test
surface. A concerted effort should be made to prevent any air bubbles, dirt, or water from
becoming trapped between the sensor and the test surface. So the sensor should be
mounted on a smooth, clean, dry surface. A thin, uniform layer of the paste should be
applied to the sensor and then press the sensor gently to test surface. Use the smallest
amount of paste possible. Not only is excess paste messy, but also it can slow the
response time of the sensor.
Thermoelectric modules
A thermoelectric module is a semiconductor-based electronic component that
functions as a small heat pump. Four basic physical phenomena are related to the
operation of thermoelectric devices: The Seebeck effect, the Peltier effect, the Thomson
effect, and the Joule effect. The Seebeck effect means that the voltage is generated when
a temperature change is maintained between the two sides of a TEC. The Peltier effect is
the heating or cooling effect observed when an electrical current is passed through two
dissimilar junctions. The Thomson effect is heating or cooling effect in a homogeneous
conductor observed when an electrical current is passed in the direction of a temperature
gradient. This effect plays a negligible role in the operation of practical thermoelectric
Chapter5
142
modules. The Joule effect is the heating effect observed in a conductor as an electrical
current is passed through the conductor.
A typical TE module consists of two ceramic plates with several P-type and N-
type semiconductor elements connected electrically in series and thermally in parallel (as
shown in Fig. 5.12). The thermal model of the TE module is shown in Fig. 5.13, where
TH is the temperature of the hot side of the TE, TC is the temperature of the cold side of
the TE, V and I are input voltage and input current applied to the TE module, respectively
[171]. QC is the absorbed heat in the cold side, QH is the released heat in the hot side, and
Pe is the electric power supplied to the module.
CeH QPQ += ( 5.9)
VIPe = ( 5.10)
MchM RITTSV ×+−×= )( ( 5.11)
)(5.0 chMMcMc TTKRIITSQ −×−××−××= ( 5.12)
Fig. 5.12 Schematic of a TE module.
Chapter5
143
I2RM/2
Hot
side
cold
side
I2RM/2
SMThI
qh
qcSMTcI
KM
qh qc
Cold sideHot side
KM
SMTcI-I2RM/2
+
-
+
-
+
-VinSM(Th-Tc)
Pin
RM
TcTh
Fig. 5.13 Equivalent thermal model of TE module.
where MS is the Seebeck coefficient of the module (V/K), MR is the module’s
resistance (Ω), MK is thermal conductance of module (W/K).
By applying a low voltage DC power source to a TE module, heat will be moved
through the module from one side to the other, so one side becomes cold while the other
is heated. By varying the power to the TE module, TE module can be used to adjust and
control the heat flow and temperature. Two identical TE modules CZ1-1.4-127-1.14,
electrically in series and thermally in parallel, are used as cooler in the proposed
calorimeter to stabilize the temperature of the base plate II. The specifications for the
CZ1-1.4-127-1.14 are as follows: Imax =8 A, Qmax = 78 W, Vmax = 16.1 V, ∆Tmax =79 ºC.
The heat pumping capacity of the TE module significantly depends on the heat sink,
which must be capable of dissipating both the heat pumped by the module as well as the
heat losses generated as a result of supplying electrical power to the module. In the
proposed apparatus, an air-forced convection heat sink is employed to ensure TE
module’s performance.
5.4.2. Thermal analysis of the proposed calorimeter
A simple thermal model of the proposed apparatus is shown in Fig. 5.14. The
thermal model of the TE module is included, where TC is the cold side temperature and Th
Chapter5
144
is the hot side temperature, I is the input current applied to the TE modules. The heat
generated in the DUT flows downwards through the thermal resistance Rp1 of the base
plate I, thermal resistance Rfs of the heat flux sensor, thermal resistance Rp2 of the base
plate II, and through the TE modules and heat sink (Rhs) into the environment. A small
portion of the heat generated in the DUT escapes through the two covers (thermal
resistance Rio) into the ambient air.
RP1 Rfs RP2
TA
Ti TC
I2Rm/2 I2Rm/2αΙTC αΙTH
TH1/KmTo Rio
Roa
TP2Tin
Rhs
Two Covers
DUT
BasePlate I
Heat FluxSensor
BasePlate II Thermoelectric Modules Heat Sink
Fig. 5.14 Complete thermal model of the proposed calorimeter.
All of the heat flux that doesn’t pass through the flux sensor contributes to the
measurement errors. There are two main heat leakage paths in the proposed apparatus:
One is the heat leakage through the two covers and the other one is the conducted heat
along any power leads which connects the DUT to an external source.
Heat leakage through the two covers
The space between the inner cover and outer cover is full of thermal insulation
material (fiber glass). The heat leakage consists of conduction leakage and radiation
leakage. The radiation heat leakage is negligible. The heat leakage through the two
covers can be expressed as:
( )io
oinlc R
TTq −= ( 5.13)
where inT is the average temperature of the inner cover, oT is the average
temperature of the outer cover, and onR is the thermal resistance between two covers. If
the temperature difference between the two covers can be reduced, then the heat leakage
through the two covers will also be minimized. In the proposed measurement system,
heaters mounted on the outer cover are controlled to keep the temperature of the outer
Chapter5
145
cover close to that of the inner cover. By monitoring and controlling °<−=Δ 1oiio TTT C,
the heat leakage will be less than 0.24 W for the proposed calorimeter.
FEM thermal simulation results were obtained to compare the influence of heaters
on the heat leakage through the covers. Dimensions of the covers are listed in the Table
5.3. The simulation results for the proposed calorimeters in Fig. 5.15 are shown in Table
5.4. Without heaters on the outer cover, the temperature difference between the inner
cover and the outer cover is about 8.7°C, and the heat leakage through the two covers is
about 2.18W. When heaters are mounted on the surface of the outer cover, the
temperature difference between the two covers can be reduced to about 0.75°C, and the
heat leakage through the two covers is then only about 0.19W. Therefore the
measurement error of the calorimeter is greatly reduced when the temperature control is
introduced between the two covers. Therefore the measurement error is greatly reduced
when the temperature control is introduced between the two covers.
C
H
F
D
E
B
A
G
Fig. 5.15 Locations of temperature points of the calorimeter in the thermal simulations.
Table 5.3 Dimensions of the covers.
Diameter (mm) Height (mm) Thickness (mm)
Inner cover 200 150 5
Outer cover 270 180 5
Base cover 270 40 5
Chapter5
146
Table 5.4 Simulation results of the apparatus
Temperature (oC)
Without Heaters Control With Heaters control
A Base Plate I Bottom 36.0 36.0
B Base Plate I Top 42.4 43.7
C Device Top 127.3 129.4
D Inner Cover Side 48.9 49.8
E Outer Cover Side 40.1 49.0
F Inner Cover Top 48.4 49.6
G Out Cover Top 40.1 48.9
H Ambient 25.0 25.0
Heat leakage along the power leads
The heat leakage through thermocouple wires and power leads must also be
calculated to estimate the error of the measurement system. In [140], the conduction heat
loss along the wires is calculated assuming that the wire is cooled by natural convection.
To calculate the heat leakage through the wires, a steady-state thermal model of the
power leads is presented, as shown in Fig. 5.16. iT is the temperature of the wire’s high
temperature end. iT1 (i is from 1 to n) is temperature in the power leads. iT2 (i is from 1 to
n-1) is temperature on the insulation surface of the power leads. The thermal resistance
iR1 of the metal wire with length of dx is
4akdxR 2
wi1 /π
= ( 5.14)
and the thermal resistance iR2 of the insulation of the power lead with the length
of dx is
dxk2a
b2a
Ri
i2 π
⎟⎠⎞
⎜⎝⎛ +
=ln
( 5.15)
Chapter5
147
where kw is the thermal conductivity of the metal wire, ki is the thermal
conductivity of the insulation, a is the dimension of the metal wire, b is the thickness of
the insulation. The convection thermal resistance iR3 of the power lead with the length of
dx is
( )dxb2ah1R
ci3 +
=π ( 5.16)
where
( )⎟⎟⎠
⎞⎜⎜⎝
⎛+
=b2a
kNuh ac ( 5.17)
Nu is the Nusselt number, ka is the thermal conductivity of air. Nusselt number
can be calculated based on the empirical formula as the following: m
rr PGCNu )( ⋅⋅= ( 5.18)
where rG is Grashoff number and rP is Prandtl number.
Ti
TA
dxL
b
a
TATiR11 R12 R1nR13
R21 R22 R2(n-1)
R31 R32 R3(n-1)
T11 T12 T1(n-1)T13
T21 T22 T2(n-1)
Fig. 5.16 Thermal model of the power leads into the calorimeter.
Take an example, consider an insulated wire with L=0.2 m, a=1.09 mm, b=1 mm,
n=100, Ki=0.1 W/(m·oC), Ti=55 oC, TA=25 oC, we get Rtotal=168 oC/W from the thermal
model above. The heat leakage along the wire is then:
W180R
TTq
total
Aiw .=
−= ( 5.19)
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148
Also the analytical equation to calculate the heat leakage along the leads can be
derived as the following. Considering the energy balance on the wire with the length of
dx , we can get
)(|| aeqdxxcwxcw TTPdxhdxdTAk
dxdTAk −+−=− +
( 5.20)
then,
0TTAkPh
dxTd
acw
eq2
2
=−− )( ( 5.21)
where
ic
eq
kabaa
bahah
2)/2ln(
)2(
1+
++
= , which combines the thermal
resistance of the insulation layer and the convection resistance around the insulation
layer; aP π= , 4
2aAcπ
= .
Assuming the power lead loses heat from the end of the lead, the temperature
distribution and the total heat leakage along the wire can be obtained:
mLmkhmLxLmmkhxLm
TTTT
weq
weq
ai
a
sinh)/(cosh)](sinh[)/()](cosh[
+
−+−=
−−
( 5.22)
mLmkhmLmLmkhmL
TTAPkhqweq
weqaicweqw sinh)/(cosh
cosh)/(sinh)(
+
+−= ( 5.23)
where cw
eq
AkPh
m =2.
Some results are shown in figures (Fig. 5.17 ~ Fig. 5.19) below. The following
conclusions are made: The heat loss of the wire increases with increasing wire diameter,
and increases with the length of the wire when the wire’s length is small. But when the
length of the wire is beyond a critical value, the heat loss will almost remain constant.
Note that the insulation of the wire may actually increase the heat loss released from the
wire as a function of insulation thickness until heat loss reaches a maximum value at a
critical radius, beyond which the heat loss will start decreasing.
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149
0.5mm0.5mm
Length (m)
oC
1.09mm1.09mm
1.9mm1.9mm
Fig. 5.17 Temperature distribution for 3 diameters of the wire: 0.5 mm, 1.09 mm, and 1.9 mm when
b=1 mm.
0.5mm0.5mm
Insulation thickness (m)
Total heat loss (W)
1.09mm1.09mm
1.9mm1.9mm
Fig. 5.18 Total heat loss for 3 diameters of wire: 0.5 mm, 1.09 mm, and 1.9 mm.
Chapter5
150
Length (m)
Total heat loss (W)
0.5mm0.5mm
1.09mm1.09mm
1.9mm1.9mm
Fig. 5.19 Heat leakage as a function of length for given diameters: 0.5 mm, 1.09 mm, and 1.9 mm
when b = 1 mm.
In the conventional analysis of the heat loss along the wire where the effect of
convection is neglected and only the conduction heat transfer along the axial direction is
considered, the result is 05.0=wq W. This shows that the heat leakage along the wires is
underestimated by the conventional analysis.
5.4.3. Calibration and experiment
The design process of the calorimeter is described in Appendix III. Fig. 5.20
shows the prototype calorimeter.
Chapter5
151
Fig. 5.20 Prototype of the proposed calorimeter.
Calibration was performed by using a power resistor in place of the DUT and
subjecting it to a known DC power. The resistor was chosen for its ability to maintain
high accuracy over a wide temperature range. The measured power loss of the resistor as
a function of the heat flux sensor output in mV is given in Fig. 5.21. The calculated
power losses based on the sensor’s sensitivity are also plotted on the same graph. The
measured and calculated power losses are given in Table 5.5. The figures and tables show
good agreement with the calculated results.
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152
HFS-4 calibration curve
05
10152025303540455055606570
0 5 10 15 20 25 30
Power loss (W)
Out
put (
mV)
Theoretical valueMax measurementMin measurement
Fig. 5.21 Comparison between measured results and theoretical values.
Table 5.5 Calibration results
Input power (W) Theoretical (mV) Measured Max value Measured Min value Min error Max error
4.99±1.5% 12.89 12.84 12.32 3.88% 4.44%
10.04±1.5% 25.9 24.6 23.8 5.02% 8.10%
15.07±1.5% 38.95 38.2 37.44 1.92% 3.88%
20.02±1.5% 51.75 51.36 50.4 0.75% 2.6%
25.11±1.5% 64.9 63.48 63.2 2.2% 2.62%
5.5. Summary
Various power loss measurement techniques, including electrical and calorimetric
methods, are reviewed along with their advantages and disadvantages. The limits of
electrical power loss measurement techniques are analyzed. They are not suitable for high
efficiency systems due to the difficulty extracting losses from two nearly equal numbers.
Also electrical measurement methods are not suitable for high frequency signals due to
larger errors introduced by measuring equipments and interferences from the
environments.
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153
A simple dry type calorimeter for accurate power loss measurements was
developed, analyzed, tested and herein presented. Compared to other calorimetric
methods, it does not need a complex liquid cooling system. A heat flux sensor and
thermoelectric modules in the apparatus, in combination with simple control circuits,
make this structure compact and simple to use. The apparatus is easy to set up and very
cost-effective. Factors affecting the accuracy of the calorimeter were identified and
considered in its design and practical development. Double polished aluminum covers
with temperature difference control minimize the heat leakage through the covers, and the
inner test chamber is air-tight to minimize the heat leakage. Empirical calibration verifies
that the apparatus has an acceptable accuracy. The calorimeter is also suitable for other
low power losses measurement applications.
Chapter6
154
Chapter 6 Conclusion and Future Work
6.1. Conclusion
This thesis is an attempt to investigate the fundamental frequency limitations for
HF/VHF power conversion technology in order to optimize the power density and
efficiency as the frequency is pushed higher and higher. Major emphasis is placed on
fundamental investigations with regards to: power conversion structures, semiconductor
devices, passive components, and power loss measurement techniques. The major
accomplishments and conclusion are summarized below:
The existing state-of-the-art HF/VHF power conversion technologies were
briefly reviewed, focusing on their topologies, power levels, frequency
levels, dimensions, and implementation techniques. The trend of power
levels and frequencies is extracted to estimate the future development of
HF/VHF power conversion. Raising the frequency is a common method
for increasing power density. When frequency increases beyond a certain
range or value, the dimension of power converters begin to increase again
due to the complex interplay of design trade-offs, thus degrading the
power density. A fundamental limit responsible for the trade-off between
the power and frequency ultimately depends on the physical properties of
the semiconductor materials, i.e., critical breakdown field and saturated
drift velocity. It is this fundamental limitation being imposed by the
semiconductor devices that determines the upper bound of power level as
frequency increases. Semiconductor materials with higher breakdown field
and drift velocity have larger power-frequency products. This indicates
that in order to optimize the power density in the future as frequency
increases it is necessary to apply new materials with higher breakdown
field and drift velocity into the semiconductor devices, besides the
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155
advances in other constituent technologies.
A DC-DC power converter (derived from the RF Class E power amplifier),
which is very suitable for VHF power conversion and that dominates the
higher end of the frequency scale, is analyzed with a detailed discussion
and derivation of design equations. A 250 MHz prototype (implemented
using discrete surface-mounted components) is demonstrated along with
the experiment results, which achieves the highest frequency among the
discrete power converters ever found in the literature.
Power losses, including conduction loss and switching loss, in the
semiconductor devices can be represented by ON-resistance and device
capacitance. The smaller the product of ON-resistance and device
capacitance is, the higher the efficiencies of HF power architectures can be.
In order to improve the efficiency of power conversion system, the product
of ON-resistance and device capacitance should be minimized. By relating
the product to the intrinsic material properties, the power loss can be
reduced by using semiconductor materials exhibiting a larger breakdown
field and a larger mobility whilst the die area is also reduced. When the
semiconductor material is given, the minimum power loss in the device
will increase with increasing frequency, leading to lower efficiency of the
system. And the device die area at which the minimum power loss occurs
is reduced with switching frequency.
A generic multi-disciplinary model was constructed and then used to
analyze the performances of passive components (i.e. power density and
power conversion efficiency) as functions of frequency. For magnetic
components, there is an optimum frequency (or frequencies) at which the
power density and power conversion efficiency is maximized, and beyond
which the reverse is true. It was demonstrated how this optimum
frequency (or frequency limit) can be identified, and how power
Chapter6
156
conversion efficiency deteriorates beyond the optimum under a fixed
maximum temperature. Therefore further increases in operating
frequencies to improve power density are not always beneficial in terms of
power density. The frequency scaling investigation of passive components
(capacitors and magnetics) shows how frequency dependencies of material
properties are responsible for high frequency operation. The method can
be extended to identify the most optimum power conversion frequency for
a given set of specifications, circuit functions, selection of materials and
packaging technology, and thermal conditions.
Using the results from the fundamental limitations of the power devices
and passive components in the power converter, the power density and
efficiency as a function of frequency scaling is plotted in Fig. 6.1. It is
clear that pursuing high frequency alone doesn’t necessarily lead to
improved power density and efficiency. Some compromises must be made
between different requirements with respect to specific applications.
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157
Fig. 6.1 Power density and efficiency variation with switching frequency.
The limitations of electrical loss measurement techniques are analyzed,
exhibiting large error for high-efficiency, high-frequency power
electronics system. Various calorimetric methods for loss measurement are
reviewed, demonstrating reduced errors due to the direct measurement of
thermal heat flux. A new advanced calorimetric measurement system for
accurate power loss measurement is proposed, analyzed and tested.
Compared to other calorimetric methods, it does not need a complex liquid
cooling system. A heat flux sensor and thermoelectric modules, in
combination with simple control circuits, make this system compact and
easy to use. It has the ability to measure heatsink-mounted components
such as IPEMs, passive IPEMs and integrated magnetics. The calibration
of the calorimetric system demonstrates about 5% error in up to 25 W total
Chapter6
158
losses.
6.2. Future work
The investigation of fundamental frequency limitations for HF/VHF power
conversion is a quite broad, complex and systematic subject, requiring knowledge from
many different disciplines in the different fields related to power electronics system. In
order to continue pushing the trend towards miniaturization of power converter, the other
fundamental limitations in packaging, integration, interconnects and thermal management
technologies should be further investigated, identified and optimized for optimum
performances of the power converter. The guidelines and design tools demonstrated in
the dissertation can be extended to the future work as the follows.
(1) Evaluation of new semiconductor devices for HF/VHF power conversion.
New semiconductor devices with better material properties than those of silicon
should be evaluated in the power converter for their performances in terms of power level,
efficiency, frequency, power density.
(2) Further improvement of Class E RF DC-DC power converter for better
efficiency and power density.
Class E RF DC-DC power converter demonstrates promising potential for VHF
power conversion. It is necessary to apply new devices and new control strategies (such
as the multi-switching cell concepts) in a higher level of integration techniques to achieve
higher efficiency, increased power and higher power density.
(3) Optimization of power density or efficiency through the optimization of
passive and active components by frequency selection at the system level design stage.
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159
Based on the present available high frequency power devices, magnetic materials
and dielectric materials, evaluate some frequency ranges for optimum power density or
efficiency at different power levels. If necessary, investigate the feasible frequency range
for the applications of air core magnetic components.
References
160
References
Chapter 1 & 2:
[1] R.J. Huljak, V.J. Thottuvelil, A.J. Marsh, B.A. Miller, “Where are power supplies
headed?” Fifteenth Annual IEEE on APEC 2000, vol. 1, pp. 10 – 17, 2000.
[2] A.W. Lotfi, M.A. Wilkowski, “Issues and advances in high-frequency magnetics for
switching power supplies,” Proceedings of the IEEE, vol. 89, no. 6, pp. 833 – 845, 2001.
[3] J.D. van Wyk, “Power electronics technology at the dawn of a new century – past
achievements and future expectations,” Proceedings of 3rd International Power
Electronics and Motion Control Conference (PIEMC), vol. 1, pp. 9 – 20, 2000.
[4] S. Musunuri, P.L. Chapman, J. Zou, C. Liu, “Design Issues for Monolithic DC–DC
Converters,” IEEE Transactions on Power Electronics, vol. 20, no. 3, pp. 639 – 649, May
2005.
[5] A. Lidow, D. Kinzer, G. Sheridan, D. Tam, “The semiconductor roadmap for power
management in the new millennium,” Proceedings of the IEEE, vol. 89, no. 6, pp. 803 –
812, June 2001.
[6] H. Ohashi, “Power Electronics Innovation with Next Generation Advanced Power
Devices,” The 25th International Telecommunications Energy Conference (INTELEC ‘03),
pp. 9 – 13, 19-23 Oct. 2003.
[7] S.C.O., Mathuna, T. O’Donnell, N. Wang, K. Rinne, “Magnetics on Silicon: An
Enabling Technology for Power Supply on Chip,” IEEE Transactions on Power
Electronics, vol. 20, no. 3, pp. 585-592, May 2005.
[8] S.C.O., Mathuna, P. Byrne, G. Duffy, W. Chen, M. Ludwig, T. O’Donnell, P.
McCloskey, M. Duffy, “Packaging and integration technologies for future high-frequency
power supplies,” IEEE Transactions on Industrial Electronics, vol. 51, no. 6, pp. 1305 –
1312, Dec. 2004.
References
161
[9] E. Waffenschmidt, B. Ackermann, J.A. Ferreira, “Design method and material
technologies for passives in printed circuit board embedded circuits,” IEEE Transactions
on Power Electronics, vol. 20, no. 3, pp. 576 – 584, May 2005.
[10] P. Dhagat, S. Prabhakaran, C.R. Sullivan, “Comparison of magnetic materials for V-
groove inductors in optimized high-frequency DC-DC converters,” IEEE Transactions on
Magnetics, vol. 40, no. 4, pp. 2008 – 2010, July 2004.
[11] Kim Yong-Jun, M.G. Allen, “Surface micromachined solenoid inductors for high
frequency applications,” IEEE Transactions on Components, Packaging, and
Manufacturing Technology, Part C, vol. 21, no. 1, pp. 26 – 33, January 1998.
[12] W. Y. Liu, J. Suryanarayanan, J. Nath, S. Mohammadi, L.P.B. Katehi, M.B. Steer,
“Toroidal inductors for radio-frequency integrated circuits,” IEEE Transactions on
Microwave Theory and Techniques, vol. 52, no. 2, pp. 646 – 654, Feb. 2004.
[13] W.J. Sarjeant, I.W. Clelland, R.A. Price, “Capacitive components for power
electronics,” Proceedings of the IEEE, vol. 89, no. 6, pp. 846 – 855, June 2001.
[14] S. Wang, M.A. D. Rooij, W.G. Odendaal, J.D. van Wyk, D. Boroyevich, “Reduction
of high-frequency conduction losses using a planar litz structure,” IEEE Transactions on
Power Electronics, vol. 20, no. 2, pp. 261 – 267, 2005.
[15] S. Djukic, D. Maksimovic, Z. Popovic, “Planar C-band DC-DC converter,”1999
IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 827 – 830, 13-19
June 1999.
[16] S. Djukic, D. Maksimovic, Z. Popvic, “ A planar 4.5-GHz DC-DC power
converter,” IEEE Transactions on Microwave Theory and Techniques, vol. 47, no. 8, pp.
1457 – 1460, 1999.
[17] T. Suetsugu, S. Kiryu, M. K. Kazimierczuk, “ Feasibility study of on-chip class E
DC-DC converter,” Proceedings of the ISCAS ‘03, vol. 3, pp. 443-446, 2003.
[18] J. M. Rivas, R. S. Wahby, J. S. Shafran, D. J. Perreault, “ New architectures for
radio-frequency dc/dc power conversion,” IEEE 35th Annual PESC’04, vol. 5, pp. 4074 –
4084, 2004.
References
162
[19] R.S. Wahby, “Radio frequency rectifiers for DC/DC power conversion,” MS Thesis,
MIT, May 2004.
[20] M. Ohadi, Jianwei Qi, “Thermal management of harsh-environment electronics,”
Twentieth Annual IEEE on Semiconductor Thermal Measurement and Management
Symposium, pp. 231 – 240, 2004.
[21] N.O. Sokal, A.D. Sokal, “Class E-A new class of high-efficiency tuned single-ended
switching power amplifiers,” IEEE Journal of Solid-State Circuits, vol. 10, no. 3, pp. 168
– 176, Jun 1975.
[22] F. Raab, “Idealized operation of the class E tuned power amplifier,” IEEE
Transactions on Circuits and Systems, vol. 24, no. 12, pp.725–735, 1977.
[23] N.O. Sokal, “Class E high-efficiency power amplifiers, from HF to microwave,”
1998 IEEE MTT-S International Microwave Symposium Digest, vol. 2, pp. 1109 – 1112,
June 1998.
[24] R.J. Gutmann, “Application of RF circuit design principles to distributed power
converters,” IEEE Transactions on Industrial Electronics & Control Instrumentation, vol.
IECI-27, no. 3, pp. 156 – 164, 1980.
[25] R. Redl, B. Molnar, N.O. Sokal, “Class-E resonant regulated DC/DC power
converters: analysis of operation, and experimental results at 1.5 MHz,” IEEE Power
Electronics Specialists Conference, pp. 50 – 60, 1983.
[26] M.K. Kazimierczuk, D. Czarkowski, Resonant Power Converters, John Wiley&Sons,
1995.
[27] M. Kazimierczuk, K. Puczko, “Exact analysis of class E tuned power amplifier at
any Q and switch duty cycle,” IEEE Transactions on Circuits and System, vol. 34, no. 2,
pp. 149 – 159, Feb. 1987.
[28] M.K. Kazimierczuk, “Analysis of class E zero-voltage-switching rectifier,” IEEE
Transactions on Circuits and Systems, vol. 37, no. 6, pp.747–755, 1990.
[29] P. Khandelwal, M. Trivedi, K. Shenai, S.K. Leong, “Thermal and package
performance limitations in LDMOSFET’s for RFIC applications,” IEEE Transactions on
Microwave Theory and Techniques, vol. 47, no. 5, pp. 575 – 585, 1999.
References
163
[30] K.H. Liu, F.C. Lee, “Zero-voltage switching technique in DC/DC converters,” IEEE
Transactions on Power Electronics, vol. 5, no. 3, pp. 293 – 304, 1990.
[31] R. Redl, B. Molnar, N. Sokal, “Class-E resonant regulated DC/DC power converters:
analysis of operation, and experimental results at 1.5 MHz,” IEEE PESC Record, pp. 50
– 60, 1983.
[32] R.J. Gutmann, “Application of RF circuit design principles to distributed power
converters,” IEEE Transactions on Industrial Electronics and Control Instrumentation,
vol. IECI-27, no. 3, 1980.
[33] R. Kollman, G. Collins, D. Plumton, “10MHz PWM converters with GaAs VFETS,”
IEEE APEC 1996, vol. 1, pp. 264 – 269.
[34] A. Goldberg, J. Kassakian, “The applications of power MOSFETs at 10 MHz,”
IEEE PESC Record, pp. 91 – 100, 1985.
[35] D. Guckenberger, K. Kornegay, “Integrated DC-DC converter design for improved
WCDMA power amplifier efficiency in SiGe BiCMOS technology,” Proceedings of the
ISLPED’03, pp. 449 – 454, 2003.
[36] “What’s high density – brick sizes?” Switching Power Magazine, vol. 4, no. 1, pp. 7
– 17, 2003.
[37] W.A. Tabisz, P. M. Gradzki, F. C. Lee, “ Zero-voltage-switched Quasi-resonant
buck and flyback converters - experimental results at 10 MHz,” IEEE Trans. on Power
Electronics, vol. 4, no. 2, pp. 194 – 204, 1989.
[38] G. Hanington, P.F. Chen, V. Radisic, T. Itoh, P. M. Asbeck, “Microwave power
amplifier efficiency improvement with a 10 MHz HBT DC-DC converter,” IEEE MTT-S
International Microwave Symposium Digest, vol. 2, pp. 589 – 592, 1998.
[39] M. Gaye, S. Ajram, P. Maynadier, G. Salmer, “An ultra-high switching frequency
step-down DC-DC converter based on Gallium Arsenide devices,” Gallium Arsenide
applications symposium. GAAS 2000, 2-6 october 2000, Paris.
[40] S. Ajram, R. Kozlowski, H. Fawaz, D. Vandermoere, G. Salmer, “A fully GaAs-
based 100 MHz, 2W DC-to-DC power converter,” 1997.
References
164
[41] S. Ajram, R. Kozlowski, and G. Salmer, “Application of III-V power devices for
DC/DC power conversion,” Electronics Letters, vol. 32, no. 1, pp. 67 – 68, Jan. 1996.
[42] S. Ajram, G. Salmer, “Ultrahigh frequency DC-to-DC converters using GaAs power
switches,” IEEE Trans. On Power Electronics, vol. 16, no. 5, pp. 594 – 602, Sept. 2001.
[43] M.Gaye, S. Ajram, J. Lebas, R. Kozlowski, and G. Salmer, “A 50 – 100 MHz 5V To
-5V, 1W Cuk converter using Gallium Arsenide power switches,” ISCAS 2000 – IEEE
International Symposium on Circuits and Systems, vol. 1, pp. 264 – 267, May 200,
Geneva, Switzerland.
[44] J. Biernacki, D. Czarkowski, “Radio Frequency DC-DC flyback converter,”
Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 1, pp.
94 – 97, 2000.
[45] S. Abedinpour, S. Kiaei, “Monolithic distributed power supply for a mixed-signal
integrated circuit,” Proceedings of the ISCAS’03, vol. 3, pp. 308-311, 2003.
[46] V. Kursun, S. G. Narendra, V. K. De, E. G. Friedman, “High input voltage step-
down DC-DC converters for integration in a low voltage CMOS Process,” Proceedings
of 5th International Symposium on Quality Electronic Design, pp. 517-521, 2004.
[47] V. Kursun, S. G. Narendra, V. K. De, E. G. Friedman, “Analysis of buck converters
for on-chip integration with a dual supply voltage microprocessor,” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp. 514-522, 2003.
[48] V. Kursun, S. G. Narendra, V. K. De, E. G. Friedman, “Monolithic DC-DC
converter analysis and MOSFET gate voltage optimization,” Proceedings of 4th
International Symposium on Quality Electronic Design, pp. 279 – 284, 2003.
[49] G. Schrom, P. Hazucha, J. Hahn, D. S. Gardner, B. A. Bloechel, G. Dermer, S. G.
Narendra, T. Karnik, V. De, “A 480 MHz, Multi-phase interleaved Buck DC-DC
converter with hysteresis control,” IEEE 35th Annual PESC’04, vol. 6, pp. 4702 – 4707,
2004.
[50] P. Hazucha, G. Schrom, J. Hahn, B.A. Bloechel, P. Hack, G.E. Dermer, S. Narendra,
et al., “A 233-MHz 80%-87% efficiency four-phase DC-DC converter utilizing air-core
inductors on package,” IEEE J. of Solid-state Circuits, vol. 40, no. 4, pp. 838 – 845, 2005.
References
165
[51] G. Schrom, P. Hazucha, J. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik, V.
De, “Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in
90 nm technology generation,” Proceedings of the 2004 International Symposium on Low
Power Electronics and Design, ISLPED '04, pp. 263 – 268, 2004.
[52] D. Gardner, A.M. Crawford, S. Wang, “High frequency (GHz) and low resistance
integrated inductors using magnetic materials,” Proceedings of the IEEE 2001
International on Interconnect Technology Conference, pp. 101 – 103, 2001.
[53] V. Kursun, S. G. Narendra, V. K. De, E. G. Friedman, “Low-voltage-swing
monolithic DC-DC conversion,” IEEE Trans. On Circuits and Systems –II: Express
Briefs, vol. 51, no. 5, pp. 241 – 248, 2004.
[54] R.J. Gutmann, “Application of RF circuit design principles to distributed power
converters,” IEEE Trans. On Industrial Electronics & Control Instrumentation, vol.
IECI-27, no. 3, pp. 156 – 164, 1980.
[55] R. Redl, B. Molnar, N.O. Sokal, “Class-E resonant regulated DC/DC power
converters: analysis of operation, and experimental results at 1.5 MHz,” IEEE PESC
Record, pp. 50 – 60, 1983.
[56] W.C. Bowman, J.F. Balicki, F.T. Dickens, R.M. Honeycutt, W.A. Nitz, W. Strauss,
W.B. Suiter, N.G. Ziesse, “A resonant DC-to-DC converter operating at 22 Megahertz,”
Conference Proceedings of 3rd Annual IEEE APEC, pp. 3 – 11, 1988.
[57] N.O. Sokal, A.D. Sokal, “Class E – a new class of high-efficiency tuned single-
ended switching power amplifier,” IEEE Journal Solid-state Circuits, vol. SC-10, no. 3,
pp. 168 – 175, 1975.
[58] N.O. Sokal, A.D. Sokal, “Class E switching-mode RF power amplifiers – low power
dissipation, low sensitivity to component tolerances (including transistors), and well-
defined operation,” RF Design, vol. 3, no. 7, pp. 33 – 38, 41, 1980.
[59] S. Djukic, D. Maksimovic, Z. Popvic, “A planar 4.5-GHz DC-DC power converter,”
IEEE Transactions on Microwave Theory and Techniques, vol. 47, no. 8, pp. 1457 –
1460, 1999.
[60] T. Suetsugu, S. Kiryu, M. K. Kazimierczuk, “Feasibility study of on-chip class E
DC-DC converter,” Proceedings of the ISCAS '03, vol. 3, pp. 443-446, 2003.
References
166
[61] J. M. Rivas, R. S. Wahby, J. S. Shafran, D. J. Perreault, “New architectures for
radio-frequency dc/dc power conversion,” IEEE 35th Annual PESC’04, vol. 5, pp. 4074 –
4084, 2004.
[62] M. Iwadare, S. Mori, K. Ikeda, “Even harmonic resonant ZVS-class E tuned
amplifier without RF choke,” Pro. European Conference on Circuit Theory and Design
(ECCTD’93), pp. 1211 – 1216, 1993.
[63] P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog
Integrated Circuits, 4th Edition, John Wiley&Sons, 2001.
[64] E.O. Johnson, “Physical limitations on frequency and power parameters of
transistors,” IRE International Convention Record, vol. 13, no. 5, pp. 27-34, 1965.
Chapter 3:
[65] M.K. Kazimierczuk, D. Czarkowski, Resonant Power Converters, John Wiley&Sons,
1995.
[66] M. Kazimierczuk, K. Puczko, “Exact analysis of class E tuned power amplifier at
any Q and switch duty cycle,” IEEE Transactions on Circuits and System, vol. 34, no. 2,
pp. 149 – 159, Feb. 1987.
[67] M. Albulet, RF Power Amplifiers, Nobel Publishing Company, 2001.
[68] R.E. Zulinski, J.W. Steadman, “Class E power amplifiers and frequency multipliers
with finite DC-feed inductance,” IEEE Transactions on Circuits and System, vol. 34, no.
9, pp. 1074 – 1087, 1987.
[69] F.H. Raab, N.O. Sokal, “Transistor power losses in the Class E tuned power
amplifier,” IEEE J. Solid-state circuits, vol. SC-13, no. 6, pp. 912 – 914, 1978.
[70] N. O. Sokal, “Class E high-efficiency power amplifiers, from HF to microwave,”
1998 IEEE MTT-S International on Microwave Symposium Digest, vol. 2, pp. 1109 –
1112, 1998.
[71] C.P. Avratoglou, N.C. Voulgaris “A new method for the analysis and design of the
class E power amplifier taking into account the QL factor,” IEEE Trans. Circuits and
System, vol. CAS-34, no. 6, pp. 687 – 691, 1987.
References
167
[72] F.H. Raab, “Idealized operation of the Class E tuned power amplifier,” IEEE Trans.
Circuits and Systems, vol. CAS-24, no. 12, pp. 725 – 735, 1977.
[73] D.J. Kessler, M. Kazimierczuk, “Power losses and efficiency of Class-E power
amplifier at any duty ratio,” IEEE Transactions on Circuits and Systems –I: regular
papers, vol. 51, no. 9, pp. 1657 – 1689, Sept. 2004.
[74] P. Alinikula, “Optimum component values for a lossy class E power amplifier,”
IEEE MTT-S International on Microwave Symposium Digest, vol. 3, pp. 2145 – 2148,
Jun. 2003.
[75] S.A. El-Hamamsy, “Design of high-efficiency RF Class-D power amplifier,” IEEE
Trans. Power Electronics, vol. 9, no. 3, pp. 297 – 308, 1994.
[76] D.V. Chernov, M. Kazimierczuk, V.G. Krizhanovski, “Class-E MOSFET low-
voltage power oscillator,” IEEE International Symposium on Circuits and Systems, vol. 5,
pp. V-509 – V-512, May 2002.
[77] J. Ebert, M. Kazimierczuk, “Class E high-efficiency tuned power oscillator,” IEEE
Journal on Solid-state Circuits, vol. SC-16, no. 2, pp. 62 – 66, 1981.
[78] M. Kazimierczuk, V.G. Krizhanovski, J.V. Rassokhina, D.V. Chernov, “Class-E
MOSFET tuned power oscillator design procedure,” IEEE Transactions on Circuits and
Systems –I: regular papers, vol. 52, no. 6, pp. 1138 – 1147, 2005.
[79] M. Matsuo, H. Sekiya, T. Suetsugu, K. Shinoda, S. Mori, “Design of a high-
efficiency Class DE tuned power oscillator,” IEEE Transactions on Circuits and Systems
–I: Fundamental theory and applications, vol. 47, no. 11, pp. 1645 – 1649, 2000.
[80] C.J. Georgopoulos, RF and Microwave Matching Techniques, Interference Control
Technologies, Inc., 1990, ISBN 0-944916-14-7.
[81] N. Dye, H. Granberg, Radio Frequency Transistors: Principles and Practical
Applications, 2nd Edition, published by Newnes, 2000, ISBN 0-7506-7281-1.
[82] Y. Tan, M. Kumar, J.K.O. Sin, J. Cai, J. Lau, “A LDMOS technology compatible
with CMOS and passive components for integrated RF power amplifiers,” IEEE Trans.
Electron Device Letters, vol. 21, no. 2, pp. 82 – 84, 2000.
[83] I. Bahl, Lumped elements for RF and microwave circuits, Artech House, 2003, ISBN
1-5805-309-4.
[84] http://www.coilcraft.com/pdfs/mini.pdf
References
168
[85] http://www.analog.com.tw/DB/doc/app_note/an017.pdf
[86] User’s Reference, Maxwell Quick 3D Parameter Extractor, Ansoft Co., 2001. [87] A. Ruehli, C. Paul, J. Garrett, “Inductance calculations using partial inductances and
macromodels,” IEEE International Symposium on Electromagnetic Compatibility, pp.
23-28, August 1995.
[88] Jingen Qian, “RF Models for Active IPEMs,” Master Thesis, Virginia Polytechnic
Institute and State University, January 2003.
[89] Liyu Yang, “Modeling and Characterization of a PFC Converter in the Medium and
High Frequency Ranges for Predicting the Conducted EMI ,” Master Thesis, Virginia
Polytechnic Institute and State University, September 2003.
[90] Kalyan C. Siddabattula, “Electromagnetic modeling of packaging layout in power
electronic modules,” Master Thesis, Virginia Polytechnic Institute and State University,
Dec 1999.
[91] Wei Zhang, “Integrated EMI/Thermal Design for Switching Power Supplies,”
Master Thesis, Virginia Polytechnic Institute and State University, Feb 1998.
[92] L.D. Smith, D. Hockanson, K. Kothari, “A Transmission-line model for ceramic
capacitors for CAD tools based on measured parameters,” 52nd Proceedings of Electronic
Components and Technology Conference, pp. 331 - 336, 2002.
[93] L.D. Smith, D. Hockanson, “Distributed SPICE circuit model for ceramic
capacitors,” 51st Proceedings of Electronic Components and Technology Conference, pp.
523 - 528, 2001.
[94] M.Ingalls, G. Kent, “Monolithic capacitors as transmission lines,” IEEE Trans. on
Microwave and Techniques, vol. MTT – 35, no. 11, pp. 964 - 970, 1987.
[95] J. Mondal, “An experimental verification of a simple distributed model of MIM
capacitors for MMIC applications,” IEEE Trans. on Microwave and Techniques, vol.
MTT – 35, no. 4, pp. 403 - 408, 1987.
[96] T. Suetsugu, M.K. Kazimierczuk, “Analysis and design of Class E amplifier with
shunt capacitance composed of nonlinear and linear capacitances,” IEEE Trans. on
Circuits and Systems – I: regular papers, vol. 51, no. 7, pp. 1261 - 1268, 2004.
References
169
[97] P. Alinikula, K. Choi, S.I. Long, “Design of Class E power amplifier with nonlinear
parasitic output capacitances,” IEEE Trans. on Circuits and Systems – II: analog and
digital signal processing, vol. 46, no. 2, pp. 114 - 119, 1999.
[98] H. Sekiya, Y. Arifuku, H. Hase, J. Lu, T. Yahagi, “Design of Class E amplifier with
any output Q and nonlinear capacitance on MOSFET,” Proceedings of the 2005
European Conference on Circuit theory and design, vol. 3, pp. 105 - 108, 2005.
[99] C.K. Thomas, C. Toumazou, “Design of a Class E power amplifier with non-linear
transistor output capacitance and finite DC-feed inductance,” The 2001IEEE
International Symposium on Circuits and Systems (ISCAS 2001), vol. 1, pp. 129 - 132,
2001.
[100] B.J. Baliga, “Power semiconductor device figure of merit for high-frequency
applications,” IEEE Electron Device Letters, vol. 10, no. 10, pp. 455-457, 1989.
Chapter 4:
[101] W.G. Odendaal, “A Generic Approach for the Modelling of High Power Density
Magnetic Components,” PhD Dissertation, Rand Afrikaans University, May 1997.
[102] W.G. Odendaal, J. Azevedo, G.W. Bruning, R.M. Wolf, “A high-efficient magnetic
component with superior caloric performce for low-profile high-density power
conversion,” IEEE Trans. Industry Applications, vol. 40, no. 5, pp. 1287 - 1293, 2004.
[103] W.G. Odendaal, J.A. Ferreira, “Effects of scaling high-frequency transformer
parameters,” IEEE Trans. Industry Applications, vol. 35, no. 4, pp. 932 - 940, 1999.
[104] W.G. Odendaal, J.A. Ferreira, “A thermal model for high-frequency magnetic
components,” IEEE Trans. Industry Applications, vol. 35, no. 4, pp. 924 - 931, 1999.
[105] Chucheng Xiao, W.G. Odendaal, J.A. Ferreira, “Frequency scaling effects of
integrated passive components in high frequency power conversion,” IEEE IAS 2006.
[106] F.C. Lee, J.D. van Wyk, D. Boroyevich, P. Barbosa, “An integrated approach to
power electronics systems,” Proceedings of the Power Conversion Conference (2002
PCC), vol. 1, pp. 7 - 12, 2002.
References
170
[107] J.D. van Wyk, F.C. Lee, Z. Liang, R. Chen, S. Wang, B. Lu, “Integrating active,
passive and EMI-filter functions in power electronics systems: a case study of some
technologies,” IEEE Trans. on Power Electronics, vol. 20, no. 3, pp. 523 - 532, 2005.
[108] A.A. Jaecklin, “Future devices and modules for power electronic applications,”
fifth European Conference on Power Electronics and Applications, vol. 1, pp. 1 - 8, 1993.
[109] Y. Nanishi, “Recent development of nitride semiconductor electronic devices for
next generation wireless communications,” 4th International Workshop on Junction
Technology (IWJT’04), pp. 12 - 17, 2004.
[110] Alessandro Chini, “Fabrication, characterization and reliability of AlGaN/GaN
HEMTs for power microwave applications”.
[111] R. Allison, “Silicon Bipolar Microwave Power Transistors,” IEEE Transactions on
Microwave Theory and Techniques, vol. MTT-27, no. 5, pp. 415 - 422, 1979.
[112] J.A. Ferreira, J.D. Van Wyk, “Electromagnetic energy propagation in power
electronic converters: toward future electromagnetic integration,” Proceedings of the
IEEE, vol. 89, no. 6, pp.876–889, 2001.
[113] J.A. Ferreira, “Engineering science considerations for integration and packaging,”
Record of IEEE 31st Annual Power Electronics Specialists Conference, vol. 1, pp. 12-18,
2000.
[114] J.P. Homan, Heat Transfer, 9th Edition, published by MCGraw-Hill, 2002.
[115] E.C. Snelling, A.D. Giles, “Ferrites for inductor and transformer,” published by
Research studies Press LTD, 1983.
[116] L. Dalessandro, W.G. Odendaal, J.W. Kolar, “HF characterization and non-linear
modeling of a gapped toroidal magnetic structure,” IEEE 36th Conference on Power
Electronics Specialists, pp. 1520 – 1527, 2005.
[117] M.T. Johnson, E.G. Visser, “A coherent model for the complex permeability in
polycrystalline ferrites,” IEEE Trans. On Magnetics, vol. 26, no. 5, pp. 1987 – 1989, Setp.
1990.
[118] M. Yamaguchi, S. Arakawa, H. Ohzeki, Y. Hayashi, K.I. Arai, “Characteristics and
analysis of a thin film inductor with closed magnetic circuit structure,” IEEE Trans. On
Magnetics, vol. 28, no. 5, pp. 3015 – 3017, Setp. 1992.
References
171
[119] O. Oshiro, H. Tsujimoto, K. Shirae, “High frequency characteristics of a planar
inductor and a magnetic coupling control device,” IEEE Trans. On Magnetics in Japan,
vol. 6, no. 5, pp. 436 – 442, 1991.
[120] M. Heshmatzadeh, X. Zhou, G. Bridges, G. Williams, “High-frequency giant
magnetoimpedance measurement and complex permeability behavior of soft magnetic
Co-based ribbons,” IEEE Trans. On Magnetics, vol. 41, no. 8, pp. 2328 – 2333, 2005.
[121] S.O. Kasap, “Principles of Electronic Materials and Devices,” 2nd Edition,
McGraw-Hill.
[122] M.W. Barsoum, “Fundamentals of Ceramics,” IoP Publishing Ltd 2003, ISBN 0-
7503-0902-4.
[123] Kwan Chi Kao, “Dielectric Phenomena in Solids with Emphasis on Physical
Concepts of Electronic Processes,” Elsevier Academic Press, 2004.
[124] D.F. Kelley, R.J. Luebbers, “Debye function expansions of empirical models of
complex permittivity for use in FDTD solutions,” IEEE on Antennas and Propagation
Society International Symposium, vol. 4, pp. 372 – 375, 2003.
[125] A.J. Moulson, J.M. Herbert, “Electroceramics: materials, properties and
applications,” John Wiley & Sons Ltd., 2003.
[126] R.E. Lafferty, “Capacitor loss at radio frequencies,” IEEE Transactions on
Components, Hybrid, and Manufacturing Technology, vol. 15, no. 4, pp. 590 –593, 1992.
[127] Yovanovich, M.M., Culham, J. R., Teertstra, P., “ Calculating interface
resistance”, Electronics Cooling, May 1997.
Chapter 5:
[128] Chucheng Xiao, Lingyin Zhao, T. Asada, W.G. Odendaal, J.D. van Wyk, “An
overview of integratable current sensor technologies,” 38th IAS Annual Meeting
Conference Record of the Industry Applications Conference, vol.2. pp. 1251 – 1258,
2003.
[129] Instructions of P5050 10X Passive Probe, 071-1018-01, www.tektronix.com.
References
172
[130] D.C. Smith, “High frequency measurements and noise in electronic circuits,” Van
nostrand Reinhold – New York, 1993.
[131] S. Mukherjee, R.G. Hoft, J.A. McCormick, “Digital measurement of the efficiency
of inverter-induction machines,” IEEE Trans. on Industry Applications, vol.26. no.5, pp.
872 – 879, 1990.
[132] R. Perret, C. Schaeffer, E.Farjah, “Temperature evolution in power semiconductor
devices: measurement techniques and simulation,” IEE Colloquium on Measurement
techniques for power electronics, 1992.
[133] L. Peretto, R. Sasdelli, G. Serra, “Measurement of harmonic losses in transformers
supplying nonsinusoidal load currents,” IEEE Trans. Instrum. & Meas., vol.49, no.2, pp.
315 - 319, April 2000.
[134] N.Schmidt, H.Guldner, “A simple method to determine dynamic hysteresis loops of
soft magnetic materials,” IEEE Trans. Magnetics, vol. 32, no. 2, pp. 489 - 496, March
1996.
[135] F.D.Tan, J.L.Vollin, S.M.Cuk, “A practical approach for magnetic core-loss
characterization,” IEEE Trans. Power Electronics, vol. 10, no. 2, pp. 124 - 130, March
1995.
[136] W.Chen, L.M.Ye, D.Y.Chen, F.C.Lee, “Phase error compensation method for the
characterization of low-power-factor inductors under high-frequency large-signal
excitation,” Conference Proceedings of 13th Annual Applied Power Electronics
Conference and Exposition, vol.1, pp. 420 – 424, Feb. 1998.
[137] D.J.Patterson, “An efficiency optimized controller for a brushless DC machine, and
loss measurement using a simple calorimetric technique,” PESC 1995, IEEE 26th Annual,
vol.pp. 22 - 27, 1995.
[138] Shri Sridhar, R.M. Wolf, W.G. Odendaal, “An accurate experimental apparatus for
measuring losses in magnetic components,” Conference Record of the 1999 IEEE Thirty-
fourth IAS Annual Meeting, vol.3, pp. 2129 - 2133, 1999.
[139] T.G.Imre, W.A.Cronje, J.D.van Wyk, “An experimental method for low power loss
determination,” Africon, 1999 IEEE, vol. 2, pp. 593 – 598, 1999.
References
173
[140] J.K. Bowman, R.F. Cascio, M. P. Sayani, “A calorimetric method for measurement
of total loss in a power transformer,” Record of 22nd Annual IEEE on Power Electronics
Specialists Conference, pp. 633 – 640, 1991.
[141] D.K.Conroy, G.F.Pierce, “Measurement techniques for the design of high-
frequency SMPS transformers,” Conference Proceeding of 3rd Annual Meeting on
Applied Power Electronics Conference and Exposition, pp. 341 – 351, 1988.
[142] J.P. Keradec, “Validating the power loss model of a transformer by measurement:
the price to pay,” Conference Record of the 37th IAS Annual Meeting on Industry
Applications Conference, vol. 2, pp. 1377 – 1382, 2002.
[143] B. Seguin, J. P. Gosse, A.Sylvestre, “Calorimetric apparatus for measurement of
power losses in capacitors,” IEEE Instrumentation and Measurement Technology
Conference, vol.1, 602 – 607, May ,1998.
[144] Brown A. J., Mellor P. H., Stone D. A., “Calorimetric measurements of losses in
IGBTs and MOSFETs in hard switched and resonant power converters,” PCIM’96
EUROPE, pp. 753-762, 1996.
[145] N.P. van der Duijn Schouten, C.Y. Leong, P.D. Malliband, R.A. McMahon,
“Implementation and calorimetric verification of models for IGBT-based inverters for
small drives,” Conference Record of the 38th IAS Annual Meeting on Industry
Applications Conference, vol. 3, pp. 1786 – 1793, 2003.
[146] M.Carpita, M. Mazzucchelli, L.Puglisi, “A differential system for evaluation of
losses in static power converters,” International Journal of Energy Systems, vol. 9, no.2,
pp. 115 – 119, 1989.
[147] P.D.Malliband, D.R.H.Carte, B.M.Gordon, “Design of a double-jacketed, closed
type calorimeter for direct measurement of motor losses,” IEE Conference Publication on
Power Electronics and Variable Speed Drives, no. 456, pp. 212 – 217, 1998.
[148] P.D.Malliband, N.P. van der Duijn Schouten, R.A. McMahon, “Precision
calorimetry for the accurate measurement of inverter losses,” 5th International
Conference on Power Electronics and Drive Systems, vol. 1, pp. 321 – 326, 2003.
[149] P.D.Malliband, R.A. McMahon, “Implementation and calorimetric verification of
models for wide speed range three-phase induction motors for use in washing machines,”
References
174
Conference Record of the 39th IAS Annual Meeting.on Industry Applications Conference,
vol. 4, pp. 2485 – 2492, Oct. 2004.
[150] D.R.Turner, K.J.Binns, B.N.Shamsadeen, “Accurate measurement of induction
motor losses using balance calorimeter,” IEE Proceedings-B, vol.138, no.5, Sept. 1991.
[151] A. Jalilian, V. J. Gosbell, B.S.P. Perera, “Double Chamber Calorimeter (DCC): a
new approach to measure induction motor harmonic losses,” IEEE Transactions on
Energy Conversion, vol. 14, no. 3, pp. 680 – 685, Sept. 1999.
[152] K.J.Bradley, A.Ferrah, R.Magill, J.C. Clare, P. Wheeler, P. Sewell, “Improvements
to precision measurements of stray load loss by calorimeter,” 9th IEE International
Conference on Electrical Machines and Devices, no. 468, pp. 189 – 193, 1999.
[153] P.Mcleod, K.J.Bradley, A.Ferrah, R.Magill, J.C. Clare, P. Wheeler, P. Sewell,
“High precision calorimetry for the measurement of the efficiency of induction motors,”
Conference Record of the 33th IAS Annual Meeting on Industry Applications Conference,
vol. 1, pp. 304 – 311,1998.
[154] B.Szabados, A.Mihalcea, “Design and implementation of a calorimetric
measurement facility for determining losses in electrical machines,” IEEE Trans. Instrum.
& Meas., vol. 51, no. 5, pp. 902 – 907, Oct, 2002.
[155] E. Ritchie, J.K. Pedersen, F. Blaabjerg, P. Hansen, “Calorimetric measuring
systems,” IEEE Magazine on Industry Applications, vol. 10, no. 3, pp. 70 – 78, May-Jun
2004.
[156] P. Hansen, F.Blaabjerg, K.D. Madsen, “An accurate method for power loss
measurement in energy optimized apparatus and systems,” EPE’99,Lausanne.
[157] A.J.Batista, J.C.S.Fagundes, P.Viarouge, “An automated system for core loss
measurement and characterization: a useful tool for high frequency magnetic components
design,” IEEE Proceedings of International Symposium on Industrial Electronics
(ISIE’98), vol.2, 1998.
[158] V.J.Thottuvelil, T.G.Wilson, H.A.Owen, “High-frequency measurement techniques
for magnetic cores,” IEEE Trans. Power Electronics, vol. 5, no. 1, January 1990.
[159] D.R. Zrudsky, J.M. Pichler, “Virtual instrument for instantaneous power
measurements,” IEEE Trans. Instrum. & Meas., vol.41, no.4, pp. 528 – 534, August 1992.
References
175
[160] E.F.Fuchs, R. Fei, “A new computer-aided method for the efficiency measurement
of low-loss transformers and inductors under nonsinusoidal operation,” IEEE
Transactions on Power Delivery, vol. 11, no.1, pp. 292 – 304, January 1996.
[161] G.Cauffet, J.P.Keradec, “Digital oscilloscope measurements in high-frequency
switching power electronics,” IEEE Trans. Instrum. Meas. vol. 41, no.6, pp. 856 – 860,
December 1992.
[162] I.A.El-kassas, E.J.K.Miti, L.N.Hulley, “Measurement of incidental power losses in
switching power devices,” Proceeding of the International Conference on Industrial
Electronics, Control, and Instrumentation (IECON’93), vol.2, pp. 757 – 761, 1993.
[163] N.Locci, F.Mocci, M.Tosi, “Measurement of instantaneous losses in switching
power devices,” IEEE Trans. Instrum. & Meas., vol.37, no.4, pp. 541 – 546, 1988.
[164] Y. Lembeye, J.P. Keradec, D Lafore, “Measurements of losses of fast power
switches, impact of typical causes of inaccuracy,” EPE’95.
[165] “ABCs of probes,” Tektronix, Inc.
[166] K. Ammous, B. Allard, O. Brevet, H.E. Omari, D. Bergogne, D. Ligot, R. Ehlinger,
H. Morel, A. Ammous, F. Sellami, “Error in estimation of power switching losses based
on electrical measurements,” IEEE 31st Annual Power Electronics Specialists Conference
(PESC 2000), vol. 1, pp. 286 – 291, 2000.
[167] “High-Speed probing,” Tektronix, Inc.
[168] A.Jalilian, V.J.Gosbell, B.S.P.Perera, “Double Chamber Calorimeter (DCC): a new
approach to measure induction motor harmonic losses,” IEEE Trans. Energy Conversion,
vol. 14, no.3, pp. 680 – 685, September 1999.
[169] A.V.den Bossche, “Flow calorimeter for power electronic converter,” EPE 2001-
Graz.
[170] Gang Chen, Chucheng Xiao, W.G. Odendaal, “An apparatus for loss measurement
of integrated power electronics modules: design and analysis,” 37th IAS Annual Meeting
Industry Applications Conference, vol. 1, pp. 222 – 226, Oct. 2002.
[171] J.A. Chavez, J.A. Ortega, J. Salazar, A. Turo, and M.J. Garcia, “SPICE model of
thermoelectric elements including thermal effects,” IEEE proceeding of the 17th
Instrumentation and Measurement Technology Conference, IMTC 2000, vol. 2, pp. 1019-
1023.
Appendix I
176
Appendix I Implementation of RF DC-DC power converter
The DC-DC converter with Class E inverter and Class E rectifier is supposed to
be implemented with discrete components and operate at MHzf 250= . In such high
frequency circuitry, it is critical to select proper components that can operate under this
frequency. Grounding and proper placement of switching components are also crucial to
achieve the desirable performance.
A. Component selection of the circuitry – LDMOSFET and passive components
A wide variety of active devices is currently available for use in RF applications.
Traditionally, RF power transistors have been built using Si bipolar technology, although
GaAs power transistors area also available. Recently, laterally diffused metal-oxide-
semiconductor (LDMOSFET) transistors have been proven to be very popular for these
applications [81].
LDMOSFET is a modified n-channel MOSFET specifically designed for both
high frequency and power amplifier applications. The significantly reduced parasitic
capacitances, especially the miller feedback capacitance, make it suitable for high
frequency applications. They have superior RF performance compared to bipolar
transistors and are highly cost-effective compared to their GaAs counterparts. Most
MESFETs are deletion-mode devices and require a negative gate bias. Therefore
LDMOSFET is a better candidate over GaAs MESFET for switching applications in the
proposed RF DC-DC power converter.
LDMOS is especially useful at UHF and lower microwave frequencies because
direct grounding of its source eliminates bond-wire inductance. LDMOS devices allow
the breakdown voltage to be above 80V while maintaining good frequency performance,
Appendix I
177
opening the door of high power and high frequency operation to bulk-Si technology. Also
LDMOS technology is compatible with CMOS process and passive components [82],
providing the potential for the integrated implementation.
Some key parameters of several LDMOS devices are listed in Table A. 1. L8711P
from Polyfet is chosen as the switching device in the prototype due to its low cost and
easy availability from vendors.
Table A. 1 Comparison of several LDMOSFETs.
Part Vendor f
(GHz)
V(BR)DSS
(V)
PD_max
(W) Rds_on (Ω)
Coss
(pF)
Ciss
(pF)
PD57018S ST 1 65 31.7 0.72 (Vgs=10V, Id=1.25A) 21 34.5
MRF284LSR1 Motorola 2 65 87.5 0.3 (Vgs=10V, Id=1A) 23 43
MRF6522-70R3 Freescale 1 65 159 0.15 (Vgs=10V, Id=1A) 47 130
L8711P Polyfet 1 36 60 0.4 (Vgs=20V, Id=8A) 40 50
Discrete passive components are employed in the prototype of RF DC-DC
converter. In comparison to the distributed elements, they have the advantage of smaller
size, lower cost, smaller interaction effects between discrete components and wider
bandwidth characteristics in this frequency range although discrete passive components
exhibit lower quality factor Q [83].
Components for applications in resonant, matching and filter sections are required
to meet the requirements of high Q, high self-resonant frequency and low parasitic values.
RFC choke in the circuit need higher current-handling capability and lower dc resistance
values.
As there are few magnetic materials that can be applied in such high frequency
range, air-core inductors are selected in the converter. RF air core inductors from
Coilcraft® are found to be very suitable for RF application. They feature tight inductance
tolerance and thermal stability, which can often eliminate the need for circuit tuning.
They have high SRF (Self-resonant frequency) in the order of GHz. The product of
inductance and SRF for smaller value inductors is as large as 24 nH – GHz, whereas for
Appendix I
178
large value inductors (100 nH) the product is as large as 120 nH – 1 GHz. The mini
spring air core inductors from Coilcraft have inductance from 2.5nH to 43 nH with SRF
ranging from 12.5 GHz to 1.2 GHz. For large inductance, for example, 120 nH midi
spring air core inductor has SRF at 1.1 GHz. These air core inductors are in form of
surface mount and provide extremely high Q over a wide frequency range. For example,
mini spring air core inductors from Coilcraft can achieve a minimum Q-value of 100. Fig.
A 1 shows the variation of Q as a function of frequency [84]. The inductors with the
current rating of 4 A are also available.
Fig. A 1 Typical variation of Q vs frequency for mini spring air core inductors from Coilcraft.
When selecting a capacitor, one should consider several parameters including
capacitance value, tolerances, the quality factor Q, ESR, SRF, voltage rating, current
rating, temperature coefficient, and cost [83]. A typical range for RF applications is from
0.1 pF to 1 μF. All discrete capacitors at radio frequencies have both resistance and
inductance. Series resistance in a capacitor is determined by knowing the Q of the
capacitor at the operating frequency. When a capacitor is represented by a series
combination of capacitance C and resistance sR , the quality factor Q is defined
asss fCRCR
Qπω 2
11== . The chip capacitors from ATC and AVX are available for RF
applications, featuring high Q, low ESR/ESL, high SRF, low noise and ultra stable
Appendix I
179
performance. Fig. A 2 shows typical measured Q values of ATC series 100B chip
capacitors. For a 22 pF capacitor, the Q is around 100 at 1GHz. Fig. A 3 shows typical
ESR values for ATC series 100B chip capacitors. For a 22 pF capacitor, ESR is about
0.06 Ohm at 500 MHz.
Fig. A 2 Typical variation of Q vs capacitance of ATC chip capacitors.
Fig. A 3 ESR vs capacitance of ATC chip capacitors.
B. Layout and parasitic extraction
Appendix I
180
The implementation of proper layout in switching converters is essential to the
successful operation of the converters. The importance of a good layout in the VHF
ranges cannot be overstated. The layout factors can affect the performance of the
switching converter. The considerations that affect the circuit board layout include:
radiated electromagnetic interference (radiated EMI), conducted EMI, stability,
efficiency and operational longevity. It is really a critical challenge to layout the RF
circuit board. However the knowledge about the layout fundamentals for switching
circuits makes the efforts much easier.
Switching power converter has large current pulses with very sharp edges flowing
within the circuit. These current pulses have the greatest effect on the creation of EMI,
particular attention should be paid to place the components of these loops. Fig. A 4 shows
these current loops for the proposed RF power converter.
Vdc
SW
RFCCrLr
Cs
RLCf
Lf
Csr
Dr
vDr
Control
vDs
Input loop Power switching loop
Resonant loop Rectifier loop Out loop
Fig. A 4 Major current loops in the switching RF DC-DC power converter.
Five loops are listed in the figure above. They are:
1. Power switching loop.
2. Resonant loop.
3. Rectifier loop.
4. Input source loop.
5. Output load loop.
The current flows in both input and output loops are composed of DC elements
with some AC ripple current. These AC components are the elements that generate
conducted EMI. The input and output loops do not result in problems most of the time
Appendix I
181
because the AC pulses are filtered by the input filter and output filter capacitors
respectively. This means that the high frequency noise problems created by these two
loops are less than the other three AC loops. The output voltage ripple is caused by the
charging and discharging of the output capacitors. Therefore it is helpful to minimize the
effect of ESR and ESL by making the traces between the filter capacitor and the load as
short and wide as possible. An adequate capacitor value, in parallel with power source, is
required at the input terminal. Besides, to prevent the spike voltage from feeding back to
the power line, some isolated installation is desirable, for example, a small inductor.
On the other hand, the power switching loop, resonant loop and rectifier loop are
entirely AC. They have high peak currents and very sharp edges (di/dt). Simultaneously,
there are high rates of dv/dt occurring within these loops. As a result these loops are very
noisy and deserve extraordinary attention. These loops should be laid out to have very
small circumferences and be implemented with short, wide traces. Smaller circumference
dictates less efficient antenna, reducing the radiated RF energy. The inductance and
resistance exhibited by a trace is inversely proportional to its width. Wider trace not only
causes lower voltage drop around the loop, thus less RF radiation, but also provides better
heatsinking for the power devices. So the loop traces should be as wide as possible.
For the layout considerations, care must be taken to make sure the components
that make up each of the three loops close to each other. In this way the dynamic high
currents remain in the converter’s power section. Therefore inC , RFC and SW (Fig. A 4)
should be close to each other. Also inC , rL , rC and rD should be close. By using short,
wide traces, the tight layout can be achieved to reduce radiation, improve efficiency,
reduce ringing and prevent interference to quieter parts of the circuit.
The stray capacitance at the nodes where voltage changes quickly should be
minimized. The size of such nodes should be kept small by using wide, short traces. At
the same time, EMI emanated from those nodes is reduced. The nodes DSV and DrV in Fig.
A 4 are identified as nodes where voltage quickly changes. The stray inductance in the
circuit branches with quickly changing current also should be minimized. The inductance
Appendix I
182
in series with SW and rD can indeed cause a problem because current through them
changes abruptly. These series inductance include stray inductance from leads as well as
inductance in the ground return path. Note the current through the resonant
tank rr CL − undergoes quick change due to very high switching frequency. Thus the stray
inductance of these branches must be minimized.
The ground serves as a common point of the reference for the circuit, which is a
very important function. Therefore, to place the ground carefully is crucial since
improper grounding layout will cause instability in the circuitry. Usually there are two
types of grounds existing within the switching power converter: high current loop power
ground and low level control ground. The control ground should be isolated from the
noisy power ground. Two separate ground paths can be routed. The power ground should
be made with short and wide traces to minimize the inductance and resistance.
Connecting the two grounds at one point ensures that no noisy current circulates within
the control ground. The connection between these two grounds can be relatively narrow,
as virtually no currents flows via that path.
A large ground plane can be placed on PCB back side and around high current
traces to reduce EMI. The ground plane acts as a shield to prevent some RF energy from
radiating to the environment [85]. These large conductor areas traps radiated EMI and
dissipate them within eddy current created by RF energy. Furthermore, the ground plane
on the back gains thermal characteristics to keep the PCB at a lower temperature
(comparing to no planes).
According to the characteristics of RF power converter, the key points on
designing PCB layout are summarized in the following:
1. Power ground is separated from control ground, but connected at a point.
2. Noisy loops (power switching loop, resonant loop, rectifier loop) should be
kept tight to reduce ringing and radiation.
3. Minimize stray capacitances at nodes DSV and DrV with high dv/dt.
Appendix I
183
4. Minimize stray inductance, especially branches SW , rD and resonant tank.
Based on these principles, the practical PCB layout of the RF DC-DC converter is
shown in Fig. A 5.
Fig. A 5 Practical layout of RF DC-DC power converter.
In order to evaluate the layout design and estimate the parasitic effects on the
circuit, it is necessary to determine the parasitics of the circuit layout. In the following
section the extraction of the layout parasitic is described.
Software Maxwell Q3D Extractor is chosen as the tool to calculate the parasitic
elements. Maxwell Q3D Extractor is interactive software package that can be used to
electrically characterize 3D interconnect structures such as those found in connectors,
Printed Circuit Boards (PCBs) [86]. This software can be used to solve for the circuit
parameters such as capacitance matrices, partial inductance and resistance matrices based
on the theory of partial element equivalent circuit (PECC) [87]. Lots of successful
applications of Q3D Extractor in parasitic extraction can be found in some literatures
[88][89][90][91].
Appendix I
184
The process for extracting the parasitic matrices is summarized below. In order to
setup the 3D geometrical model in Q3D Extractor, firstly the practical 2D PCB layout
generated is saved as an Autocad file. Then this 2D profile can be converted into 3D
structure based on the information of practical geometry in Autocad and saved as ACIS
file *.sat. The ACIS file is exported into the Q3D Extractor as a 3D model which has the
same dimensions as the practical ones. After specifying material properties for each
object, identifying the conductors, specifying source excitations and setting up the
solution settings, all the necessary parasitic parameters in the circuit can be generated.
Only the important circuit board parasitics are listed in Table A. 2 (refer to Fig. A 6). The
results show small parasitic capacitances and inductances of the layout which have
negligible effects on the performance of the circuit.
Table A. 2 Key parasitics in the circuit board.
DS Dr Gate
Parasitic cap (refer to GND) 0.069 pF 0.057 pF 0.047 pF
Parasitic inductance 0.17 nH 0.04 nH 0.014 nH
GND
Gate DS Dr
Fig. A 6 Model of 3D circuit layout in Q3D.
Appendix II
185
Appendix II Voltage measurement probe
TDS5104 digital oscilloscope manufactured by Tektronix® is chosen as a
measurement platform to measure the waveform in the RF DC-DC converter (refer to Fig.
3.30). The key features of the oscilloscope include up to 1 GHz bandwidth and 5 GS/s
real time sampling rate. The input impedance of the channel is 1 MΩ ± 1% in parallel
with 18 pF ± 2 pF or 50 Ω ± 2.5%.
The commercially available probe - the high impedance passive probe P5050 10×,
500 MHz is often used to measure the voltage waveform. It is necessary to look at the
frequency characteristics of this probe when it is used for high frequency measurement.
This typical 10× probe uses an RC network at the probe tip to form a 10:1 voltage divider
with the scope input impedance and the cable capacitance. The RC probe tip network is
approximately a 10 MΩ resistor in parallel with a 11.1 pF capacitor. The probe cable has
a characteristic impedance made as high as possible with a typical value being 170 Ω.
Since the probe is not terminated in its characteristic impedance at the scope, there will
be some reflections at higher frequencies and the resultant ringing and spurious response.
Another problem with this probe is that the input capacitance of 11.1 pF becomes fairly
low impedance at frequencies above 50 MHz. At 50 MHz, 11.1 pF has a capacitive
reactance of about 300 Ω. The frequency characteristics of the input impedance of probe
5050 is shown in Fig. A 7 [129], which clearly shows that the probe is not suitable for
voltage waveform measurement in the 250 MHz DC-DC power converter.
Appendix II
186
Fig. A 7 Frequency response of input impedance of probe 5050.
Since the input impedance of the scope TDS5104 can also be selected at 50 Ohm,
a coaxial cable having 50 Ohm characteristic impedance is chosen to construct a probe.
The cable is terminated at the scope end, so the input impedance looking into the input
end of the cable is 50 Ohm over a wide range of frequencies. A resistor inR is added in
series with the cable to form a voltage divider and set higher input impedance (as shown
in Fig. A 8).
Z0 = 50 OhmZL=50 OhmRin
VoutVin
Fig. A 8 Probe made by coaxial cable.
The input impedance is now 0ZRin + and the divider ratio is given by
0
0
ZRZ
VV
inin
out
+= . If a 10:1 probe is needed inR must be 450 Ohm and input impedance is
Appendix II
187
500 Ohm. It should be noted that the parasitic capacitance inC of inR should be minimized.
If assuming inC in parallel with inR , there exists a corner frequency ininCRπ2
1 below
which the probe behaves like a voltage divider composed of 0Z and inR . Above the corner
frequency, the divider ratio approaches unity. So a high quality resistor inR is necessary.
For typical resistor designs, this corner frequency ranges between 300 to 500 MHz for a
450 Ohm resistor. If there is a mismatch between the cable characteristic impedance and
the scope, a reflection is generated which travels back on the cable. The probe tip resistor
450 Ohm is also not a match for the cable. So in order to mitigate the resultant reflections
at the probe tip, a 50 Ohm resistor can be connected between the center conductor and the
shield of the coaxial cable as shown in Fig. A 9. The input impedance looking into the
cable is now 25 Ohm. So the probe has a divider ratio of 20:1 probe if inR =475 Ohm.
The input resistance of the probe is still 500 Ohm. In fact 500 Ohm input impedance of
this probe is resistive over a wide frequency range and greater than that of probe 5050
above 50 MHz [130].
Z0 = 50 OhmZL=50 OhmRin
VoutR1
Fig. A 9 Improve probe made by coaxial cable.
This kind of passive probe is well suitable for low impedance circuits. The input
impedance should be much higher than the impedances encountered in these circuits. If it
is not the case, the circuit would not likely function in the first place. In this case, high
performance commercial probes such as active probes (e.g. P6202) should be resorted to
at the expense of high cost.
Appendix III
188
Appendix III Design of the proposed calorimeter
Based on the thermal model analysis of the calorimeter in 5.4.2, it is essential to
minimize the heat leakage through the two covers. Aside from the heaters necessary for
controlling the temperature of the outer cover, other design considerations are also
required to achieve this goal. These considerations include:
• to provide a high degree of thermal insulation
• to minimize heat flow escaping from the system to the surrounding
• low thermal resistance path from the DUT to the TE module
• control circuits for TE module to direct heat flow and keep operating
temperature close to the practical case
• control circuits for heaters on the outer cover
• minimizing the thermal expansion stress between different materials
• various temperature measurements for control and monitoring
• flexibility and ease of operation.
The surface temperatures are measured with K type thermocouples. Monolithic
thermocouple amplifiers with cold junction compensators IC AD595 (Fig. A 10)
amplifies the output voltages of the thermocouples. These thermocouples should be
evenly and reliably mounted on the surfaces. One thermocouple is installed on every
outer surface of the inner cover and outer cover. On the top surface of the base plate I,
four evenly distributed thermocouples are mounted. Four thermocouples are also installed
on the surface of base plate II for the purpose of controlling TE module. The controllers
for heaters and TE modules are shown below in Fig. A 11 and Fig. A 12, respectively.
Appendix III
189
G
+A
-+
+ G-+
ICE Point Comp
TC connector
AD595
Overload detect
Vout: 10 mV/°C
Fig. A 10 Functional block diagram of AD595.
TEModules
Base Plate II AD595
AmplifierCMP
+15
-15+15
Driver
+15
-15
Vref
DUT
(a) Functional block diagram.
Appendix III
190
IN+1
C+ 2T+3
COM4
T-5 C- 6
7
FB 8
VO 9COMP10
11
ALM+ 12
ALM- 13IN-14
U1
AD594CQ (14)
red
yellow
+12 C20.1u
D1
1N4737(7.5V)
R4
20k
C36.8u
6
57
84
Amp
X1A
LM392N(8)
2
31Comp
84
X1B
LM392N(8)
R5
2.2k
R6 20k
GND
GND
GND
C10.068u
GND
D2
1N4740
R7
10k
R910M
R810k
R2
100
R3
2k
R1
200
R10
50
Q1IRFP140N
+15V
+12C4
0.1u
GND
GND
Vref
C5 33p
+12
TE red
TE black
K type thermocouple
TE module control circuit
D71N4002
GND
2k
R?1k
C?
0.068u
LO 1
NC 4
Vs5 Vb6
HO 7
NC 8
HIN10
SD11 LIN12
NC 14
U?
IR2112
+129
+123
GND
13 2
(b) Circuit schematic.
Fig. A 11 Controller for TE modules.
Heater
+15
Inner cover
Outer cover
AD595
AD595
DifferentialAmplifier
CMP
+15
-15+15
Driver
+15
-15
(a) Block diagram.
Appendix III
191
IN+1
C+ 2T+3
COM4
T-5 C- 6
7
FB 8
VO 9COMP10
11
ALM+ 12
ALM- 13IN-14
U1
AD594CQ (14)
red
yellow
+12
C2
0.1u
D1
1N4737(7.5V)
R4
20k
C36.8u+0.068u
GND
GND
Thermocouple
IN+1
C+ 2T+3
COM4
T-5 C- 6
7
FB 8
VO 9COMP10
11
ALM+ 12
ALM- 13IN-14
U1
AD594CQ (14)
red
yellow
+12
C2
0.1u
D1
1N4737(7.5V)
R4
20k
C36.8+0.068u
GND
GND
Thermocouple5
67
411
X2B
LF347N(14)
2
31
411
X2A
LF347N(14)
9
108
411
X2C
LF347N(14)
R10
50
Q1
MOSFET N
+V
Heater_1
Heater_2
R11
20k
R12
20k
R1310k
R14
1k
R15
1k
R169.1k
R21
9.1k
R203kR18
5k
R17
5k
R19
10M
+12
-12
D5ZENER3
D61N4740
D71N4002
GND
GND
+12
GND
R?
10k
R?
10k
R?750
R?150R?
10k
R?1k
R?1k
GND
R?1k
R?
1k
+12
-12
R?750
R?150
R?RES1
9
814
C
LM339
2kLO 1
NC 4
Vs5 Vb6
HO 7
NC 8
HIN10
SD11 LIN12
NC 14
U?
IR2112
+129
+123
GND
13 2
R?1k
C?
0.068u
(b) Circuit schematic.
Fig. A 12 Temperature difference controller for the two covers.
The proposed calorimeter is in the form of two concentric boxes. The internal box
is the test chamber and should be in good contact with the base plate I. Internal surfaces
of the inner cover and outer cover are highly polished to reduce the radiation heat leakage.
A fiberglass material with a thermal conductivity of 0.033 W/m⋅K fills the space between
the two covers, which can effectively prevents the heat from escaping. The external
surfaces of the outer cover are coated with an additional layer of fiberglass to ensure
more uniform temperature distribution across the whole outer cover. Fig. A 13 shows a
schematic diagram of the apparatus.
Fig. A 13 Mechanical schematic of the calorimeter.
Heaters Outer Cover
Inner CoverInsulation
Base Plate Base HF
TE
Appendix III
192
Two power resistor heaters are uniformly distributed on each of the external
surfaces of the outer covers. The mounting surfaces of the heaters were coated with
thermally conductive grease and then bolted to the cover. Four spring-loaded connectors
are arranged in a symmetrical pattern between the two covers so as to provide uniform
pressure when the two covers rest on the base plate and base cover (as shown in Fig. A
14). The maximum load of each spring in the design is 23.7 lb. Aside from the stainless
steel screws and the Zinc-plated springs, other parts of the connector are good thermal
insulators for minimizing the heat loss through the connector. With this design the inner
cover and outer cover are mechanically connected, and easily removable. The pressure
caused by the spring compression helps to increase the contact between inner cover and
base plate I.
1"
Inner Cover
Outer Cover
Fig. A 14 Spring connection between two covers.
In order to ensure a low thermal resistance path from DUT downward to TE
module, aluminum is used as the heat plates. All the aluminum plates were therefore
machined flat. Since the coefficients of thermal expansion (CTE) of the aluminum plates,
heat flux sensor and TE modules are different, the heat sink and the aluminum plate just
above the TE module were bolted together using the spring-loaded stainless steel screws
to effectively minimize the thermally induced mechanical stress induced by mismatched
CTE’s. This construction was repeated for the heat sink and base frame together (Fig. A
15).
Appendix III
193
Base Plate I
Base Plate II
Fig. A 15 Illustration of reducing thermal stress.
A soft layer of silicone gasket between the inner cover and base plate seals it air
tight. Any power leads and signal wires necessary for the operation of the DUT can be
connected via four airtight feed-through connectors on the base plate I. The supporting
legs of the calorimeter should have good mechanical strength and thermal insulation.
Adjustable draw latches are installed to clamp the upper part and the lower base part
together.
Appendix IV
194
Appendix IV Fabrication processing of the integrated inductor
In order to obtain the practical integrated inductor as described in design process
of 4.5, the fabrication processes below are required to follow.
1. Rounding the 12 sharp edges of the ferrite core by sander machine.
2. Cleaning: cleaning is always critical to the success of fabrication. Clean the
ferrite core by Actone at first, then alcohol; finally rinse the ferrite core with DI water,
and dry it.
3. Coating the ferrite core with the solder mask as insulation layer between the
ferrite core and windings. The solder mask is the combination of one part ENTHONE®
DSR-3241 B and four part ENTHONE® DSR-3241 A. After the coating of each side,
place the sample on the hot plate for 20 minutes at 80 °C.
4. Baking the ferrite core coated with the solder mask inside the heat oven to
harden the solder mask in preparation for the sputtering. The baking process is illustrated
in Fig. A 16. The sample after this process step is shown in Fig. A 17.
Fig. A 16 Baking process for hardening the solder mask.
t (minute)
90°C
125°
160°T (°C)
1°C/minute
1°C/minute
1°C/minute
2′
2′
30′
Appendix IV
195
Fig. A 17 Sample after solder mask.
5. Sputtering the sample.
It is better to clean the surfaces of the ferrite core after the step above before
sputtering. The two sides of the sample are required to be sputtered. Before the sputtering
of copper layers, Ti layer is firstly sputtered to each side of the sample. Ti sputtering
process lasts for about 15 minutes. After sputtering Ti on each side, then sputter Cu on
both sides of the sample. Cu sputtering process lasts for 15 minutes plus another 15
minutes, i.e., totally 30 minutes. The sputtering step is a long process for about 12 hours
because of 2~3 hours pumping time at the beginning of each sputtering. The sample after
Cu sputtering is shown in Fig. A 18. The empirical relationship between the sputtering
time and the thickness is listed in Table A. 3.
Table A. 3 Relationship between sputtering time and thickness.
30 minutes
Ti 50 – 60 nm
Cu 500 – 600 nm
Fig. A 18 Sample after Cu sputtering.
Appendix IV
196
6. Cu Electroplating of the sputtered sample.
The Cu electroplating process is to increase the thickness of the designed
metallization layer. The normal plating current density is 20 mA/cm2 and 25 μm
thickness is achieved under this current density after one hour. The current is set at 1.1 A
according to the total surface area of the sample. The plating lasts 2 hours to obtain 50
μm thickness of Cu layer.
Fig. A 19 shows the picture of the samples after electroplating.
Fig. A 19 Samples after electroplating.
7. Etching: The Kapton in width of 6.5 mm is wrapped around the ferrite core to
develop the winding pattern of the inductor, as shown in Fig. A 20. Then put the sample
in the developer as shown in Fig. A 21 to remove the unnecessary copper. This etching
process lasts about 10 minutes. After washing with water, put the sample into the Ti
etching solution (1 Ti etchant TFT: 20 DI water) for about 5 minutes to remove Ti layer.
Fig. A 20 Winding Pattern of the inductor.
Appendix IV
197
Fig. A 21 Developer machine for removing copper.
Now the sample is ready for making inductor.
Vita
198
Vita
The author, Chucheng Xiao, received his B.S. and M.S. degree from Huazhong
University of Science and Technology, Wuhan, China in 1995 and 1998, respectively.
From July 1998 to June 2001, he worked as an engineer in the Power Electronics Institute
of Dongfang Electronics Co., China. Since August 2001, he has been working towards
his Ph. D degree at Center for Power Electronics Systems (CPES), Virginia Polytechnic
Institute and State University. His research interests include high frequency high power
density DC-DC power converters, thermal management and measurement of power
electronic systems, integrated current sensing techniques and integration of passive
components.