an improved submodule unified pulse modulation scheme for … · abstract—this paper presents an...

322 CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, SEPTEMBER 2017

Abstract—This paper presents an improved submodule unified

pulse width modulation (SUPWM) scheme for a hybrid modular

multilevel converter (MMC) composed of half-bridge submodules

(HBSMs) and full-bridge submodules (FBSMs). The proposed

SUPWM scheme can achieve an output voltage of (2N+1) (where

N is the number of submodules in each arm) levels, which is the

same as that of the carrier-phase-shifted PWM (CPSPWM)

scheme. Meanwhile, the proposed SUPWM scheme can alleviate

the uneven loss distributions between the left leg and right leg in

FBSMs of the hybrid MMC. Moreover, the capacitor voltages of

the sub-modules can be well balanced without complicated

closed-loop voltage balancing controllers. The validity of the

proposed SUPWM scheme is verified by both the simulated and

experimental results.

Index Terms—Hybrid MMC, loss distribution, pulse width

modulation.

I. INTRODUCTION

HE modular multilevel converter (MMC) [1] is a

promising topology for medium- or high-power

high-voltage applications [2]-[4] due to its high power quality,

high efficiency, modularity and expandability. These

advantages make the MMC highly suitable for high-voltage

direct current transmission (HVDC) applications [5]-[6]. The

MMC is based on the half-bridge submodule (HBSM) in [1]

and has attracted extensive research interest due to its simple,

low component number and high efficiency. However, the

HBSM-based MMC cannot limit the fault current during the

DC-side short-circuit condition [7]-[8], so it cannot be

implemented in applications where DC-side short-circuit

protection is required. To realize DC-side short-circuit

protection, various modified sub-modules (SMs), such as a

full-bridge submodule (FBSM) [9], unipolar voltage FBSMs

[10], clamp-double SMs [6], five-level cross-connected

This work was supported in part by the National Natural Science Foundation

of China under Grant 51707088, 51607081 and the 5th–level talent introduction

program of Kunming University of Science and Technology.

Sizhao Lu, Xiaotin Deng and Siqi Li are with the Electrical Power Engineering Department, Kunming University of Science of Technology,

Kunming 650500, China. (e-mail: [email protected];

[email protected]; [email protected]. ) Kai Li and Zhengming Zhao are with the Electrical Engineering Department,

Tsinghua University, Beijing 10084, China. (e-mail: [email protected];

[email protected].) Correspondence: [email protected] Tel: +86-186-8717-6365

half-bridge SMs [11], three-level cross- connected SMs [12]

and diode-clamped SMs [12] are proposed. However, these

modified SMs need more power devices and suffer from high

conduction loss compared with the HBSM-based MMC’s [13].

To overcome these issues, the modified SMs can be mixed with

the HBSM to form hybrid MMCs [10]. Among these hybrid

MMCs, the hybrid MMC composed of the HBSMs and the

FBSMs is considered a very promising topology for the next

generation of highly meshed multi-terminal HVDC grids [14]

because it can not only control the DC fault current to be zero,

but also support the AC grid during the DC-side fault condition

[15]-[16].

Many published papers have focused on capacitor voltage

balancing and circulating current suppression for the

HBSM-based MMC [17]-[21], the FBSM-based MMC [22]

and the hybrid MMC [14], [16], [23]. In addition, many pulse

width modulation (PWM) schemes for the MMC have been

proposed [24] in order to improve the performance of the MMC.

Although space-vector modulation (SVM) is initially

considered as a possible modulation scheme for the MMC [25],

it has been proved that it is not preferred for the MMC with a

large number of SMs because the calculation and selection of

the vectors becomes more complicated as the SMs increase.

The phase-shifted carrier PWM (PSCPWM) is a popular PWM

scheme for the MMC [26]-[28] because of its high effective

switching frequency, even loss distribution among the SMs and

low total harmonic distortion (THD). However, it is not suitable

for the MMC with a large number of SMs because the dedicated

capacitor voltage balancing controllers that are mandatory for

the SMs. In [28], an improved PSCPWM for the hybrid MMC

is proposed. But it is still not suitable for the MMC with a large

number of SMs. The level-shifted PWM (LSPWM) scheme is

investigated in [29] and [30]. The dedicated capacitor voltage

balancing controllers are not needed in the LSPWM, as the

balancing control of the capacitor voltages is achieved by a

sorting and selecting algorithm. For the MMC with a large

number of SMs, the nearest level modulation (NLM) is

preferred [31]-[33]. The issue with the NLM, however, is the

round error introduced by the round function [32]. Therefore,

submodule unified pulse width modulation (SUPWM) is

proposed in order to compensate for the round errors of the

NLM by introducing one SM working in PWM mode [34].

An Improved Submodule Unified Pulse

Modulation Scheme for a Hybrid Modular

Multilevel Converter

Sizhao Lu, Member, IEEE, Kai Li, Member, IEEE, Xiaoting Deng, Siqi Li, Member, IEEE,

and Zhengming Zhao, Senior Member, IEEE

(Invited)

T

LU et al. : AN IMPROVED SUBMODULE UNIFIED PULSE MODULATION SCHEME FOR A HYBRID MODULAR MULTILEVEL 323

CONVERTER

SUPWM is suitable for the MMC with a large number of SMs,

no round errors, low total switching loss and no complicated

closed-loop voltage balancing controllers [34-38], so it is an

attractive modulation scheme for the MMC.

SUPWM has been proven as an effective PWM scheme for

the HBSM-based MMC. However, previous literatures about

SUPWM schemes only focus on the HBSM-based MMC. To

the knowledge of the authors, SUPWM schemes for the hybrid

MMC composed of HBSMs and FBSMs have not been studied

in the previous literatures. When the traditional SUPWM

schemes used in the HBSM-based MMC are directly applied to

the hybrid MMC, the FBSM is used just like an HBSM. The

modulation signals are only sent to the left leg of the FBSM; the

lower device of the right leg is constantly on and the upper

device of the right leg is constantly off. Therefore, the

switching actions will only concentrate on the left leg of the

FBSM. The right leg of the FBSM only has conduction loss,

which induces significantly uneven loss distribution between

the left leg and the right leg. Moreover, the devices of the

FBSM are not fully involved when the traditional SUPWM

scheme is directly applied to the hybrid MMC. In this paper, an

improved SUPWM scheme is proposed to deal with the issues

associated with the traditional SUPWM scheme implemented

in the hybrid MMC. The aim of this paper is to extend the

well-proven SUPWM scheme to the hybrid MMC.

The remainder of this paper is organized as follows. The

basic structure of the hybrid MMC and the traditional SUPWM

scheme, with a capacitor voltage balancing control for the

MMC, are presented in Section II. The improved SUPWM

scheme is presented in Section III. Simulated and experimental

results are presented in Section IV. The conclusions are drawn

in Section V.

II. TRADITIONAL SUPWM SCHEMES FOR HYBRID MMC

Fig. 1 shows one phase of the hybrid MMC. The DC-link

voltage is Vdc. Each arm is composed of N SMs, which consists

of H HBSMs and F FBSMs (N=H+F). The SMs are

series-connected and interfaced with the DC-link by the arm

inductor. A coupled arm inductor is employed in this paper

because of its smaller size and weight compared with the

discrete inductors [39]. M, Lu and Lw are the mutual inductance

and self-inductances of the coupled arm inductor. uL is the

voltage across the coupled inductor. uo and io represent the

output phase voltage and the output current. uuh and uuf denote

the voltages generated by the HBSMs and FBSMs in the upper

arm. uwh and uwf are the voltages generated by the HBSMs and

FBSMs in the lower arm. iu and iw represent the upper arm

current and the lower arm current, respectively. ic represents the

circulating current.

Assuming the coupled inductor is fully coupled (i.e., Lu =

Lw =M = Lo), the following equations can be derived [26]:

1 1 1

2 2 2o wh wf uh uf w uu u u u u u u (1)

4 c

L w u dc o

diu u u V L

dt (2)

1

2c u wi i i (3)

0

4

t

Lc c

o

ui I dt

L (4)

where uu and uw are the lower arm voltage and the upper arm

voltage, and Ic is the DC component of the circulating current.

The switch states of the HBSM and the FBSM are shown in

Tables I and II, respectively. The HBSM can only generate

voltage states Vc and 0. If S11 is on and S12 is off, the HBSM

output voltage vSMh will be equal to Vc, irrespective of the

direction of the arm current. This state of the HBSM is defined

as ON. If S12 is on and S11 is off, the HBSM output voltage vSMh

will be equal to 0, irrespective of the direction of the arm

current. This state of the HBSM is defined as OFF. The FBSM,

on the other hand, can not only generate voltage states 0 and Vc,

but also voltage state –Vc. However, only voltage states Vc and

0 are employed in its normal operation. Voltage state –Vc is

engaged only during the DC-side short-circuit condition. The

switch states of the FBSM can be defined as ON, OFF1, OFF2,

NEG and BLOCK, as shown in Table II, which are determined

by the states of S21, S22, S23 and S24. If switch S24 of the FBSM is

constantly on and only the switch states ON and OFF1 are used,

the FBSM can be controlled just like the HBSM. Therefore, the

SUPWM schemes used in the HBSM-based MMC, which this

paper calls the traditional SUPWM schemes, can be directly

applied to the hybrid MMC.

TABLE Ⅰ

SWITCH STATES OF HBSM.

States S11 S12 vSMh

ON 1 0 Vc

OFF 0 1 0

A

P

N

1

2dcV

1

2dcV

+

-

O

+

-

h( )SM H

f( )SM F

f(1)SM

h(1)SM

h( )SM H

f( )SM F

f(1)SM

h(1)SM

*

*

+

-

+

-+

-

+

-+

-

+

-

-

-

Fig. 1. Structure of the hybrid MMC.


TABLE Ⅱ

SWITCH STATES OF FBSM.

States S21 S22 S23 S24 vSMf

ON 1 0 0 1 Vc

OFF1 0 1 0 1 0

OFF2 1 0 1 0 0

NEG 0 1 1 0 -Vc

BLOCK 0 0 0 0 --

In general, the reference phase voltage of the MMC can be

expressed as

ref_cos

2dc

o o

Vu m t (5)

where m (0 ≤ m ≤ 1) is the modulation depth, ωo is the angular

frequency of the output ac voltage, and is the phase angle.

The reference voltage for the lower and upper arms can be

expressed as

ref_

1 cos( )2dc

w o

Vu m t (6)

ref_1 cos( )

2dc

u o

Vu m t

(7)

Take the upper arm as an example to illustrate the SUPWM

scheme. Assuming the capacitor voltages of all the SMs are

well balanced at Vc (Vc=Vdc/N), then KVc<uref_u < (K+1)Vc,

where K is a positive integer. K is given by

ref_ ref_

/u u

c dc

u uK floor floor

V V N (8)

where floor[x] stands for the floor function.

To generate a voltage of uref_u at a certain time, if only K SMs

are controlled to be ON, the arm voltage will be not enough; if

(K+1) SMs are controlled to be ON, the arm voltage will be in

surplus. Therefore, K SMs are controlled to be ON first, with

the (K+1)th

SM controlled to be pulse width modulated (PWM)

within one Tc and (N-K -1) SMs are controlled to be OFF. The

reference voltages for the (K+1)th

SM in the upper arm can be

expressed as

ref_K 1_ ref_

dcu u

Vu u K

N (9)

In SUPWM, the sorting and selecting algorithm [34] is used

to balance the capacitor voltages of the SMs, meaning that

complicated closed-loop voltage balancing controllers are not

needed. The sorting and selecting algorithm can be described as

follows. The voltages of the N SMs in the arm are first sorted in

an ascending order. Then the SMs will be selected to be ON,

OFF or PWM according to the capacitor voltages and the

direction of the arm current. When the arm current is positive, K

SMs with the lower capacitor voltage are controlled to be ON

(i.e., charging of the ON SM capacitors), (N-K -1) SMs with the

higher capacitor voltage are controlled to be OFF and the

(K+1)th

SM will be pulse width modulated. When the arm

current is negative, K SMs with the higher capacitor voltage are

controlled to be ON (i.e., discharging of the ON SM capacitors),

(N-K -1) SMs with the lower capacitor voltage are controlled to

be OFF and the (K+1)th

SM will be pulse width modulated.

The implementation diagram of the SUPWM scheme is

shown in Fig. 2 and the modulation of the PWM SM is shown

in Fig. 3. Take the upper arm as an example: the number of

ON-state SMs uK and the duty cycle ref_K 1_ uu

for the PWM

SM are generated by a round function. The capacitor voltages

( 1,2,..., )cujV j N and the arm current ui are sampled and the

sorting and selecting algorithm is applied to the sorting block in

order to balance the capacitor voltages. The duty cycles SMujd

for the SMs can be decided as

，

0，

ref_K 1_

1 , 1,...,

= , , 1

, 2,...,

SMuj u

ON state SMs j K

d u PWM SM j K

OFF state SMs j K N

(10)

In the PWM block, the duty cycles SMujd are compared with

the carriers to generate the pulses, and these pulses are sent to

the SMs.

In practice, the same carriers are employed for the N SMs in

each arm. However, the carrier displacement angle between the

lower and the upper arms can be either π or 0. When this

displacement angle is equal to π, the voltage step of the output

voltage is Vc, as shown in Fig. 3(a). Furthermore, the output

voltage has maximally (N+1) levels [34]. When this

displacement angle is equal to 0, the voltage step of the output

voltage is Vc/2, as shown in Fig. 3(b), with an output voltage

that has maximally (2N+1) levels [35]. In Fig. 3, Cu is the

carrier waveform for the SMs in the upper arm, while Cw is the

carrier waveform for the SMs in the lower arm.

In the traditional SUPWM schemes for the hybrid MMC,

switch S24 of the FBSM is constantly on and only the voltage

states ON and OFF1 of the FBSM are used. Therefore, the

switching loss will concentrate on S21 and S22; S24 has only

conduction loss and S23 is never engaged, which induces

A

P

N

1

2dcV

1

2dcV

+

-

O

+

-

h( )SM H

f( )SM F

f(1)SM

h(1)SM

h( )SM H

f( )SM F

f(1)SM

h(1)SM

Round

Round

Sorting

Sorting

ref_ou

2

dcV

uK

cujV

cwjV

1ref_K _ uu

wK

PWM

PWM

SMujd

SMwjd

ref_uu

ref_wu

1ref_K _ wu

Fig. 2. The implementation diagram of the SUPWM scheme.


CONVERTER

significantly uneven loss distribution between the left leg and

the right leg. Meanwhile, the devices of the FBSM are not fully

involved during normal operation.

III. IMPROVED SUPWM SCHEME FOR HYBRID MMC

This section proposes improvements to the traditional

SUPWM scheme for the hybrid MMC in order to overcome its

drawbacks. To fully utilize the FBSM, all the devices in the

FBSM should be engaged. Therefore, the switch state ON is

used to generate the voltage state Vc, while OFF1 and OFF2 are

alternatively used to generate the voltage state 0. In the hybrid

MMC, both the HBSM and the FBSM, which have different

characteristics, are used. Therefore, the characteristics of the

HBSM and the FBSM in the SUPWM scheme are first

investigated.

A. Characteristics of HBSM and FBSM in SUPWM

The voltage states of the HBSM and the FBSM are given in

Table I and Table II, respectively. In the hybrid MMC, the

(K+1)th

SM could be an HBSM or a FBSM. If the (K+1) th

SM is

an HBSM, the reference voltage of this HBSM is given by (9);

if the (K+1) th

SM is an FBSM, the reference voltages of the left

leg and the right leg of this (K+1) th

FBSM can be expressed as

ref_

ref_K 1_ _

ref_

ref_K 1_ _

2 2

2 2

dcu

dcu left

dcu

dcu right

Vu K

NVu

N

Vu K

NVu

N

(11)

When the same carrier is used for both the HBSM and the

FBSM, the voltage states of the PWM HBSM and the PWM

FBSM are as shown in Fig. 4. In Fig. 4, 1smhv and smfF

v

represent the voltage states of the PWM HBSM and the PWM

FBSM, respectively, and 1smh smf( )

Fv v denotes the voltage

state difference of these two SMs. It can be seen that the voltage

states of the PWM FBSM are different from those of the PWM

HBSM when the same carrier is used for the HBSM and the

FBSM. In addition, the total switching actions of the FBSM is

double that of the HBSM, which induces significantly uneven

loss distribution between the FBSM and the HBSM.

To deal with these issues, the carrier frequency of the FBSM

is first reduced to be half of the HBSM. Then a carrier

displacement angle θ is applied between the FBSM and the

HBSM, as shown in Fig. 5. In Fig. 5, the displacement angle θ

is equal to π. It can be seen that the output voltage states of the

PWM FBSM are exactly the same as those of the PWM HBSM.

B. An improved SUPWM Scheme for Hybrid MMC

To deal with the issues associated with the traditional

SUPWM scheme in the hybrid MMC, an improved SUPWM

scheme is proposed in this section. In each arm, the carrier

frequency of the FBSM is reduced to be half of the HBSM and

a carrier displacement angle θ, which is equal to π, is applied

between the FBSM and the HBSM. Moreover, the carrier

displacement angle between the lower and upper arms is equal

to 0. The PWM SM in the upper arm can be an HBSM or an

FBSM; the PWM SM in the lower arm can also be an HBSM or

an FBSM. Therefore, there are four combinations of the PWM

SMs in the hybrid MMC—that is, PWM HBSM and PWM

FBSM, PWM FBSM and PWM HBSM, PWM HBSM and

PWM HBSM, and PWM FBSM and PWM FBSM, which are

PWM

PWM SM

(a) (b)

PWM

PWM

Fig. 3. Modulation of the PWM SM in the lower arm and the PWM SM in the

upper arm with the SUPWM scheme. (a) (N+1) levels, (b) (2N+1) levels.

A

+

-O

N

P

+

-

Cell H

Cell 1

Cell F

Cell 1

Cell H

Cell 1

Cell F

Cell 1

1

2dcV

1

2dcV

(a) (b)

+

-cU

Left-leg Right-leg

+

-cU

PWM

PWM FBSM

Fig. 4. Output voltage states of the PWM HBSM and the PWM FBSM when

the same carrier is used.

A

+

-O

N

P

+

-

Cell H

Cell 1

Cell F

Cell 1

Cell H

Cell 1

Cell F

Cell 1

1

2dcV

1

2dcV

(a) (b)

PWM

PWM FBSM

+

-cU

Left-leg Right-leg

+

-cU

Fig. 5. Output voltage states of the PWM HBSM and the PWM FBSM with the

improved modulation scheme.


shown in Fig. 6 ~ Fig. 9.

Take the PWM HBSM in the upper arm and the PWM

FBSM in the lower arm as an example to illustrate the improved

SUPWM scheme, which is shown in Fig. 6. In Fig. 6, the

number of ON state SMs in the upper arm is K or (K+1), while

that of the lower arm is (N-K-1) or (N-K). Therefore, the total

number of ON state SMs in one phase is (N-1), N or (N+1). The

voltages of the upper and lower arms can be expressed as four

cases [35].

The first case is from t0 to t1 or from t4 to t5 in Fig. 6(a) and

Fig. (b)

=( 1)

=( )u c

w c

u K V

u N K V (12)

The output voltage of the first case can be expressed as

( 2 1) 1= =

2 2 2 2w u c

o c

u u N K V Nu K V (13)

The second case is from t1 to t2 or from t3 to t4 or from t5 to t6

in Fig. 6(a)

=( 1)

=( - 1)u c

w c

u K V

u N K V (14)

The output voltage of the second case can be expressed as

( -2 -2)= = 1

2 2 2w u c

o c


The third case is from t2 to t3 or from t6 to t7 in Fig. 6(a) and

Fig. 6(b)

=

=( - 1)u c

w c

u KV

u N K V (16)

The output voltage of the third case can be expressed as

( -2 1) 1= =

2 2 2 2w u c

o c


The fourth case is from t1 to t2 or from t3 to t4 or from t5 to t6

in Fig. 6(b)

(a) (b)

PWM

PWM

PWM

PWM

(a)

ref_K 1_ / 2u cu V (b)ref_K 1_ / 2u cu V

Fig. 6. Modulation of the PWM HBSM in the upper arm and the PWM

FBSM in the lower arm with the improved SUPWM scheme..

(a) (b)

PWM

PWM

PWM

PWM

(a)

ref_K 1_ / 2u cu V (b)ref_K 1_ / 2u cu V .

Fig. 7. Modulation of the PWM FBSM in the upper arm and the PWM HBSM in the lower arm with the improved SUPWM scheme.

(a) (b)

PWM

PWM

PWM

PWM

(a) ref_K 1_ / 2u cu V (b) ref_K 1_ / 2u cu V .

Fig. 8. Modulation of the PWM HBSM in the upper arm and the PWM

HBSM in the lower arm with the improved SUPWM scheme.

(a) (b)

PWM

PWM F

PWM

PWM F

(a) ref_K 1_ / 2u cu V (b) ref_K 1_ / 2u cu V .

Fig. 9. Modulation of the PWM FBSM in the upper arm and the PWM FBSM

in the lower arm with the improved SUPWM scheme.


CONVERTER

P

N

1

2dcV+

-

O

f(3)SM

h(1)SM

h(2)SM

h(3)SM

f(1)SM

f(2)SM

A

f(6)SM

h(4)SM

h(5)SM

h(6)SM

f(4)SM

f(5)SM

1

2dcV+

-

Fig. 10. Schematic of the single-phase inverter for simulation and

experiment.

=

=( - )u c

w c

u KV

u N K V (18)

The output voltage of the fourth case can be expressed as

( -2 )= =

2 2 2w u c

o c


It can be seen that the voltage step of the output voltage is

equal to Vc/2, which can make the maximum number of output

voltage levels be equal to (2N+1) levels. A similar analysis can

be applied to the other three cases. For these three cases, the

voltage steps of the output voltages are also equal to Vc/2 and

the maximum number of output voltage levels is equal to (2N+1)

levels as well.

According to the analysis results, it can be concluded that the

output voltages for these four combinations are the same. The

OFF1 and OFF2 of the FBSM are used alternatively, which can

alleviate the uneven loss distributions between the left leg and

right leg of the FBSM. Meanwhile, all of the devices in the

FBSM are engaged. In addition, the voltage step of the output

voltage is equal to Vc/2 and the maximum number of output

voltage levels is equal to (2N+1) levels.

In the improved SUPWM scheme, a sorting and selecting

algorithm [34] is used in order to balance the capacitor voltages

of the SMs, thus the complicated closed-loop voltage balancing

controllers are not needed.

IV. SIMULATED AND EXPERIMENTAL RESULTS

A. Simulated Results

To verify the validity of the improved SUPWM scheme, a

simulation model of the hybrid MMC is built in

MATLAB/SIMULINK. The structure of the simulation model

is shown in Fig. 10. Each arm is composed of six SMs,

consisting of three HBSMs and three FBSMs.

Table III shows the parameters of the simulation model. A

2.5kHz carrier frequency is employed for both the HBSMs and

the FBSMs under the traditional SUPWM schemes. The carrier

frequencies for the HBSMs and the FBSMs under the improved

SUPWM scheme are 2.5kHz and 1.25kHz, respectively. The

sorting and selecting algorithm is executed by every Tc (Tc=1/fc)

for both the traditional SUPWM schemes and the improved

SUPWM scheme.

TABLE III.

PARAMETERS OF SIMULATION.

Parameters Value Parameters Values

Rated active power P 500 kW SM Capacitance C 2 mF

DC-link voltage Vdc 10.8 kV Unit capacitance constant [40] Ucc 78 ms

Rated phase rms voltage Vao 3.46kV(rms) Carrier frequency fc 2.5k Hz

Number of SMs per arm N 6 Carrier frequency for HBSMs fch 2.5k Hz

Number of HBSMs per arm H 3 Carrier frequency for FBSMs fcf 1.25k Hz

Number of FBSMs per arm F 3 Fundamental frequency f0 50 Hz

Arm inductance Lu= Lw=M =Lo 1.2 mH

(1.6%) Load inductance LLoad

6 mH

(7.9%)

Rated SM Capacitor voltage Uc 1.8 kV Output AC current 145 A(rms)

Values in () are on a single-phase 3.46 kV, 500kW and 50Hz base.

The simulated results of the hybrid MMC with the traditional

SUPWM schemes are shown in Fig. 11 and Fig. 12. For the

traditional (N+1) level SUPWM scheme, the phase voltage uo is

a seven level staircase waveform, as shown in Fig. 11(a). For

the traditional (2N+1) level SUPWM scheme, the phase voltage

uo is a 13 level staircase waveform, as shown in Fig. 12(a). The

capacitor voltages are well balanced in both cases, as shown in

Fig. 11(b) and Fig. 12(b). The arm currents and the output

current for these two cases are shown in Fig. 11(c), Fig. 11(d),

Fig. 12(c), and Fig. 12(d). It can be seen from the figures that

the arm current waveforms in Fig. 11(c) are “cleaner” than

those in Fig. 12(c). However, the quality of the output current in

Fig. 12(d) is better than that in Fig. 11(d).

Fig. 13 shows the simulated results of the hybrid MMC with

the improved SUPWM scheme. The phase voltage uo is a 13

level staircase waveform, as shown in Fig. 13(a), which is equal

to (2N+1) levels. The capacitor voltages are well balanced, as

shown in Fig. 13(b). The output current is a sinusoidal

waveform with good quality, as shown in Fig. 13(d), and is the


same as that in Fig. 12(d).

The harmonics spectra of the hybrid MMC phase voltage

using the traditional (N+1) level SUPWM scheme, traditional

(2N+1) level SUPWM scheme and the improved SUPWM

scheme are shown in Fig. 14. Fig. 14(a) shows the phase

voltage harmonics spectra of the traditional (N+1) level

SUPWM scheme. Its center frequency of the lowest harmonic

group of the output voltage is 2.5kHz (fc=2.5kHz). Fig. 14(b)

and Fig. 14(c) display the phase voltage harmonics spectra of

the traditional (2N+1) level SUPWM scheme and the improved

SUPWM scheme, respectively. For these two cases, the center

frequencies of the lowest harmonic group of the output voltages

are 5kHz (2fc=2*2.5kHz). Meanwhile, the magnitudes of the

phase voltage harmonics spectra of these two cases are much

smaller than that of the traditional (N+1) level SUPWM scheme,

which can significantly reduce the output filter size.

A simple loss calculation method [34] is embedded into the

simulation model of the hybrid MMC in order to investigate the

loss distribution of the FBSMs. The main parameters of the

simulation model are given in Table III. The parameters of the

semiconductor module, FZ400R33KL2C_B5, are used in the

calculation. The loss distributions of the FBSM in the hybrid

MMC using traditional SUPWM schemes and the improved

0.45 0.46 0.47 0.48 0.49 0.51700

1800

1900

Volta

ge (

V)

0.45 0.46 0.47 0.48 0.49 0.5

-200

0

200

Curr

ent (A

)

0.45 0.46 0.47 0.48 0.49 0.5

-200

0

200

Time (s)

Curr

ent (A

)

0.45 0.46 0.47 0.48 0.49 0.5

-5000

0

5000

Volta

ge (

V)

0.45 0.46 0.47 0.48 0.49 0.5-100

0

100

200

Time (s)

Curr

ent (A

)

(a)

(b)

(c)

(d)

Volt

age

(V)

Cu

rren

t (A

)V

olt

age

(V)

Cu

rren

t (A

)

Fig. 11. Simulated waveforms of the hybrid MMC using the traditional (N+1) level SUPWM scheme. (a) phase voltage uo, (b) capacitor voltages, (c) arm

currents, and (d) output current io.

0.45 0.46 0.47 0.48 0.49 0.51700

1800

1900

Volta

ge (

V)

0.45 0.46 0.47 0.48 0.49 0.5

-200

0

200

Curr

ent (A

)

0.45 0.46 0.47 0.48 0.49 0.5

-200

0

200

Time (s)

Curr

ent (A

)

0.45 0.46 0.47 0.48 0.49 0.5

-5000

0

5000

Volta

ge (

V)

0.45 0.46 0.47 0.48 0.49 0.5-100

0

100

200

Time (s)

Curr

ent (A

)

(a)

(b)

(c)

(d)

Volt

age

(V)

Curr

ent

(A)

Volt

age

(V)

Curr

ent

(A)

Fig. 12. Simulated waveforms of the hybrid MMC using the traditional (2N+1)

level SUPWM scheme. (a) phase voltage uo, (b) capacitor voltages, (c) arm currents, and (d) output current io.

0.45 0.46 0.47 0.48 0.49 0.51700

1800

1900

Volta

ge (

V)

0.45 0.46 0.47 0.48 0.49 0.5

-200

0

200

Curr

ent (A

)

0.45 0.46 0.47 0.48 0.49 0.5

-200

0

200

Time (s)

Curr

ent (A

)

0.45 0.46 0.47 0.48 0.49 0.5

-5000

0

5000

Volta

ge (

V)

0.45 0.46 0.47 0.48 0.49 0.5-100

0

100

200

Time (s)

Curr

ent (A

)

(a)

(b)

(c)

(d)

Volt

age

(V)

Curr

ent

(A)

Volt

age

(V)

Curr

ent

(A)

Fig. 13. Simulated waveforms of the hybrid MMC using the improved

SUPWM scheme. (a) phase voltage uo, (b) capacitor voltages, (c) arm currents,

and (d) output current io.

Fig. 14. Harmonics spectra of hybrid MMC phase voltage using traditional SUPWM schemes and the improved SUPWM scheme. (a) traditional (N+1)

level SUPWM scheme, (b) traditional (2N+1) level SUPWM scheme, and (c)

improved SUPWM scheme.


CONVERTER

SUPWM scheme are shown in Fig. 15.

When the traditional SUPWM schemes are used, the

switching loss concentrates on only the left leg of the FBSM.

The right leg of the FBSM only has conduction loss because the

right leg of the FBSM has no switching actions, which induces

significantly uneven loss distribution between the left leg and

the right leg of the FBSM. Meanwhile, the devices of the

FBSM are not fully involved when the traditional SUPWM

schemes are applied to the hybrid MMC. When the improved

SUPWM scheme is applied, the uneven loss distribution

between the left leg and the right leg of the FBSM can be

alleviated because all the devices of the FBSM are involved.

Due to the switching loss and the conduction loss being

distributed across all the devices of the FBSM, the power rating

of the devices of the FBSM can be reduced. Therefore, lower

power rating devices can be used in FBSMs, which can

potentially reduce the expense of the semiconductors [34].

B. Experimental Results

A hybrid MMC prototype is built as shown in Fig. 16 in

order to verify the theoretical analysis and simulation results.

The parameters of the prototype are tabulated in Table IV. Each

arm of the hybrid MMC contains three HBSMs and three

FBSMs. A coupled inductor is employed as the arm inductor

and a resistor is used as the load in the experiment. A 2.5kHz

carrier frequency is used for both the HBSMs and the FBSMs

under the traditional SUPWM schemes. The carrier frequencies

for the HBSMs and FBSMs under the improved SUPWM

scheme are 2.5kHz and 1.25kHz, respectively.

The control algorithms for the MMC [41] are executed and

PWM signals for the SMs are generated in the digital signal

processor (DSP), TMS320F28335. PWM synchronization is

achieved by every Tc (Tc=1/fc) in the traditional SUPWM

schemes, while PWM synchronization is achieved by every Tcf

(Tcf=1/fcf) in the improved SUPWM scheme. The duty cycles of

the SMs are updated by every Tc (Tc=1/fc=1/fch) for both the

traditional SUPWM schemes and the improved SUPWM

scheme. An EP4CE15F17C8N FPGA is used to distribute the

PWM signals to the SMs and collect the capacitor voltages of

the SMs via optical fibers.

In Fig. 17, (a) and (b) show experimental waveforms of the

traditional (N+1) level SUPWM scheme for the hybrid MMC.

The phase voltage uo is a 7 level staircase waveform and the

capacitor voltages are well balanced, as shown in Fig. 17(a).

The output current is a sinusoidal waveform, as shown in Fig.

17(b). Fig. 17(c) and Fig. 17(d) show experimental waveforms

of the traditional (2N+1) level SUPWM scheme for the hybrid

MMC. The phase voltage uo is a 13 level staircase waveform

and the capacitor voltages are well balanced, as shown in Fig.

17(c). The output current is a sinusoidal waveform with good

quality, as shown in Fig. 17(d). From Fig. 17(b) and Fig. 17(d),

it can be seen that the quality of the output current in Fig. 17(d)

is better than that in Fig. 17(b).

TABLE Ⅳ

PARAMETERS OF THE HYBRID MMC PROTOTYPE.

Parameters Value Parameters Values

Rated active power P 622 W Unit capacitance constant [40] Ucc 79 ms

DC-link voltage Vdc 300 V Carrier frequency fc 2.5k Hz

Number of SMs per arm N 6 Carrier frequency for HBSMs fch 2.5k Hz

Number of HBSMs per arm H 3 Carrier frequency for FBSMs fcf 1.25k Hz

Number of FBSMs per arm F 3 Fundamental frequency f0 50 Hz

Rated SM capacitor voltage Uc 50 V Load resistance RLoad 12 ohm

Arm inductance Lu= Lw=M =Lo 0.625 mH (1.6%) Load inductance LLoad 3 mH (7.8%)

SM capacitance C 3280 uF Output AC current 7.2 A (RMS)

Values in () are on a single-phase 86V, 7.2A and 50Hz base.

The experimental results of the hybrid MMC with the

improved SUPWM scheme are shown in Fig. 18. The phase

voltage uo is a 13 level staircase waveform, as shown in Fig.

18(a). The capacitor voltages are well balanced, as shown in

0

50

100

150

200

250

300

350

400

450

HBSM_N1 FBSM_L_N4FBSM_R_N4 (e)

Conduction loss Switching loss

200W

359W

203W

382W

160W

Pow

er l

oss

(W

)

158W185W180W 180W

192W

Left leg Right legLeft leg Right leg Left leg Right leg

Traditional (N+1) level Traditional (2N+1) level Proposed

Fig. 15. Loss distributions for the hybrid MMC using traditional SUPWM schemes and the improved SUPWM scheme.

Fig. 16. Schematic and picture of the hybrid MMC prototype. (a) prototype

schematic, and (b) prototype picture.


Fig. 18(a). The output current is a sinusoidal waveform with

good quality, as shown in Fig. 18(b), and is the same as that in

Fig. 17(d).

The harmonics spectra of the hybrid MMC phase voltage

using the traditional (N+1) level SUPWM scheme, traditional

(2N+1) level SUPWM scheme and the improved SUPWM

scheme are shown in Fig. 19. Fig. 19(a) shows the phase

voltage harmonics spectra of the traditional (N+1) level

SUPWM scheme. Its center frequency of the lowest harmonic

group of the output voltage is 2.5kHz (fc=2.5kHz). Fig. 19(b)

and Fig. 19(c) show the phase voltage harmonics spectra of the

traditional (2N+1) level SUPWM scheme and the improved

SUPWM scheme, respectively. For these two cases, the center

frequencies of the lowest harmonic group of the output voltages

are 5kHz (2fc=2*2.5kHz). Meanwhile, the magnitudes of the

phase voltage harmonics spectra of these two cases are much

smaller than that of the traditional (N+1) level SUPWM scheme,

which can significantly reduce the output filter size. In Fig. 17

and Fig. 18, the experimental waveforms are not so “clean”

compared with the simulation results due to some non-ideal

factors (dead-time, sensor noises, sampling delay, etc.) in the

real experiments. However, the advantages of the (2N+1) level

SUPWM scheme and the improved SUPWM scheme when

compared with the (N+1) level SUPWM scheme are still clearly

illustrated.

The PWM gate signals of the FBSM using the traditional

SUPWM schemes are shown in Fig. 20(a) and Fig. 20(b). It can

be seen that the PWM gate signals are distributed only to the

left leg of the FBSM for both of the traditional SUPWM

schemes. Therefore, the switching loss will be concentrated on

the left leg, while the right leg will have only conduction loss,

which induces significantly uneven loss distribution between

the left leg and the right leg. The PWM gate signals of the

FBSM using the improved SUPWM scheme are shown in Fig.

20(c). It can be seen that the PWM gate signals are distributed

to both the left leg and the right leg of the FBSM. Therefore, the

switching loss will be distributed across both legs. All the

devices of the FBSM are engaged and the uneven loss

distribution between the left leg and the right leg can be

alleviated.

(a) (b)

15

1

(c) (d)

1

Fig. 17. Experimental waveforms of the hybrid MMC using traditional

SUPWM schemes. (a) phase voltage uo and capacitor voltages of the traditional

(N+1) level SUPWM scheme, (b) arm currents and output current io of the traditional (N+1) level SUPWM scheme, (c) phase voltage uo and capacitor

voltages of the traditional (2N+1) level SUPWM scheme, and (d) arm currents

and output current io of the traditional (2N+1) level SUPWM scheme.

(a) (b)

1

Fig. 18. Experimental waveforms of the hybrid MMC using the improved

SUPWM scheme. (a) phase voltage uo, (b) capacitor voltages, (c) arm currents,

and (d) output current io.

Fig. 19. Harmonics spectra of the hybrid MMC phase voltage using the

traditional SUPWM schemes and the improved SUPWM scheme. (a) traditional

(N+1) level SUPWM scheme, (b) traditional (2N+1) level SUPWM scheme,

and (c) improved SUPWM scheme.


CONVERTER

(c)(b)(b)(a)

Fig. 20. PWM gate signals of the FBSM using the SUPWM schemes. (a) traditional (N+1) level SUPWM scheme, (b) traditional (2N+1) level SUPWM scheme, and (c) improved SUPWM scheme.

V. CONCLUSIONS

In this paper, an improved SUPWM scheme is proposed for a

hybrid MMC consisting of HBSMs and FBSMs. When the

traditional SUPWM schemes are directly used in the hybrid

MMC, the switching signals are only distributed to the left leg

of the FBSM, which induces significantly uneven loss

distributions between the left leg and the right leg of the FBSM.

Meanwhile, the devices of the FBSM are not fully engaged.

Therefore, an improved SUPWM scheme is proposed to deal

with these issues. In the improved SUPWM scheme, the

switching frequency of the FBSM is reduced to be half of the

HBSM and a proper phase-shifting angle is applied between the

HBSMs and the FBSMs. Then the switching signals are

distributed to both the left leg and the right leg of the FBSM.

The improved SUPWM scheme can achieve an output voltage

with (2N+1) levels and alleviate the uneven loss distributions

between the left leg and right leg in the FBSM of the hybrid

MMC. Therefore, lower power rating devices can be used in

FBSMs of the hybrid MMC, which can potentially reduce the

expense of the semiconductors. Moreover, the capacitor

voltages of the submodules are well balanced without

complicated closed-loop voltage balancing controllers. The

validity of the proposed SUPWM scheme is verified by both

the simulation results and the experimental results.

ACKNOWLEDGMENTS

The research is supported by National Science Foundation

(51707088 and 51607081) of China in part, the 5th

–level talent

introduction program of Kunming University of Science and

Technology in part.

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Sizhao Lu (M’16) received the B.S. and

M.S. degree in electrical engineering from

Harbin Institute of Technology, Harbin,

China, in 2008 and 2010, respectively. He

received the Ph. D. degree in electrical

engineering from Tsinghua University,

Beijing, China, in 2016. He became an

Assistant Professor in 2016 with the

Department of Electrical Engineering, Kunming University of

Science and Technology, Kunming, China. He was a Visiting

Scholar at the Center for Power Electronics Systems, Virginia

Tech, Blacksburg, VA, USA, from February 2012 to November

2013.

His research interests include Modular Multilevel Converters

(MMC), solid state transformers and high-frequency high

power three-level DC-DC converters.

Kai Li (S’13) was born in Henan, China,

in 1988. He received the B.S. degree in

electrical engineering from Wuhan

University, Hubei, China, in 2011 and the

Ph. D degree from Tsinghua University,

Beijing, China, in 2017, where he is

currently a Postdoctoral Fellow. He was a

Visiting Scholar at the Center for Power

Electronics Systems, Virginia Tech, Blacksburg, VA, USA,

from September 2013 to February 2015.

His research interests include modular multilevel converters

and solid state transformers.

Xiaoting Deng received the B.S. degree in

electrical engineering from Kunming

University of Science and Technology,

Kunming, China, in 2017. She is currently

working toward the M.S. degree with the

Department of Electrical Engineering,

Kunming University of Science and

Technology, Kunming, China.

Her research interests include modular multilevel converters

and Vienna rectifiers.

Siqi Li (M’11) received the B.S. and Ph.D.

degree in electrical engineering from

Tsinghua University, Beijing, China, in

2004 and 2010, respectively. He was a

Postdoctoral Fellow with the University of

Michigan, Dearborn, USA from 2011 to

2013. In 2013, he joined the Faculty of

Electric Power Engineering, Kunming

University of Science and Technology (KUST), Kunming,

China, where he is currently an associate professor with the

Department of Electrical Engineering. Also, he is the director

of the Advanced Power Electronics and New Energy


CONVERTER

Laboratory in KUST. His research interest focuses on battery

management system, high performance wired, wireless battery

chargers for electric vehicles and solid state transformers.

Zhengming Zhao (M’02–SM’03)

received the B.S. and M.S. degrees in

electrical engineering from Hunan

University, Changsha, China, in 1982 and

1985, respectively, and the Ph.D. degree

from Tsinghua University, Beijing, China,

in 1991.

In 1991, he joined the Department of

Electrical Engineering, Tsinghua

University. From 1994 to 1996, he was a Postdoctoral Fellow

with The Ohio State University, Columbus, OH, USA, and then

was a Visiting Scholar with the University of California, Irvine,

CA, USA, for one year. He is currently a Professor with the

Department of Electrical Engineering and the Deputy Director

of the State Key Laboratory of Power System, Tsinghua

University. His research interests include high-power

conversion, power electronics and motor control, and solar

energy applications.

Prof. Zhao is a Fellow of the Institution of Engineering and

Technology, U.K. He is also the Vice President of Beijing

Power Electronics Society and the Chairman of the IEEE

Power Electronics Society Beijing Chapter.

an improved submodule unified pulse modulation scheme for … · abstract—this paper presents an...

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