An improved common-mode feedback loopfor the differential-difference amplifier

Francesco Centurelli • Andrea Simonetti •

Alessandro Trifiletti

Received: 17 March 2012 / Revised: 5 July 2012 / Accepted: 31 August 2012 / Published online: 25 September 2012

� Springer Science+Business Media, LLC 2012

Abstract Unconditional stability of the high-gain ampli-

fiers is a mandatory requirement for a reliable steady-state

condition of time-discrete systems, especially for all blocks

designed to sample-and-hold (S/H) circuits. Compared to

differential path, the common-mode feedback loop is often

affected by poles and zeros shifting that degrades the large

signal response of the amplifiers. This drawback is made

worse in some well-known topologies as the difference-

differential amplifier (DDA) that shows non-constant

transconductance and poor linearity. This work proposes a

body-driven positive-feedback frequency compensation

technique (BD-PFFC) to improve the linearity for precision

DDA-based S/H applications. Theoretical calculations and

circuit simulations carried out in a 0.13 lm process are also

given to demonstrate its validity.

Keywords Positive-feedback compensation � Differential

difference amplifier � Common-mode feedback loop �Sample-and-hold circuits

1 Introduction

A glance to steady-state equations made for several sam-

ple-and-hold circuits, leads to non-linear systems with time

varying norm-bounded uncertainties [1–3]. Hence, many

optimized topologies have been proposed to enhance the

maximum intrinsic gain of analog blocks [4–7] constrained

by the generalized scaling theory [8] as well as to preserve

usefulness and flexibility of the well-known linearization

techniques.

Currently, introduction of active-feedback sample-and-

hold amplifiers (AF-SHA), allows designers to reduce

several limitations related to deep-submicron processes

[9–11]. As explained in [9], this family of SHA achieve a

near-zero steady-state error simply using very low gain

amplifiers in the network loop. To further emphasize ver-

satility of the aforementioned technique, some limitations

imposed by unwanted drawbacks must be removed. Pri-

marily, theory of operation shows a statistical dependence

of the accuracy figure-of-merit (FOM).

Additionally, since the fully-differential AF-SHA

requires a difference-differential amplifier (DDA)-based

auxiliary amplifier, a high-gain common-mode (CM)

feedback loop (CMFB) is a mandatory requirement

[12, 13]. For a comparative analysis, it should be noted that

the special processes as the FinFET [14], or the floating

gate technology [15] as also the bulk-driven technique

[7, 16], require a very accurate design for a reliable oper-

ation [17–20]. Therefore, some considerations related to

standard CMOS design and the clock phases minimization,

makes AF-SHA among the most efficient architectures also

compared to FOM of the SHA-less analog-to-digital con-

verters (ADCs) [21, 22]. Expanding upon the method

reported in [23, 24], this paper introduces a novel CMFB

compensation technique, especially suited for DDA-based

AF-SHA, but also applicable to a variety of time-discrete

applications. Before proceeding any further, it is worth

noting that by improving the CMFB gain, also the com-

mon-mode rejection ratio (CMRR) is enhanced [25, 26].

Several CMFB configurations have been presented in the

literature [27–32], using both continuous-time (CT) and

switched-capacitor (SC) topologies. A detailed description

of major features of these techniques can be found in [27, 28].

F. Centurelli � A. Simonetti (&) � A. Trifiletti

Department of Information Engineering, Electronics and

Telecommunications (DIET), University of Rome

‘‘La Sapienza’’, Via Eudossiana 18, 00184 Rome, Italy

e-mail: simonetti@die.uniroma1.it

123

Analog Integr Circ Sig Process (2013) 74:33–48

DOI 10.1007/s10470-012-9961-1

The most common topology for a wide input swing is based

on a CT balanced resistive-capacitive divider CM-sense

network [29], followed by a differential pair error amplifier.

This topology offers the best performance in terms of loop

gain, bandwidth and linearity, but the sensing resistors

should be very large to guarantee the gain of the system is not

deteriorated. However, large resistors lead to huge noise and

parasitic effects as also a gate leakage at input of the error

amplifier (usually with a capacitive type impedance), espe-

cially in nanoscale technologies [30].

Stability of the CM-path is also affected by some

additional drawbacks. As practical example, the CMFB

loop of a fully-differential (FD) two-stage Miller–com-

pensated operational transconductance amplifier (OTA), is

affected by several parasitic poles. Since the dominant pole

is set by the Miller compensation that is designed to satisfy

specifications on the differential signal, these poles degrade

the phase margin of the CMFB, thus making very difficult

to have an unity-gain frequency comparable with that of

the differential amplifier [30]. Moreover, the external

feedback loop results in a positive reaction for what con-

cerns the common-mode signal, so that to avoid instability

a careful design is required [31].

In this work, we propose a SC CMFB circuit based on

the body-driven and positive-feedback frequency com-

pensation technique (BD-PFFC) to increase the CMRR and

keep low the input leakage. This paper is organized as

follows. In Sect. 2, we analyze the CMFB compensation by

using positive feedback technique, with particular empha-

sis on the frequency behavior of the CMFB and on the

constraints imposed by the main signal path on the CMFB

itself. In Sect. 3 the basic principles for the proposed sys-

tem are summarized and the circuit design is explained.

Section 4 presents the simulations results to assess the

validity of the proposed technique. Conclusions are sum-

marized in Sect. 5.

2 CMFB compensation

In this section we briefly recall the analysis of a simple

Miller-compensated (MC) DDA, with particular emphasis

on the CMFB loop and on the interaction between the

CMFB and the main differential signal path. Particularly,

the CMFB should ideally provide high loop gain, with a

unity-gain bandwidth comparable to that of the differential

path, to guarantee good CMRR for all the frequencies of

interest, and an adequate phase margin (e.g., 60�). How-

ever, as shown in the following analysis, these require-

ments cannot be all satisfied at the same time. So, the

positive feedback technique is a possible solution to

improve both the phase margin and the loop-gain of the

common-mode path. Figure 1 shows the schematic of the

MC-DDA; a purely capacitive load CL is assumed. A

resistive divider CMFB is used (Fig. 2(a)), composed by

the CM-sense network Rcm1, Rcm2, (Rcm1 = Rcm2 = Rcm)

with capacitors Ccm used to optimize the frequency

response, and a diode-loaded error amplifier.

2.1 Differential path

Figure 3 shows the small-signal differential half-circuit for

the main amplifier, where:

C0D ¼ Cgs1 þ Cgd1 1þ gm1R1Dð Þ; ð1Þ

R1D ¼ ro1kro2 � ro1= 1þ að Þ; ð2ÞC1D ¼ Cgd1 þ Cgd2 þ Cgs3 � Cgs3; ð3Þ

R2D ¼ ro3 ro4k Rcmk � ro3=2; ð4ÞC2D ¼ Cgd3 þ Cgd4 þ CL þ Ccm � CL þ Ccm: ð5Þ

For the sake of generality, we have supposed a ratio abetween the transconductances of transistors M1 and M2

(lpW2/lnW1 = a); the load effect due to the CM-sense

network is included in R2D and C2D, and we suppose that

Rcm � ro3 so that the penalty on the gain is negligible. For

the pole-zero analysis, transistor M1 summarizes the joint

effect of M10 (the differential pairs are assumed to be

balanced, so M1 = M10 = M1

00 = M1000). The analysis of

this circuit is well known and provides a dc gain:

AVoD ¼ gm1gm3R1DR2D ffi gm1gm3ro1ro3=2 1þ að Þ; ð6Þ

with three poles:

p1D ¼ �1=gm3R1DR2DCM; ð7Þp2D ¼ �gm3=C2D; ð8Þp3D ¼ �1=C1DRM; ð9Þ

and a zero due to the Miller effect on the gate-drain

capacitance of the first stage:

z1D ¼ gm1

�Cgd1; ð10Þ

as also a second zero due to the Miller compensation:

z2D ¼ gm3=CM 1� gm3RMð Þ; ð11Þ

The latter is cancelled by choosing the Miller resistance

as:

RM ¼ 1=gm3: ð12Þ

In this case the third pole is at very high frequency, since

C2D � C1D. So, the unity-gain frequency is:

xuD ¼ AVoDp1 ¼ gm1=CM; ð13Þ

and if a 60� phase margin is desired the following relation

must hold for the second pole:

34 Analog Integr Circ Sig Process (2013) 74:33–48

123

p2Dj j � 2xuD: ð14Þ

2.2 Common-mode path

Figure 4 shows the small-signal circuit for the CMFB loop,

where:

CG ¼ 2 Cgs2 þ Cgd2 1þ gm2ro2ð Þ� �

¼ 2C0C; ð15Þ

is the load capacitance of the error amplifier and:

R1C � ro2 ¼ 1þ að ÞR1D=a; ð16ÞC1C ¼ Cgd1 þ Cgd2 þ Cgs3 ¼ C1D; ð17Þ

R2C ¼ ro3 ro4 1�

G0L � ro3=2 ¼ R2D;���� ð18Þ

C2C ¼ Cgd3 þ Cgd4 þ CL þ C0L � CL þ C0L; ð19Þ

The common-mode half-circuit has been considered for

the main amplifier (Fig. 4(b)), whereas the full error

amplifier should in general be considered due to the dif-

ferent loading of its outputs (Fig. 4(a), neglect CK). In this

case, the analysis provides the load effect of the CMFB on

the main amplifier as:

Y 0L ¼ G0L þ sC0L ¼sCgs5

4

1þ sRcmCcm

1þ sRcm 4Ccm þ Cgs5

� ��4; ð20Þ

and the overall loop gain:

Fig. 1 Miller-compensated DDA

Fig. 2 Resistive divider CMFB. a basic buffered circuit; b CMFB with positive feedback compensation

Fig. 3 Differential-mode half-circuit

Analog Integr Circ Sig Process (2013) 74:33–48 35

123

Acmfb ¼ ADivAEAV : ð21Þ

Referring to (21) we have the following terms:

ADiv ¼vi

voc¼ 1þ sRcmCcm

1þ sRcmCcm 1þ Cgs5

�2Ccm

� � ¼ 1þ sscm

1þ ssB;

ð22Þ

as the voltage divider of the CM-sense network, with:

scm ¼ RcmCcm; ð23Þ

sB ¼ Rcm Ccm þ Cgs5

�4

� �; ð24Þ

and:

AE ¼vix

vi¼ gm5=2gm7

1þ s Cgs7 þ CG

� ��gm7

ð25Þ

as the gain of the error amplifier; finally

AV ¼voc

vix¼ AVoC 1þ s=z1Cð Þ 1þ s=z2Cð Þ

1þ s=p1Cð Þ 1þ s=p2Cð Þ 1þ s=p3Cð Þ ; ð26Þ

is the gain along the main amplifier, with:

AVoC ¼ gm2gm3R1CR2C � AVoD 1þ að Þ; ð27Þ

z1C ¼ gm2

�Cgd2 ¼ z1D; ð28Þ

z2C ¼ gm3=CM 1� gm3RMð Þ ¼ 1: ð29Þ

If (12) is verified we obtain:

p1C ¼ �1=gm3R1CR2CCM ¼ ap1D= 1þ að Þ; ð30Þp2C ¼ �gm3=C2C; ð31Þp3C ¼ �1=C1CRM ¼ p3D: ð32Þ

We can note that the Miller compensation sets the

dominant pole also for the CMFB loop; however,

additional poles are present with respect to the

differential path, due to the error amplifier and to the

CM-sense network.

Table 1 summarizes the values of open-loop poles and

zeros for the differential gain and the CMFB loop gain.

2.3 Positive feedback compensation technique

The first constraint on the design of the CMFB loop stems

from the interaction between differential path and CMFB.

The previous equations show that the Miller compensation

is usually designed according to the specifications on the

differential path, and p2C & p2D. As shown in Fig. 5, the

additional poles in the CMFB require a lower unity-gain

frequency to guarantee 60� phase margin. If we recall that

for the CMFB loop we have for the dc gain and the unity-

gain bandwidth, respectively:

Acmfb0 ¼ 1þ að ÞAVoDgm5=2gm7; ð33Þ

xuC ¼ Acmfb0p1C ¼ axuDgm5=2gm7; ð34Þ

we see that this implies an upper limit on the loop gain of

the CMFB, to be obtained by reducing the gain of the error

amplifier (the ratio gm5/gm7): this is the reason for the diode

load on the error amplifier in Fig. 2(a). Capacitors Ccm in

the CM-sense network help to increase the phase margin,

however, the needed reduction in gain and bandwidth still

remains very large, since low value capacitors have to be

used to minimize the loading of the amplifier. All this

results in large dc offsets and limited rejection to CM

signals. The situation is still worse if cascode stages or an

output common drain stage are used, providing additional

poles that erode the phase margin as also in the DDA-based

architectures, where an optimal CMRR FOM can be

achieved by using an active error amplifier instead the

simple diode-loaded. As shown in Fig. 6, both circuits

Fig. 4 Open loop CMFB small-

signal circuit. a error amplifier;

b main amplifier

36 Analog Integr Circ Sig Process (2013) 74:33–48

123

share most of the transistors, but with some differences and

some additional blocks in the CMFB: the CMFB path

exchanges the roles of transistors M1 and M2 in the first

stage (and this results in A1C & (1 ? a)A1D), has a dif-

ferent loading of the second stage, and presents an addi-

tional diode-loaded differential pair and a filter on the

output. So, an optimal design of both loops requires an

additional compensation of the CMFB loop, as proposed

for example in [31] through a multipath scheme. However,

a simple solution can be achieved with the positive feed-

back technique. Figure 2(b) shows a compensation scheme

for the resistive-divider CMFB that adds a negative zero to

the CMFB transfer function, to increase the phase for fre-

quencies around the unity-gain frequency, thus providing a

higher phase margin. This allows to design separately the

main differential path and the CMFB loop: the Miller

compensation is designed to satisfy specifications on the

differential signal, and the additional zero in the CMFB is

used to maximize gain and bandwidth of the CMFB loop

while still maintaining a good phase margin.

The zero is added without interfering with the main

signal path, by exploiting a positive capacitive feedback

around the error amplifier. In this way, there are no con-

straints on the value of this compensation capacitor CK,

apart from integration issues. As a first approximation, the

proposed scheme adds a R–C series in parallel to the Zi at

the input of the error amplifier (see Fig. 4(a)), where R is

the resistance of the diode-connected transistor M8, thus

adding a negative zero to ADiv. A detailed analysis of the

proposed solution can be performed with reference to the

small-signal circuit in Fig. 4. It can be shown that the gain

of the error amplifier (25) remains unaltered, whereas the

voltage divider of the CM-sense network becomes:

ADiv ¼vi

voc¼

2 1þ sRcmCcmð Þ gm7 þ s CK þ Cgs7

� �� �

K 1þ ss1ð Þ 1þ ss2ð Þ ;

ð35Þ

where CK is the positive feedback capacitance and

s1 � Rcm Ccm þCgs5

4

� þ CK

gm7

þ CKRcm

21� gm5

2gm7

� ;

ð36Þ

s2 �

Rcm CKCgs7þ CK þCgs7

� �2Ccmþ Cgs5

2

�h i

2 CK þCgs7

� �þRcmCK gm7� gm5

2

� �þRcmgm7 2Ccmþ Cgs5

2

� :

ð37Þ

Moreover, also the loading effect of the CMFB on the

main amplifier, given by (20), is modified into

Y 0L ¼ sCeq

1þ sRcmCcmð Þ Cgs5 CKþCgs7ð Þþ2CK Cgs7

Cgs5gm7þCK 2gm7�gm5ð Þ

1þ ss1ð Þ 1þ ss2ð Þ ð38Þ

where:

Ceq ¼ sCgs5

4þ CK

21� gm5

2gm7

� � ; ð39Þ

however, its effect on p2C is limited, so we can neglect it in

the analysis. Basically the capacitance CK modifies the

voltage divider of the CM-sense network, by substituting

(22) with

ADiv ¼1þ sscmð Þ 1þ ssXð Þ1þ ss1ð Þ 1þ ss2ð Þ ; ð40Þ

where:

sX ffi CK=gm7; ð41Þ

s1 ffi sB þ sX þCKRcm

21� gm5

2gm7

� ; ð42Þ

s2 ffiRcmCKCgs7

�gm7 þ sBsX

sB þ sX þ RcmCK

21� gm5

2gm7

� : ð43Þ

The zero z3C = 1/scm and the pole p4C = 1/s1 are at low

frequency, and have no effect on the phase margin: the

improvement of the phase margin of the CMFB loop is

given by the positions of the zero z4C = 1/sx and of the

pole p6C = 1/s2, that is usually at a higher frequency.

Figure 7 sketches the positions of poles and zeros under the

effect of CK; it has to be noted that the use of feedback to

obtain the zero allows a more robust compensation than by

using a R–C series branch, since the zero given by (41)

tracks process and temperature variations.

Moreover, Fig. 7 shows also that the pole p6C somehow

limits the effect of CK, so that a careful design of the error

amplifier is needed to maximally exploit this technique.

Additionally, (40) shows that the CM-sense impedance is

affected by the positive feedback loop, so this compensa-

tion technique cannot be applied in the switched capacitor

CMFB circuits without some improvements.

Table 1 Open loop poles and zeros

Parameter Diff. gain CMFB loop

dc gain gm1gm3ro1ro3=2 1þ að Þ gm5gm2gm3R1CR2C=2gm7

p1 �1=gm3R1DR2DCM �1=gm3R1CR2CCM

p2 �gm3=C2D �gm3=C2C

p3 �1=C1DRM �1=C1CRM

p4 – �1�

RcmCcm 1þ Cgs5

�4Ccm

� �

p5 – �gm7

�Cgs7 þ 2C0C

� �

z1 gm1

�Cgd1 gm2

�Cgd2

z2 gm3=CM 1� gm3RMð Þ gm3=CM 1� gm3RMð Þz3 – �1=RcmCcm

Analog Integr Circ Sig Process (2013) 74:33–48 37

123

3 Proposed CMFB circuit

3.1 System description

Figure 8 depicts the proposed CMFB architecture. The

circuit is composed by a CM-sense followed by an error

amplifier with active load output. The high-impedance

circuitry for the dc-bias of the body path is not shown at

this point (will be discussed in the next paragraph). Notice

that the inputs to M1 and M2 must be exchanged when the

main amplifier has an even number of stages. Assuming fs,

Cs for the sampling clock and the sense capacitors,

respectively, we have C, p�C, Rcc for the positive-feedback

network, and w�C as output load of the error amplifier (i.e.,

the gate-to-source capacitance of the active load pair of the

main amplifier). The p and w are scalar constants to

establish a relationship among homogeneous parts. Since

the switches have a low-pass behavior with cutoff

frequency:

x�3db ¼1

RonCs; ð44Þ

the SC CM-sense can be modeled as a resistive-capacitive

divider, so the following analysis is similar (under some

conditions) for the above-described time-continuous

counterpart. From (44), we pose Rcm = Ron & 1/(2pfsCs)

Fig. 5 Bode plots for the main

differential path (solid) and the

CMFB loop (dashed)

Fig. 6 Block scheme

comparison between the

differential path and the CMFB

loop

38 Analog Integr Circ Sig Process (2013) 74:33–48

123

and Ccm = Cs, with Cp as the parasitic capacitance that

needs to be driven the CMFB (i.e., the input capacitance of

the error amplifier). The small-signal analysis of the

common-mode path, see Fig. 9, provides an overall loop

gain:

Acmfb ¼ AcmAeAacm: ð45Þ

The transfer function Acm of the CM-sense network will

be given similarly as in (22–24):

Acm ¼tcm

tdm¼ 1þ sRcmCcm

1þ sRcmCcm 1þ Cp

2Ccm

� ¼ 1þ sscm

1þ ssa; ð46Þ

with:

scm ¼ RcmCcm; ð47Þ

sa ¼ Rcm Ccm þCp

2

� : ð48Þ

The error amplifier can be analyzed as follows. Con-

sidering gm and ro, respectively, the small signal trans-

conductance and output resistance of a mos transistor, we

have gmbody, gm, gma, for the body and forward trans-

conductance of the input-pair, and the active load,

respectively. Therefore, by introducing the scalar constants

c and v we pose:

gma ¼ c � gm; ð49Þgmbody ¼ v � gm: ð50Þ

Neglecting some parasitic contributions, that results in

a much wider gain-bandwidth product (GBW), from (49)

the open-loop gain Aeu of the error amplifier without com-

pensating network can be expressed as:

Fig. 7 Position of poles and

zeros with positive feedback

compensation

Fig. 8 Proposed SC-CMFB

architecture with BD-PFFC

technique

Analog Integr Circ Sig Process (2013) 74:33–48 39

123

Aeu ¼te

tacm� gm � ro

3

1þ Cgs

2gm

�s

1þ Cgs

2gmþro�w�C

4

�s

2

4

3

5 ¼ Aeo1þ ssb

1þ ssc;

ð51Þ

where Cgs is the gate-to-source capacitance of the input

transistor and:

Aeo ¼gm � ro

3; ð52Þ

sb ¼Cgs

2gm; ð53Þ

sc ¼Cgs

2gmþ ro � w � C

4: ð54Þ

Equation (51) shows a dominant pole response, so the

positive feedback loop can be taked into account with a

similar analysis as described in [4, 5]. Since the

compensating network is closed to bulk input instead to

gate ones (i.e., the input of amplifier), only a fraction of the

overall gain is controlled by the positive reaction.

Accordingly, we expect a closed-loop response as:

Ae ¼Aeu

1� bBe; ð55Þ

where Be is the gain contribution related to bulk input and

b = C/p�C = 1/p is the feedback factor. From (50), Be is

proportional to Aeu, so the allowable range for the scalar p

can be obtained by manipulating (55) as:

Ae ¼Aeu

1� bvAeu; ð56Þ

with the stability condition:

b\1

v � Aeu; ð57Þ

Equation (57) together (51) and (56), demonstrate that

by applying too much positive feedback, results in a right

half-plane pole making the system unstable. Since Aeu is

design-related and v & 0.1–0.3, the lower bound of p for a

reliable operation is completely determined. For a practical

expression of (56), notice that the improvement of the

phase margin of the CMFB loop is given by the positions

of the zero and pole that are usually at a higher frequency.

Consequently, a simplified small-signal analysis leads to

closed-loop compensated gain Ae as:

Ae ¼ A0eo1þ ss#1þ ssd

; ð58Þ

where:

A0eo ¼2gm � ro cþ 1ð Þ

2 3cþ vþ 32c � vþ 3

� �� 2v � gm � ro

; ð59Þ

s# ¼Cgs 1þ c� v� c � vð Þ þ 2gm � c � C � Rcc

2gm cþ 1ð Þ ; ð60Þ

sd ¼�v �Cgsþ 2c �wþ 2wþ 2cþ c � vþw � vþw � c � vð Þ

2ro

3cþ vþ 32c � vþ 3

� �� 2v � gm

�

ð61Þ

Equation (58) together with (59), (60), and (61),

demonstrate that the positive feedback adds a negative

zero to the CMFB function, to increase the phase margin

without affecting the bias point or the DC gain. As shown

in Fig. 8, the latter is increased by using an active load

scheme (i.e., a current mirror) instead of the well-known

diode-loaded configuration, and the gain is further

increased in the frequency domain by the positive

reaction. Summarizing, three features are achieved with

the proposed method. First, the bulk-driven compensation

instead to conventional gate-driven feedback, avoids the

input leakage when compared with the Miller-based

scheme (impracticable for SC types CM-sense). Since the

coupling is AC-type, the parasitic junction connected to

bulk-terminal is never forward or reverse biased (the body

is weak forward biased). Next, a simple error amplifier

based on the active-load, increases the CMRR without

complex configurations that cannot be used in a CMFB

loop avoiding the poles and zeros shift. Finally, the

positive-feedback compensation technique increases the

gain of the overall cmfb path maintaining an adequate

phase margin.

Fig. 9 Schematic block of the BD-PFFC technique

40 Analog Integr Circ Sig Process (2013) 74:33–48

123

3.2 Body bias circuitry

Figure 10 shows a wide-swing cascode current mirror [32,

33] with a floating current source and load [34]. This cir-

cuit is often used in class AB op-amps [35–37]. Transistors

M1–M4 and M5–M8 act as a balanced cascode current

mirror where the drain-to-source voltages of transistors M1

and M2 as well as M7 and M8 are biased, with auxiliary

sources V(p) and V(n), to be close to the minimum value

needed to operate in saturation region. By applying this

scheme as a body bias circuitry, nodes N1 and N2 act as a

high impedance source (notice that the positive feedback

loop is carried out with an AC coupling technique) with a

minimum voltage drop across itself, tying the p-substrate or

the n-well to the optimal safety level to keep the parasitic

junction from forward biasing or equivalently, to prevent

the latch-up action.

As a matter of fact, lowering node N2 to ground or

increasing the node N1 to supply voltage, it makes a simple

and reliable solution for a weak forward biasing of the N-

type or P-type bodies, respectively.

Detailing the principle of operation, the proper voltage

level for the body bias is obtained via the floating current

mirror (transistors M9 and M11) and the output load

(transistors M10 and M12). Assuming M9 and M11 with

the same transconductance, the floating current source (or

also a ‘floating current mirror’ considering its bias tran-

sistors M13–M16) acts like a level shifting voltage source

with series resistance. Since the voltage level for the left

side nodes are fixed by M9 and M11, by sizing transistors

M9, M11 and M10, M12 for the same transconductance

(and similarly the groups M1–M4 and M5–M8), both left

and right side of the wide-swing current mirror have cor-

responding nodes (N1 and N3 as well as N2 and N4) at the

same potential. Notice that both the floating current source

as the load track temperature and supply variations via their

bias transistors M13–M16 and M17–M20, so the output

impedance (right side) is quite constant. Consequently, the

high impedance nodes (i.e., N1, N2) can be used to bias the

body-input of the error amplifier related to the positive

feedback loop whereas the low impedance counterparts

(i.e., N3, N4) can bias the other one.

As expected, tying the bodies of the differential pair to

the same potential (approximately one hundred millivolt

below the source terminal, see node N5 of Fig. 10), this

results in a reduced op-amp offset. A special attention

should be paid to design the layout; this is necessary to

reduce parasitic effect to the high-impedance nodes. Par-

ticularly, parallel capacitors between the metal layers and

the substrate, leads to unwanted voltage sources, because a

current flows through these capacitive dividers. This effect

can be reduced without compromising the regenerative

loop, by design the body bias circuitry for a moderate

impedance (i.e., few megohms). However, also the regen-

erative network must be designed to overcome the effects

of the aforementioned parasitic capacitances (usually esti-

mated in a few tens of fentofarad or below) as well as to

take into account the impedance of the bias circuitry. As a

general rule, by setting the feedback capacitors on the order

of picofarads, this results in a robust design.

Fig. 10 Body bias circuitry

Analog Integr Circ Sig Process (2013) 74:33–48 41

123

3.3 Noise considerations

The main noise contributions to the proposed architecture

are substantially derived from the forward-biasing tech-

nique as also both from the body-bias circuitry (this is often

design-related, so can be adjusted for a minimum impact)

as by the positive-feedback loop itself. As a general prin-

ciple, by increasing the forward body voltage, also the

body effect is enhanced. This results in a lowering

threshold but also an exponential (with die temperature)

increase of the leakage current through the forward-biased

junctions. Consequently, apart the latch-up action that can

be evaluated distinguishing between analog and digital

circuits [38] as also respect to technology implementation,

the shot noise FOM is generally penalized. The shot noise

is proportional to current in a forward-biased p–n junc-

tions; thus a strongly forward-biased p–n junction exhibits

the full shot noise, because the carriers across itself

increase exponentially. This effect can be reduced by using

a weak forward voltage, as described in the previous par-

agraph. Contrarily to shot noise, thermal noise (that is

inversely proportional to the mosfet transconductance) is

advantaged from the forward-biasing technique. Effec-

tively, by increasing the forward voltage of substrate,

threshold decreases, leading to a greater transconductance

thus in a thermal noise reduction.

Let us return now to (56). The latter, can be extended to

a noisy amplifier as shown in Fig. 11 with few modifica-

tions. Assume a noiseless amplifier with a gain A (i.e., the

error amplifier) and a noiseless feedback network with a

gain B (i.e., the body input of the error amplifier). The

section of the forward amplifier that shares the same path

of the common mode loop can be modeled with a noiseless

block K. The feedback factor is the scalar b. Noise sources

g1, g2, g3, can be used to model the input referred noise of

the blocks with gains K and A as also the feedback network

(C, pC, Rcc, see Fig. 8), respectively. Source g4 models the

noisy behavior of the body input. Since (50), and assuming

a positive feedback loop starting from low frequencies

(quasi-static hypothesis), closed-loop response is:

to ¼KA

1� bvAð Þ þ KA

� tcm þ K 1=A� bv �

g1 þ g2 þ bvð Þg3 þ vg4

h i;

ð62Þ

with the constraint:

0\ 1� bvAð Þ 1: ð63ÞEquation (62) shows that the noise sources g2, g3 and g4

as well as the input signal tcm, all are dominated by the

negative loop showing an unitary signal-to-noise ratio. This

is an expected result, since the feedback decreases the output

signal by the same amount as the noise contributions. Con-

versely, the source g1 decreases in proportion to the gain (A).

Since (62), can be concluded that the sources g3 and g4

introduced with the proposed circuit increase the overall

noise of the system, but the regenerative loop doesn’t further

emphasizes these contributions. Additionally, resistor Rcc of

the feedback network has a moderate value (a few hundred of

ohms), so the effect of the source g3 is negligible.

3.4 Optimizing the feedback factor

The proposed circuit exhibits a specific solutions for DDA-

based op-amps that generally show a poor CMRR FOM.

First-of-all, the new body-driven feedback allows a simple

compensation of the cmfb loop without interposition with

the same gate dedicated to a SC CM-sense. However, the

CMRR is improved by closing the cmfb amplifier to a

current mirror, enhancing the overall common mode gain.

Of course, by cascading gain stages this results in a phase

margin degradation. This is a well-known problem that

cannot be completely solved just with a positive feedback

technique. Assuming a design using short-channel tech-

nologies (below 130 nm), where the multistage topologies

are widely used to approach analog blocks, the opamp

Fig. 11 Noisy sources of the

common mode loop

42 Analog Integr Circ Sig Process (2013) 74:33–48

123

architecture plays an important role into relocation of the

poles and zeros of the cmfb loop. So that, the maximum

common mode gain or equivalently the maximum allow-

able phase for the cmfb loop are strictly related to the gain

and topology of the main amplifier. Taking into account

these considerations, an optimal design can be obtained

lowering the regenerative effect as a minimum as possible

to reaches the best phase margin.

Figure 12 shows an example of a startup design with

C = 1pF, p = 3 (i.e., b = 0.33) and Rcc = 700 X with a

gain improvement of the error amplifier of 11 dB over its

DC value (about 23 dB). The main amplifier is a two-stage

DDA type, with Miller compensation (Cmiller = 2pF,

Rmiller = 1 kX). This amplifier shows a gain of 48 dB with

a bandwidth of 750 MHz while loaded by a 2-pF capacitor.

Since the overall common-mode path reaches 72 dB DC-

gain (see Fig. 13), a further increase of only 6 dB beyond

the starting value of 11 dB, can be considered a good

tradeoff with a 50� worst-case for the phase margin. As

described in a previous section, the pole expressed in (58)

limits the effect of the positive feedback, so that the values

of C, p and Rcc can be optimized for a specific design.

4 Simulations results

The proposed compensation technique has been applied to

a Miller-compensated two-stage DDA designed in IBM

0.13 lm CMOS technology and simulated with Cadence

Spectre. Transistor parameters for all blocks can be found

in Table 2. The supply voltage of the system is 1.2 V. The

main amplifier shows a gain of 50 dB with a bandwidth of

600 MHz loaded by a 4 pF capacitor. The R-C series

branch with CM = 4 pF and RM = 400 X performs the

Miller compensator. The cmfb loop is equipped with a SC

CM-sense followed by an error amplifier that shows a basic

gain of 20 dB. The CM network is made out with a group

of 0.8 pF capacitors and a transmission-gate switches

exploiting their complementary nature to minimize the

charge injection effect. The sampling frequency for the

CM-sense is fS = 25 MHz. Figure 14 shows gain and

phase of the common mode path before compensation. The

improvement in the phase margin (about 60�) result of the

positive feedback action is shown in Fig. 15. Figure 16

shows the AC analysis results of the combined effect

among Rcc, C, and p C in the positive feedback network

with values C = 1pF, p = 3 and a sweep between 100 Xand 2 kX for the Rcc value. As expected, best values of the

phase-margin were obtained by increasing Rcc (as in the

Miller-based compensation). Figure 17 shows a case study

with Rcc = 700 X and a sweep between 0.8 and 6.0 for the

p value. A lower value results in a higher gain. Figure 18

shows the response of the main amplifier both for the small

and large input signals. The large signal analysis is

accomplished by closing the DDA as a buffer with trans-

conductors in a high-swing common mode configuration

[13]. The overall linearity can be evaluated with the first

derivative of the amplifier response. The same system is

evaluated using the BD-PFFC technique and without this

(low gain cmfb). Figure 19 highlights that the DDA buffer

with BD-PFFC compensation exhibits an enhanced line-

arity because the proposed cmfb circuit increases the

CMRR FOM. Figure 20 and Table 3 also confirm this

feature demonstrating a good third-order distortion espe-

cially when taking into account that the buffer is made out

with a low-gain amplifier. Figure 21 shows the noise

voltage spectral density for the DDA buffer in both cmfb

configuration. As discussed in paragraph 3.3, when using

BD-PFFC an increment of the noise figure was expected.

Figures 22, and 23 show that the suggested body bias cir-

cuitry effectively track over the power supply and tem-

perature variations. To evaluate BD-PFFC response in S/H

circuits, must be considered that the DDA opamps are

frequently used in the buffered samplers with switch-and-

hold capacitor [39], or in a dedicated configurations [9, 10].

Fig. 12 Example of the Bode plot of the error amplifier with positive

feedback compensation technique. Gain (solid) and phase (dashed)

Fig. 13 Example of the Bode plot of the overall common-mode path

with positive feedback compensation technique. Gain (solid) and

phase (dashed)

Analog Integr Circ Sig Process (2013) 74:33–48 43

123

For the sake of generality, the DDA buffer is stressed with

a sine wave source with a rectangular modulation (the

common mode voltage is always present). This results in a

good approximation of the opamp behavior in a more

complex S/H circuits without accomplish a particular

topology. Figure 24 shows the accuracy of the overall

amplifier using the proposed positive feedback frequency

compensation. The differential input signal is 1.4 V-pp

Table 2 OTA transistor parameters

Parameters Main amplifier

(half circuit)

(lm/lm)

CMFB amplifier

(lm/lm)

Body bias

circuitry

(lm/lm)

M0 40/0.2 – –

M1, M2 180/0.2, 20/0.2 40/0.2, 40/0.2 3/0.2, 3/0.2

M3, M4 30/0.2, 80/0.2 5/0.2, 5/0.2 6/0.2, 6/0.2

M5, M6 – 15/0.2, 10/0.2 2/0.2, 2/0.2

M7, M8 – – 1/0.2, 1/0.2

M9, M10 –, 10/0.2 – 1.5/0.2, 1.5/0.2

M11, M12 20/0.2, – – 0.5/0.2, 0.5/0.2

M13, M14 – – 3/0.2, 3/0.2

M15, M16 – – 1/0.2, 1/0.2

M17, M18 – – 30/0.2, 30/0.2

M19, M20 – – 8/0.2, 8/0.2

Transm. gate (P) – 15/0.2 –

Transm. gate (N) – 5/0.2 –

Table 3 S/H Monte Carlo behaviour (N = 1000)

Parameters BD-PFFC Amp �X rXð Þ (dB)

Gain error 3.18 ± 0.020

HD2 113.37 ± 9.25

HD3 61.36 ± 5.70

HD4 122.71 ± 9.55

HD5 70.20 ± 7.45

HD7 77.47 ± 5.65

HD9 78.35 ± 5.50

HD11 83.06 ± 2.00

HD13 78.04 ± 3.85

Fig. 14 Bode plot of the overall common-mode path without

compensation. Gain (solid) and phase (dashed)

Fig. 15 Bode plot of the overall common-mode path with positive

feedback compensation technique. Gain (solid) and phase (dashed)

Fig. 16 Family of the Bode plots related to phase-margin

enhancement

Fig. 17 Family of the Bode plots related to gain enhancement

44 Analog Integr Circ Sig Process (2013) 74:33–48

123

with a frequency of 750 kHz. Notice that the steady-state

error is related only to low differential-gain of the main

amplifier. Figure 25 shows the buffer response with the

standard SC-CMFB followed by a diode-loaded error

amplifier [40] without the BD-PFFC (see Fig. 2(a)). The

poor CMRR FOM, results in a distorted response with

Fig. 18 Small (solid) and large (dashed) signal response of the

overall amplifier with BD-PFFC technique

Fig. 19 Linearity (first derivative) of the overall amplifier response

with BD-PFFC technique. Small signal (a), large signal (b), and

amplifier with a conventional cmfb loop (c)

Fig. 20 Frequency spectrum of the DDA buffer with BD-PFFC

technique

Fig. 21 Equivalent noise voltage spectral density (VHz-�). Standard

amplifier (solid) and proposed BD-PFFC technique (dashed)

Fig. 22 Body bias voltage. Power supply voltage sweep (solid) and

temperature sweep (dashed)

Analog Integr Circ Sig Process (2013) 74:33–48 45

123

anomalous amplitude. Figure 26 shows the common mode

response of the aforementioned DDA-based buffer using

the BD-PFFC technique compared with the simple buffered

SC-CMFB. The former allows a high-CMRR that is dem-

onstrated by a common mode response unaffected by the

input signal.

5 Conclusions

The positive feedback compensation technique results still

more useful when applied to high-gain Miller-compensated

opamps where cascoding techniques and output source

followers are used, that introduce additional poles that limit

the phase margin. This is the case of opamps to be used in

pipeline ADCs, where high gain and large bandwidth are

required to minimize static and dynamic gain errors. In this

paper we have extended this method to SC-CMFB circuits

in DDA-based amplifiers that allows to increase loop gain

and unity gain bandwidth of the CMFB, thus obtaining a

better common-mode rejection on a wider bandwidth,

without affecting the main differential path. The technique

exploits positive feedback to introduce a zero that enhances

the phase margin of the CMFB loop, thus allowing a higher

gain to be used for the error amplifier. Simulations in a

0.13 lm CMOS technology show the advantages of the

proposed technique.

Fig. 23 Common mode point. Power supply voltage sweep (solid)

and temperature sweep (dashed)

Fig. 24 Accuracy of the overall amplifier with the proposed BD-

PFFC for the common-mode loop. Amplifier output (solid) and input

signal (dashed)

Fig. 25 Accuracy of the overall amplifier with the standard buffered

SC-CMFB. Amplifier output (solid) and input signal (dashed)

Fig. 26 Common mode response of the overall amplifier with BD-

PFFC technique (solid) and the standard buffered SC-CMFB (dashed)

46 Analog Integr Circ Sig Process (2013) 74:33–48

123

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Francesco Centurelli was born

in Rome, Italy, in 1971. He

received the Laurea degree

(cum laude) and the Ph.D.

degree in Electronic Engineer-

ing from the University of

Rome ‘‘La Sapienza’’, Rome,

Italy, in 1995 and 2000,

respectively. From 2000 to 2006

he worked under research con-

tracts with the Electronic Engi-

neering Department of the

University of Rome ‘‘La Sapi-

enza’’, and since November

2006 he has been a full time

Researcher for the same Department. He has published more than 60

papers on international journals and refereed conferences, and is a

member of the Institute of Electrical and Electronics Engineers

(IEEE). He is a referee for the following international journals: IEEE

Transactions on Circuits and Systems, IEEE Transactions on VLSI

Systems, Journal on Circuits Systems and Signal Processing, Journal

on Circuits Systems and Computers, and for international

conferences.

Andrea Simonetti was born in

Rome, Italy, in 1974. He

received the Laurea degree and

the Ph.D. degree in Electronic

Engineering from the University

of Rome ‘‘La Sapienza’’, Rome,

Italy, in 2003 and 2008,

respectively. From 2008 to 2011

he worked under research con-

tracts with the Electronic Engi-

neering Department of the

University of Rome ‘‘La Sapi-

enza’’, and since November

2010 he has also an Automotive

Power Electronic Design Engi-

neer at the Mesar Labs (Rome).

Alessandro Trifiletti was born

in Rome, Italy, in 1959. He

received the Laurea degree in

Electronic Engineering from the

University of Rome ‘‘La Sapi-

enza’’, Rome, Italy. From 1991

he worked under Research

Assistant with the Electronic

Engineering Department of the

University of Rome ‘‘La Sapi-

enza’’, and since 2003 he has

been an Associate Professor for

the same Department. He has

published more than 120 papers

on international journals and

refereed conferences, and is the co-inventor of four international

patents. His research activity was mainly concerned with integrated

circuits design and focused on design methodologies able to guar-

antee robustness with respect to parameter variations in both analog

circuits (microelectronic, radio frequency and microwave applica-

tions) and digital VLSI circuits.

48 Analog Integr Circ Sig Process (2013) 74:33–48

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