Information Processing Letters 82 (2002) 155–157

An exponential gap with the removal of one negation gate

Shao-Chin Sunga, Keisuke Tanakab,∗,1

a School of Information Science, Japan Advanced Institute of Science and Technology,1-1 Asahidai Tatsunokuchi, Ishikawa 923-1292, Japan

b Department of Mathematical and Computing Sciences, Tokyo Institute of Technology,1-12-1 Ookayama Meguro-ku, Tokyo 152-8552, Japan

Received 1 December 2000; received in revised form 21 June 2001Communicated by L.A. Hemaspaandra

Keywords:Computational complexity; Circuit complexity; Negation-limited circuits

1. Introduction

We do not know much about the complexities ofcombinational circuits (i.e., circuits with AND, OR,and NEGATION gates) for explicitly defined func-tions. Even a superlinear lower bound to combina-tional circuit size is not known. On the other hand, thecomplexities of monotone circuits (i.e., combinationalcircuits without NEGATION gates) for many explic-itly defined functions are well understood. For exam-ple, exponential lower bounds to the size of monotonecircuits are known [1–3]. Exponential gaps betweenmonotone and combinational circuit complexity havealso been shown [4,3], so we cannot generally derivestrong lower bounds to combinational circuit complex-ity using the bounds of monotone circuit complexity.

In this situation, there is no doubt that it is necessaryto understand the effect of NEGATION gates inorder to obtain good lower bounds to combinationalcircuit complexity. This motivates the study of the

* Corresponding author.E-mail addresses:son@jaist.ac.jp (S.-C. Sung),

keisuke@is.titech.ac.jp (K. Tanaka).1 Work done while the author was at NTT Information Sharing

Platform Laboratories.

relationship between the number of NEGATION gatesand combinational circuit size.

2. Definitions and preliminaries

Let f be acollection of Boolean functionsf1, . . . ,

fm defined on{0,1}n. We also callf an n-inputm-output Boolean function. We denote byC(f ) orC(f1, . . . , fm) thecircuit complexityof f , i.e., the size(number of gates) of the smallest circuit consisting ofAND, OR, and NEGATION gates with inputs

x1, . . . , xn

and outputs

f1(x1, . . . , xn), . . . , fm(x1, . . . , xn).

We call a circuit with no more thanr NEGA-TION gates anr-circuit. We denote byCr(f ) orCr(f1, . . . , fm) the size of the smallestr-circuit com-putingf . If f cannot be computed with onlyr NEGA-TION gates, thenCr(f ) is undefined.

A chain C in the Boolean lattice{0,1}n is anincreasing sequencea1 < · · · < ak ∈ {0,1}n. Thedecreaseof f on C is the numberi � k such thatfor somej , fj (a

i−1) > fj (ai). We defined(f ) as

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156 S.-C. Sung, K. Tanaka / Information Processing Letters 82 (2002) 155–157

the maximum decrease off on any chainC. Noticethat d(f ) � n (d(f ) = n is attained for somef ).Markov [5] has shown thatb(d(f )) NEGATION gatesare necessary and sufficient to computef , whereb(x) = �log2(x + 1), the number of bits in theshortest binary representation ofx. Thus, Cr(f ) isalways defined forr � b(d(f )). In this paper, alllogarithms are base two.

3. Previous results

The result of Fischer [6] shows that, foranycollec-tion f of Boolean functions defined on{0,1}n, there isonly a small gap between the size of a combinationalcircuit and that of ab(n)-circuit. Combining this withthe result of Beals, Nishino, and Tanaka [7] yields thefollowing proposition.

Proposition 1 (Fischer, Beals–Nishino–Tanaka).Forany collection f of Boolean functions defined on{0,1}n,

Cb(n)(f ) � 2C(f ) + O(n logn).

Tardos [4] pointed out that there is a polynomialtime computable function whose monotone circuitcomplexity is exponential. This function is the so-called Lovászϑ function introduced by Lovász [8] tostudy the Shannon-capacity of graphs.

Proposition 2 (Tardos). There exists a monotoneBoolean functionFn defined on{0,1}n such thatC(Fn) is bounded by some polynomial inn, and

C0(Fn) = exp(�(n1/6−o(1))

).

By Propositions 1 and 2, the following propositionis shown.

Proposition 3. Let F(n) be the function in Proposi-tion 2. If n + 1 is a power of two, then there exists anintegert (0� t � log(n + 1) − 1) such that

Ct (Fn)

Ct+1(Fn)= exp

(�(n1/6−o(1))

).

Proof. Observe that there is an exponential gap be-tween the sizes of a monotone circuit and a log(n+1)-circuit computingFn, while the difference in the num-bers of NEGATION gates is only log(n + 1). ✷

From Proposition 3, we cannot uniquely determinethe value oft . Actually, t can range over log(n + 1)

different values. In other words, we can say nothinggeneral about circuit size when we delete NEGATIONgates one by one from an optimalb(n)-circuit comput-ing Fn.

Recently, Tanaka and Nishino [9] defined ann-inputfunctionHn as

Hn(w1, . . . ,wm−1, x1, . . . , xm+2)

= w1 ⊕ · · · ⊕ wm−1 ⊕ Fm+2(x1, . . . , xm+2),

whereFn is a function in Proposition 2,n + 1 is apower of two,m = (n− 1)/2, and showed that there isan optimal log(n + 1)-circuit that computesHn, fromwhich the removal oftwo NEGATION gatesmustcause exponential growth.

Proposition 4 (Tanaka–Nishino).If n + 1 is a powerof two, then there exists an integert (log(n + 1) − 2 �t � log(n + 1) − 1) such that

Ct (Hn)

Ct+1(Hn)= exp

(�(n1/6−o(1))

).

The above proposition indicates thatt can rangeover only two different values, however, the value oft is not still uniquely determined.

4. Results

Using a functionHn as defined above, we define ann-input two-output functionKn as

Kn = (Hn,Hn ).

Here we show that there is an optimal log(n + 1)-circuit that computes a two-output functionKn, fromwhich the removal ofoneNEGATION gatemustcauseexponential growth. The value oft is now uniquelydetermined. This partially answers an open problempresented by Fischer [10]: “how much must the size ofthe network increase in order to achieve the minimalnumber of negations?”

Theorem 5. If n + 1 is a power of two, then

C log(n+1)−1(Kn)

C log(n+1)(Kn)= exp

(�(n1/6−o(1))

).

S.-C. Sung, K. Tanaka / Information Processing Letters 82 (2002) 155–157 157

Let f be a collection ofn-input symmetric Booleanfunctions, each of which depends only on the numberof ones in an input off . Suppose thatd(f ) = m,wherem = 2r −1 for some integerr. Tanaka, Nishino,and Beals [11,7] have shown that the NEGATIONgates in anyr-circuit computingf must compute thenegations of the bits of the binary representation of thenumber of ones in an input off .

Proposition 6. Let f be a collection ofn-inputsymmetric Boolean functions such thatd(f ) = m,wherem = 2r − 1 for some integerr. Consider anyr-circuit ∆ computingf . Label theNEGATION gatesN1, . . . ,Nr in such a way that the input toNi doesnot depend on the outputs of any of the negation gatesNi+1, . . . ,Nr . Let zi be the function computed at theinput of Ni . It follows that z1z2 . . . zr is the binaryrepresentation of the number of ones in an input off .

SinceFm+2 is monotone, the maximum decreased(Kn) is m = (n − 1)/2. Thus, from the theorem ofMarkov [5], log(n + 1) − 1 NEGATION gates arenecessary and sufficient to computeKn.

Lemma 7. Let r = log(n + 1) − 1. Consider anyr-circuit ∆ computingKn. Label the NEGATIONgates N1, . . . ,Nr in such a way that the input toNi does not depend on the outputs of any of thenegation gatesNi+1, . . . ,Nr . Let zi be the functioncomputed at the input ofNi . It follows thatz1z2 . . . zr

is the binary representation of the number of ones in{w1, . . . ,wm−1,Fm+2}.

Proof. Since {w1, . . . ,wm−1} ∩ {x1, . . . , xm+2} = ∅,the value of Fm+2 can be changed independentlyof w1, . . . ,wm−1. Fm+2 is a non-constant monotonefunction over{x1, . . . , xm+2}. Thus, we can regard thevalue ofFm+2(x1, . . . , xm+2) as a new variable,wm,independent ofw1, . . . ,wm−1. ∆ includes onlyr =log(n+1)−1 NEGATION gates, which are necessaryand sufficient to compute them-input parity functionand its complement simultaneously. Therefore, we canapply Proposition 6 to∆. ✷Lemma 8.

C log(n+1)−1(Kn) = exp(�(n1/6−o(1))

).

Proof. Consider the sub-circuit computingz1 in a(log(n + 1) − 1)-circuit computingKn. By Lemma 7,this sub-circuit is monotone and computes the ma-jority function over{w1, . . . ,wm−1,Fm+2}. By fixing(m−1)/2 variables in{w1, . . . ,wm−1} to ones and fix-ing the other variables in{w1, . . . ,wm−1} to zeros, weget the functionFm+2(x1, . . . , xm+2) at the output ofthe sub-circuit. Combining this with Proposition 2, wehave

C log(n+1)−1(Kn) � C0(Fm+2(x1, . . . , xm+2))

= 2�(m1/6−o(1))

= 2�(n1/6−o(1)). ✷C(Kn) is bounded by some polynomial inn. From

Proposition 1,C log(n+1)(Kn) is also bounded by somepolynomial inn. From this and Lemma 8, we obtainTheorem 5.

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