an atm switch starburst packet switch...
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AN ATM SWITCH USING
STARBURST PACKET SWITCH
FABRIC
Massoud Hadjiahmad
A thesis submitted in conformity with the requirements
for the degree of Master of Applied Science,
Graduate Department of ElectricaI and Cornputer Engineering, in the
University of Toronto
@ Copyright by Massoud Hadjiahmad 1998
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An ATM Switch Using Starburst Packet Switch Fabric
A thesis submitted in confomity with the requirements
for the degree of Master of Applied Science,
Graduate Department of Electrical and Cornputer Engineering, in the
University of Toronto, 1998
by
Massoud Hadjiahmad
ABSTRACT
In this thesis, we present the design and analysis of an ATM switch using the Starburst packet
switching architecture. The first part of the thesis provides an introduction to ATM network
concepts and specifications, Starburst packet switching lntegrated Circuit, and the board design
of the Starburçt cell switch fabric. This introduction provides an ovewiew on the intemal
structure, functional and design requirements of intemal modules, and the overall picture of an
ATM switch in the network.
The second part of the thesis presents aie design of the Il0 module and system controller
interface. This portion of the aiesis defines the interface between vanous bfocks of the switch,
design criteria, and design implementation. The implementations are in the form of state
diagrams, and schernatics. Furthemore, guidelines and pointers are provided to enable future
hardware and software irnplementation of the Starburst ATM switch.
It is a pleasure to acknowledge rnany people who have diredy or indirectly cantnbuted ta the
contents of this thesis. First and foremost, I would like to thank Professor A Leon-Garcia for his
guidance and support airough the course of my MASc. work, and for many helpfut discussions
that contributeci to the design of the proposed Starburst switch.
Thanks go to my thesis cornmittee, Professors A Leon-Garcia, P. Chow, A Banejea, and 1.
Katzela. Thanks go to Professors K Sharifi and S.K Chan for reading some of the early
manuscripts and their guidance. 1 am gratefuf to Mehran Shirazi for his guidance in software
implementation of the Starburst switch.
Finally, I would like to thank my famiiy fUr the support and encouragement
To My parents and Minu
Table of Contents
1-1 ATM NETWORKS .................................................................................................................................. 2
1.2 ATM CONCEPTS .................................................................................................................................... 4
............................................................................................... 1.2.1 A TM Prochrct Design Requirements 6
.............................................................................................. 12- 1.1 Physical Laya Functions for 155.52 Mbps 8
........................................................................................................ .................. 12-12 Headcr Error Conuol ..-.. 8
.............................................................................................................. 1 .2.1.3 CeU Delincation and Snambling 9
.................................................................................................... 12.1.4 Routing & Switching Impitmtntation 10
............................................................................................. 1 -3 GENERAL ATM SWCH ARCHITECïüFE I l
............................................................................................................................... 1.3.1 Inpul Module I I
1.3.2 Ourput Module .............~~~.~~.~..~~~~~~~...~~~~~..~~~~~~~~~~~..~~.~.~....~~.......~...~.~...~...~..~..........~~~.~...~~.~.~.~.~~~..~.~~ 13
. . 1-33 Connec tion Arimrssron Control .................~...~.............................................................................. 1 4
1.3.4 System Mpnagement ...............................~.....~....~.............~~.......................................................... 1 5
........................................................................................................................ 1.3.5 Cell Switch Fabric 15
1.4 THEsrs OVERVIEW .............................................................................................................................. 16
2.1 m o ~ u c n o ~ ....... .... .................................................................................................................... 19
....................................................................................................... 2 2 STAR SUR^^ CHIP ARC HI TE^ 2 0
............................................................................................................... 2.2.1 Starburst Packet Format 20
.............................................................................................................................. 2.2.2 Sort Networh -22
................................................................................................................................ 2.2.3 Tmp Network 22
........................................................................................................................... 2.2.4 Banyun Network 23
2-3 STARSW C m OPERATION ............................................................................................................. 2 3
2.4 STARsURsr CSF ................................................................................................................................. 2 4
........................................................................................................ 2.4. 1 Starburst CSF Repuements 28
3. I/O MODULE .--Nl---WIMI-.--U.U - 2 9
.............................................................................................................................. 3.1 m O D U C ï i û N 29
3 2 DESIGN OVERVlEW ............................................................................................................................ ..30
-3 ....................................................................................................................................... 3 3 OPERATION ..d 3
3.3.1 TrmceNers ........................................................................................................................... .......34
..... ......................................................................................... 3.3.2 Network Tenninarrinarron Corüroiler .., 34
................................................................................................... 3.3.3 A&ess T d d o n ControIIer -36
......................................................................................................................... 3.3.4 Srarburst Arinpter 37
3.3.4.1 NTC-SBA lntcrface ConmUer ............................................................................................................... 39
3-3-42 SBA Rcceive Opaatio IL ......................................................................................................................... 40
33.4.3 SBA Transmit Operation ........................................................................................................................ 43
.... 4 . SYSTEM CONTROL INTERFACE ..-.--...--................ .............. 45
..................................................................................................................................... 4.1 INTRODUCTION 45
............................................................................................................................... 4 2 DESIGN OVERViEW 46
......................................................................................................................... 4.3 PCI Bus CONTROLLER 48
................................................................................................ 4.4 MEMORY MAP/sOFTWARE FUNCIIONS 50
-- 4.5 SCIM ~ ~ A R E DESIGN ............................................................................................................ ......33
4.5.1 S'rem Conaolkr Mater R e d ............................ ........................................................................53
. . ................................................................................................... 4.5.2 Systern Controlier Mater Write 33
................................................................. ........................ 4.5.3 Sysrem ControIIer Tmget Read ... -57
4.5.4 System ControIIer Tmget Write ........................................................................................ tttttttttttt59
List of Tables
Table 1: PMD and TC Functiom for 155.52 Mbps ......................................................................................... 8
................................................................................... Table 2: FPGA Resottrce I/tiIbation for S ' A Design 39
......................................................................................................................... Table 3: SCIM Mernory Map 51
vii
List of Figures
......................................................................................................................... Figure f : An A TM Nemork... -3
........................................................................................................................................ Figure 2: A TM Cell -4
............................................................................................... Figure 3: UNI and MVI Cell Header Fonnats -5
...................................................................................................... Figwe 4: Cell Deiineation State Diagram 9
Figure 5: An ATM Switch Architecture ......................................................................................................... I 2
Figwe 6: Sfarburst ATMSw'tch Architecture ............................................................................................... 17
Figwe 7: A Simple Starbwst Swt'tch ...................................................... ...... . 19
Figure 8: Stmbwst P mket Format ............................................................................................................... 21
. . . Figure 9: EOP Corn1 Btt T m t g ................................................................................................................ 22
........................................................................................ . Figwe 10: Stmbursr Ch@ Architeczure Overview 23
Figure II: An fiampie of a 4x4 Starburst Ch@ Switching .......................................................................... 24
Figure 12: A Multi-stage Starbaust Switch .................................................................................................... 25
Figure 13: Starbum and VO Module Connections ...................................................................................... -26
Figure 14: Serial to Parallel Conversion of ATM Ceils ................................................................................ 27
Figure 15: Starbusr Data Stream ................................................................................................................. 27
Figure 16: Parailel to Swial Conversion of ATM Ce& ................................................................................ 27
Figure I 7: VO Module for the Starburst Switch ........................................................................................... 30
...................................................................................................................... Figure I 8: XyR-XVR Interface 31
.................................................................................................................... F i p e 1 9: XyR-NTC IntMace -31
Figure 20: NTC-A TC Inte face ..................................................................................................................... 32
Figure 2 1: NTC-SBA Interfie ...................................................................................................................... 32
.................................................................................................................. Figure 22: SCIM-IOM Inte$ime -33
Figwe 23: NTC to A TC Data Transjier ......................................................................................................... 36
........................................................................................................ Figure 24: ATC to NTC Data Tram&- -37
..................................................................................... Fi'e 25: S t a r b m Adapter Mochre Architecture -38
viii
.............................................................. Fi'e 26: NlCSBA Interfie ComdIer Receive Stme Diagram 39
............................................................ Figure 27: NTC-SBA Intetfoce Controller T r m i t S tae Diagrm 40
Figure 28: Starburst A w t e r Transmit State Diagram ................................................................................. 41
................................................................................................................... Figure 29: M e S ~ b t u s t Packet 42
............................................................................................ Figure 30: Valid Starbw-st Packer Genermatron -42
Figure 31: Stmbwst A h t e r Transmit State Diagram ................................................................................. 43
............................................................................................................... Figure 32: 1VTC pmkei Genermon 44
......................................................................................................... Figure 33: SCIM Harhume Structure -47
........................................................................... Figure 34: Stmbwst Switch Adciiess Decoding Structure -52
............................................................................................. Fi'e 35: SCAU Master Read State Diagram -54
............................................................................................. Figure 36: SCIM Marter Wrile State Diagram 56
.............................................................................................. Figure 3 7:SCIM Tmget Read Stme Diagram -58
................................................................................. Figure 38: SCIM Tmget Write to lVTC Srute Diagram 60
................................................................................. Figure 39: SCIM T- Write to ATC State Diagram 62
List of Appendices
APPENDIX A: STARBUEST SWTTCH SCHEMATICS AND CODES --.-.e."m-.U.----.u..66
1. Introduction
The convergence of communications and computers is now well underway and is transfoming
society. Many phone, cable, computer, and communication companies and organizations are
working to provide ancüor create various sewices and products for the building biocks of the
"lnforrnation Super Highway". The existence of a network that can connect a larger portion of
households, businesses and organizau'ons is inevitable. The need for an abundance of available
information, communications, and proper services is increasing as computer networks have
become part of the social and economic fabric of the globe. News and radio information,
education, training, finance, stock exchange, video conferencing, and games are a few examples
. of the vanous senrices that are provided by today's computer and communication networks. As a
result, lntegrated Services Digital Netwotks (ISDN) technology seerns more suited for these
applications.
The urge to use ISDN technology is largefy due to telecornmuters' need for remote access to data
networks offering full senrice, that includes the ability to transfer graphies, video, and other large
data files. Broadband ISDN (B-ISDN) is more suitable for these applications, because it can
provide more bandwidth (23 B + D) cornpareci to primary ISDN (2 B + O). Delta (O, 16 Kbps)
channels are used for control and signaling information white the Bearer (B, 64 Kbps) channels
are used to transfer voice, data, or any other sewices.
As the number and types of senrices, connections, and resources increase, a scaleable network,
that can provide users with a number of required services without loss of quality, speed, and
secuiity becornes essential, The network shouId be able to provide and maintain the required
quality of servi- (QoS) for all calts in progress. QuaMy of service parameters will be difierent
arnong various services. Asynchronous Transfer Mode ( A m ) is a connection-ofiented network
service. It is a high-bandwidth, fast-packet switching and mutüplexing technique that can
guarantee QoS for calls in progres- It segments packets of payload information into 53-byte
cells and supports voice, audio, data, documents, images, and video. ATM along with
Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SON tr) are
technologies that enable broadband ISDN.
ATM products such as switches, routers, and adapters rnust be developed to equip ATM
technology witb the abiiity to provide communication and computer networks with various
services. This document discusses some of the possibilities in design and implementation of an
ATM Switch. The design uses the Starburst packet switch fabric [6] that was developed at the
University of Toronto.
This thesis consists of five chaptets. The remainder of this chapter provides an introduction to
concepts, specifications and requirements of ATM networks. It also gives a general ovewiew for
design and implementation of an ATM switch. The final section of this chapter previews the
design of the ATM switch that is the topic of this thesis.
Chapter 2 provides a brief introduction to the design of Starburst chip and Starburst switch fabric.
The design of the Il0 module and System Control Interface for the Starburst ATM swïtch are
discussed in Chapters 3 and 4, resWvely. Recommendations and future directions for
implementation and completion of the Starburst ATM switch are provided in Chapter 5.
1.1 A TM Networks
There is an unprecedented level of acceptance throughout the industry of both the technology and
the standardkation process. ATM has grown out of the need for a worldwide standard to allow
interoperability of information, regardless of the "end-system" or type of information (Figure 1).
2
Historicaliy, there have k e n separate rneaiods used for the transmission of information among
users on a Local Area Network (MN) versus users on the Wide Area Network ONAN). This
situation has added to the complexity of networking as uset s needs far connectivity expand from
the LAN to metropolitan, national, and finally worfd wide connectivity-
ATM NETWORK -- Vide0
Serve?
Mobile
Figure 1: An ATM Network
ATM is a method of communication which can be used as the basis for both LAN and WAN
technologies. Over tirne, the Iine between local and wide area networks will blur to fonn a
seamles network baseci on one standard - ATM. Today, in most instances, separate networks
are used to carry voice, data and video information, because these trafic types have different
characterktics. For instance, data trafic tends to be "bursty". Voie and video, on the other
hand, tend to be more even in the amount of information required, but are very sensitive to when
and in what order the information arrives. With ATM, separate networks will not be required.
ATM is the only standards based technology which has k e n designed from the beginning to
accommodate the sirnultaneous transmission of data, voice and video.
1.2 A TM Concepts
As descrÏbed in the previous section, ATM is the emerging standard for communications. This is
possible, because ATM is available at various speeds from Megabits to Gigabits. ATM
Technology is bas& on powerful, yet flexible concepts. For instance, when information needs to
be cornmunicated, the sender negotiates a "requested paW with the network for a connection to
the destination. M e n setting up this connecüon, the sender specifies the type, speed and other
attributes of the cal1 that detennine the end-to-end quality of service.
Figure 2: ATM Celf
Header (5 Bytes)
Another key concept is that ATM is a switch based technology. By providing connectivity through
a switch (instead of a shared bus) several benefits such as dedicated bandwidth per connection,
higher aggregate bandwidth, and flexible access speeds are provided. ln ATM networks,
information to be sent is segmented into fixed length cells, transported to and re-assembled at the
destination. An ATM ceIl has a fixed lengtti of 53 bytes (Figure 2). Using k e d length ceils allows
the information to be transported in a predictable manner. This predictability accommodates
different traffic types on the same network The ceIl is broken into two main sections, the header
and the payload. The payload (48 bytes) is the portion which cames the actual user payload
information-either voice, data, or video. The Header (5 bytes) implements the addressing
mechanism.
l nformation Field (48 bytes)
There are two types of ce11 header structure for ATM cells. One format is used for the User
Network Interface (UNI) and the other format is used for the NeWork Node Interface (NNI).
These two structures have very similar fofmats. The only difference in the structure is mat in NNI
format, the Generic Flow Control (GFC) bits are replaced by extended Virtual Path Identifier
VI), as shown in Figure 3.
I GFC (for UNI) 1 VPI (for NNI) l WI I ' 1 1
- --
VCI
VCI
4 8 7 Bits / Octctr 3
HEC
6
CLP : Ce11 L o s Priority
GFC : Gaieric Fiow Conml
PT: Payload Type
5 2
3 VC l
HEC : Hcader E m r Conml
VPI : Vinual Path lndattifia
VCI: vimial Channel Identifier
1
Figure 3: UNI and NN1 Cell Header Formats
PT
ATM is a layered architecture allowing multiple senrices like voice, data and video, to be rnixed
over the network Three lower level layers have been defined to implement the features of ATM.
The Adaptation layer assures the appropriate service characteristics and divides al1 types of data
into the 48 byte payload that will make up the ATM cell. The ATM layer takes the data to be sent
and adds the 5 byte header information to ensure the cell is transmitted on the correct connection.
The Physical layer defines the electrical characteristics and network interfaces. ATM is not tied to
a specific type of physical transport
CLP
ATM has several key benefits:
ATM provides a single network for al1 trafic types and it allows for the integ ration of
networks improving efficiency and manageability.
ATM Enables new applications (due to its high speed and the integration of trafic types,
ATM will enable the creation and expansion of new applications such as multimedia to
the desktop.)
ATM provides wrnpatibility. Sinœ ATM is not based on a specific type of physical
transport, it is compatible with currenüy deployed physical networks. ATM can be
transporteci over twîsted pair, coax and fiber optics.
ATM simplifies Network Management, Le. ATM is evoiving into a standard technology for
local, carnpus/backbone, public and private wide area services. This uniforrnity is
intended to simplify network management by using the same technology for al1 levels of
the network
ATM provides Long Architectural Lifetirne. The information systems and
telecommunicab'ons industries are focusing and standardizing on ATM. ATM has been
designed from the onset to be scaleable and flexible in:
Geographic distance,
Number of users,
Access and trunk bandwidths (As of today, the speeds range from Megabits to
Gigabits).
A TM Product Design Requirements
The requirernents for design of an ATM product can be divided into two categories. Physical
characteristics is one of these categories that is dependent on the type of connedion and the bit
rate to be used for the network connection. The type of connectÏon wiring is, in tum, categorized
to rnany different types such as coaxial cable, Unshielded Twisted Pair (UTP-3, UTP4, UTP-5),
Shielded Twisted Pair (STP), Foiled Twisted Pair (FIT), Single Mode Fiber (SMF), Mulü-Mode
Fiber (MMF), etc. There are also various bit rates (such as 25.6 Mbps. 52 Mbps. 100 Mbps,
155.52 Mbps, and 622 Mbps) that can be used in combination with the wire type to implement
ATM routers, adapters, switches, and other products. Use of electrïcal or optical signais would
a h provide the network with more choices in implementing the connections and modules.
The second category is the operational characteristics that is independent of the type of
connections, signals, and bit rates. mese requirements consist of emr detecüon/correction, VPI
andfor VCI rouüng, routing updates, Operation and Management (OAM) cell recognition, etc.
As a result, design of an ATM product is highly dependent on the topology of the network it is
connected to. Some of the important parameters that have to be considerd are:
Clock recovery and detection of cell boundaries.
Bit rate and interface symmetry (Le. the same bit rate in both transmission
directions).
Physical characteristics (optical or electrical).
I nterfacdattenuation range,
Transmission medium,
Connectors.
Line coding - most important feature of line coding is to maintain DC balance of data
transmission over optical or elecûical media in high transmission rates.
Operating wavelength (for optical lines),
The functions of the physical layer in ATM network modules and interfaces are generally grouped
into Physical Media Dependent sub-layer (PMD) and Transmission Convergence (TC) sub-layer.
The functions of these sub-layers may Vary depending on chosen bit rate and wire connedon,
1.2.1 .1 Physical Layer Functions for 155.52 Mbps
The Physical Layer design for the 155.52 bit rate can be implemented using optical fiber, UTP-3,
UTP-4, üTP-5, STP, and FTP. The basic difference between various types of link connections is
the amount of loss and bandGdth that they offer. The lossy characteristics of the links provide a
metric for calculating the maximum length of the link The maximum bandwidth of each type of
wire (fiber) is used to define the link speed of the Physical Layer. The ATM cells are
recomrnended to be transmitted using eiaier SONETISDH frarnes or no frames. The general
functions of the PMD and TC sub-layers for a private UNI are shown in Table 1-
, - - - - - - - -- - - -- , - - - - - - Transmission Convergence
- - - - - -
Table 1: PMD and TC Functions for 955.52 Mbps
Physical Media Dependent
1.2.1.2 Header Error Control
- - . - - -. - - . . - - - - - . - - - - - - - - -
HEC generation Iverification Cell scrambling/descrambling Cell delineation (HEC) Path signal identification (C2)
Bit timing Line coding Physical medium scramblingldescmmbling
The Header Emr Control (HEC) field of the ATM cell header (shown in Figure 3) is calculated
using the first four octets of the header. The code used for this function is capable of single-bit
error comcüon, or multiple-bit emr detection. The notation used to describe the HEC is bas&
on the property of the cyclic codes. The polynomial representing the content of aie header is
generated using the first bit of the header (excluding the HEC field) as the coefficient of the
highest order tem. The HEC field is the remainder of the modulo two division by the generator
Frequency justiftcationiPointer processing ScrambIing/descrambling (SONtT) Transmission frame generation/recovery I
polynomial x8 + x2 + x + 1 of the productx8 rnultiplied by the first four octets of the header. To
hprove the performance of the cell delineation in the case of bitiiips, the calculated check bits
are added to an &bit pattern (01010101) before k ing inserted as HEC field. At the receiver end,
HEC field must su btract the Mit pattern before attempting to check far errors.
1
Hunt (Bit by Bit)
t f
SYNC PRESYNC (Cell by Cell) (Cell by Cell)
1 A
DELTA Consecutive Correct HEC - -
For SONEWSDH-based physical layer: ALPHA =7, DELTA = 6
For dl-based physical layer. ALPHA = 7, DELTA = 8
Figure 4: Cell Delineation State Diagram
1.2.1.3 Cell Delineation and Scram bling
Cell delineation process uses HEC field of the ATM ceIl to identify cell boundaries, while
scrarnbling process is useci to improve the secutity and robustness of the cell delineation
mechanism. The scrarnbling mechanism also helps with randorn~ing the data in the information
field for possible improvements in transmission performanœ and mu& not after the ATM header
structure, HEC, and ceil delineation algorithm. The &te diagram of the ceIl delineation process is
shown in Figure 4.
ALPHA and DELTA parameters are to be chosen such that the cell delineation becornes as
secure and mbust as possible while satisfying the performance requirements. Robustness
against false misalignrnents due to bit errors depends on the ALPHA parameter, while robustness
against false delineation in the synchronization proceçs depends on DELTA Scrambling
procedure varies with the type of transmission and transmission rate 121.
1.2.1 -4 Routing B Switching lmplementation
Information provided in the ATM cell header is used to route each cell from source to destination.
The routing is based on the VPI and VC1 values provided in the cell header. At each node, values
of VPl and VCI are used to access routing tables. These routing tables provide the node with
new VPI andior VCI values for the incoming ATM cells, as well as choosing an output port for the
cells. As it can be seen from figure 3, the cell header contains an 8-bit VPI field and a 16-bit VC1
field (for UNI cell format); Le. there can be a maximum 28 x 216 different combinations that a
routing table wuld contain. This would require a large amount of memory in which to maintain al1
the information corresponding to each combination. As a result, it is not necessary for al1 the
nodes to maintain a database for al1 different combinations.
The number of bits of VPI and VCI fields that are used for routing is negotiated between the user
and network. This number is determined on the basis of the lower requirernent of the user or the
network The routing bits are chosen from the least significant position of VPI (beginning at bit 5
of second octet of the cell header) and VCI (beginning at the bit 5 of fourth octet of the cell
header) fields. The unused routing bits of VPI and VCI are set to zero. Routing table updates are
10
required to impmve robustness and efficiency of ATM networks. These upûates have to be done
at al1 the nodes when required. As a result, each node would require some type of management
to implement the required changes and provide the physical layer with access to the updated
information.
There are a number of preassigned [l] cell header values that are used for signaling, OAM. flow
contml, and idle cells. ldle cells cause no action at the receiving node except for ceII delineation
including HEC verifidion. These cells are inserted and discarded for cell rate decoupling and
are not passed to the ATM layer. lt seern rather obvious that ceIl type recognition is an important
task of the Physical and the ATM layers. The ATM layer functions, such as genera1 fiow control,
can be implernented using an operation and management interface with the Physical Layer.
1.3 General A TM Switch Architecture
As mentioned in earlier sections of this chapter, design and implementation of an ATM product
will require the study of vanous ATM specifications and standards. Having a general
understanding of ATM concepts, it is possible to deduce a general ovenriew of an ATM switch (or
any other product). This generaked switch architechire m can serve as a starting point in
design and implementation of various modules that are required in the implementation of the
Starburst switch. Therefore, an ATM switch can be visualized to be comprised of a set of
modules and predefined funcb'ons for each module. A general architectural overview is provided
in Figure 5. The following sections will provide a brief description of the functions that each
module should provide.
1.3.1 lnput Module
This module provides an interface between the incoming SONEUATM ceII bit stream and the
intemal processes of the switch- To provide the intemal switch modules with ATM cells and
network information, the lnput Module (IM) would require to perform PM0 and TC sub-layer
functions in the receive direction. The following a brief list of functions that IM should provide:
Processing of SONFT overtread; If the switch supports SONtT framing for the ATM
cells, the IM must be compliant with SONە standards.
Cell rate decoupling (removal of IdleiUnassigned cells from the inmming ceII stream).
Cell delineation and ceIl payload descrambling'.
Buffer Management I I I Routing I+~EI{
I I
Buffering I I
- ATMISONET
CSF
SM: System Management IM: Input Module OM: Output Module
CAC: Ca11 Admission control CSF: Cell Switch Fabric
Figure 5: An ATM Switch Architecture
Addition of an intemal tag; This will be required for most switches due to the fact that
most ATM switching nodes support only a subset of al1 possible VPINCl connections.
Depending on the Cell Switch Fabric (CSF) intemal architecture the size of the tag varies.
' The scrambling/descrambling polynornial recommended by ITü-1.432 is (x a + 1 ).
12
The tag rnay also include sbtistical information the can be accessed and interpreted b!r
the system management
Emr checking in the ceIl header using HEC field;
Validation and translation of VPlNCl values; VPI and/or VCI masking and filtering
can be performed and a look up table is generaliy used to provide the incoming cells with
a new set of VPlNCl values.
Determination of the destination output port; This is required to detemine through
which output port the incoming cells must be transrnitted- This information can be
provided in the tag if intemal tags are used for routing.
However, the functions that are supported by the Input Module can be increased or reduced
depending on the exact implementation and requirements of the switch and the network. For
instance, the IM may be required to
Extract and transfer signaling cells to the CAC module,
Extract and transfer management cells to the SM module.
7-32 Output Module
The Output Module (OM) provides an interface between the internal processes of the switch and
the outgoing SONETiATM cell bit strearn. To provide the ATM network with ATM cells (SONET
frames), statistical, and control information the Output Module is required to perforrn PMD and TC
sub-layer functions in the transmit direction. The following is a bnef list of functïons that OM
should provide:
Removal of internal tag; The tag that was added by the IM should be removed before
ATM cells are transmitted. Any switching statistical information, if provided by the hg,
can be retrieved at this point
HEC field generaüon and cell payload scrambling.
Cell rate decoupling (Insertion of Idle/Unassigned cells in the outgoing cell stream).
Mapping celis into SONtr payloads and generating SONET overhead.
However, the functions that are supported by the Output Module can be increased or reduced
depending on the exact implementation and requirements of the switch and the network For
instance, the OM rnay be required to:
lnsert signaling cells, from CAC, in the outgoing cell stream,
Insert management celts, from SM, in the outgoing cell Stream.
t3.3 Connection Admission Control
An ATM switch must be able to interact with the network and provide certain functions. One set
of these functions are the traffic controt functions. Traffic control functions are performed by the
Connecb'on Admission Control (CAC) module in an ATM switch. CAC uses signaling cetls to
establish, modify, or teminate a connection. These connections provide the users with the
required sewh, bas& on the available network resources. In general, a wnnection request is
received (via signaling cells) and the request is processed by a decision making unit inside the
CAC. If the required (VP and/or VC level) resources for the new request are available the
connedion is granted and the QoS must be maintaineci while the connection is active. The
following is a brief Iist of functions ta be provided by the CAC:
Establishment, maintenance & temination of connections at the VP and VC levels.
Interface with a signaling network
Negotiation of traffic contracts with users.
Connecb'on request admissionlrejection based on the VP and VC available
resources.
Ailocation of switch resources for VPCsNCCs, includ ing routing selection.
1.3.4 System Management
System Management (SM) is a complex module due to the important responsibiiiües that ttiis
moduie must provide. In general, SM is responsible for the correct and efficient operation of the
switching system. It must, also, support network-wide operations and management The level of
complexity of the SM is dependent on what management (fault, performance, configuration,
accounting, security, and trafic) functions are to be implernented and how detailed these
implementations are going to be. It is possible to design and implement the SM moclule to
provide the minimum functions and improve the module as more cornplex functions are needed.
The folIowing provides a brief Iist of the functions that should be supported for an SM module:
Physicaf-layer & ATM-layer OAM.
Usage measurement of switch resources.
Traffic and customer-network management
Security control of switch database.
Interface with operations systems and Telecommunications Management Network
Crrurw
1.3.5 Ce11 Switch Fabric
The Cell Switch Fabric (CSF) is prirnariiy responsible for transfemng cells beniveen other
functional blocks in the switch, depending on the switch architecture. However, the main fundion
of the CSF is to transport the user data cells from the Input Module to the Output Module. The
following lists a few of the functions that the CSF may provide bas& on the switch architecture:
Transfers cells between other functional blocks in the switch:
User data cells are routed between IM and OM.
Signaling & management cells may be routed to the CAC or SM through
special ports on the fabric-
Cell buffen'ng.
Trafic concentration and muiüplexing.
Mulücasting or Broadcasting.
Cell scheduling based on delay priorities.
Selective cell discarding based on loss priorities.
7.4 Thesis Ovewiew
The objective of this thesis is a çomprehensive design and implementation of an ATM switch that
uses the Starburst packet switching IC as its Cell Switch Fabric are. The Starburçt ATM swtch
architecture can be seen in Figure 6. This switch hardware will consist of a 16x7 6 CSF core, 16
Il0 Module (IOM) ports. and a Systern/Control interface. The Connection Admission Control and
System Management functions will be implemented in software. The initialization. access, and
updates of IOMs and control signals for the hardware portion of the switch will be transferred
through the PCI bus interface to the SystedControl Interface Module (SCIM). Design of al1
hardware and software modules, except for the Starburst CSF, was implemented in this thesis.
This thesis presents a wmplete design for the IOM hardware including schematics, state machine
design, and VHDL code for the Starburst Adapter (SBA)2. The SBA adds Starburst packet
heade? to the incoming ATM cells and later removes them from the outgoing ATM cells. The
SBA is designed to be implemented in an FPGA or PL0 device.
The SBA is a proprietary design that uses the Starburst packet format to frarne the ATM cells and
there are not any products in the market that can implement its task. The SBA design was
wntten, in VHDL cade, simulated synthes~ed, and Mted in a Xilinx FPGA. The SCIM boundary
interface signals for lOMs and the PCI bus controller are also provided (Figure 17) as well as the
See Appendix A for details. The Starburst packet header will be discussed in Chapter 2.
state machine design for transfkrring networking information and updates to and from the PCI bus
controller and IOMs.
Figure 6: Starburst ATM Switch Architecture
Memory map design, IOM initialkation procedure, IOM register access. PCI controller intempt
handling, and VPlNCl look up table updates are also presented to provide a comprehensive
design solution for irnplementation of the Starburst ATM switch. Finally. an analysis of different
design options for various su&-blocks of Me switch and suggestions for Mure implementation of
the Sbrburst switch is discussed.
The design of the Il0 and System Control modules presented numemus challenges in
researching ATM design specifications, understanding Starburçt CSF requirements, selecting the
most feasibie products that implement ATM fundons and can be easily adapted to meet the
Starbunt CSF requirements, learning PCI bus architecture and specificatons, and implemenüng
the SBA module- Although aiese challenges were frustrating at times they rnotivated
improvements in elevating my knowledge and skiIJs in a wide range of issues and topics tbat is
required to implement a complete systern. The major challenge was being able to complete the
implementation of mis thesis in hardware and software with tirniteci resources and tinte. However.
what is presented here provides a e ground work for Mure hardware/sofhrcrare implementation of
the Starburst çwitch.
2. Starburst Switching Fabric
The Starburst chip was developed as a 'VLSI Systems Design' [4] project at the University of
Toronto in 1993- The general design of the chip was bas& on 'A Flexible Packet Switch Wtth
Dedicated And Shared Output BufFeringm [3]. Although the Starburst chip does not contain any
intemal bufFering, it can be used to implement an ATM swïtch that provides a combination of
dedicated and shared buffering. A desirable feature of the Starburst chip is its expandability.
Several chips can be cascaded to increase performance, similar to the way memones are used to
improve the performance of cornputer systems.
. . . . - Starburst, . . . - Packets '.
Outgoing ATM CeIk
16 16 : : 16
Incoming Input *
starbunt
ATM Celis Module Chi p 16
Figure 7: A Simple Starburst Switch
output Module
Some of the charactefistics of the Starburst IC design are Iisted below:
Flexible dedicated and shared bufkr management scheme.
Non-blocking, colurnn-fiIl network (Batcher-Banyan),
Seif-routing (Le. vety high data rates).
Expandable (Le. wlurnn-fiIl modules can be added to improve performance).
Output buffering and priority packet transmission are used to reduce e M of Head of
the Line (HOL) blocking.
Provides routing and some buffering required for CSF imptementation.
Extra buffering at the input and a buffer management scheme wiIl improve the
performance of the Starburst CSF in meeting QoS requirements for various trafic
types-
2.2 Stahurst Chip Architecture
The Sbrburst chip delivers packets of fixed length from various inputs (e.g- data, voice, and
video) to the desired output The basic structure of the Starburst consists of a primary and
secondary Sort networks, a Trap network, a Banyan network, and a Delay network (Figure 10).
A 96x16 Starburst switch has switch fabric with 32 input and 32 output ports. Output ports 17 to
32 are used to provide buffering (Figure 7) and expandability (Figure 12) for the switch. A
simplfied version of a Starburst ATM switch is shown in Figure 7. As can be seen, a header
block must be added to the ATM cells before they can be routed to the correct output port The
input module adds the required Starburst Header (SBH) to the Am cells based on the ATM cell
header information to generate a Starburst packet while the output interface removes the SBH
from the Starburst packet to restore the ATM cell.
2.2.1 Stadurst Packet Format
The packet format for the Starburst chip is shown in Figure 8. The Starburst Header (SBH) bits
are assigned by the input module based on the roub'ng tables, Le. the IM reads the ATM cell
header information and recognizes the type of cell andlor its destination, Based on the
information provided in the look up table, the input module replaces the VPl\VCI values of the
incoming ce11 and also provides a tag for the SBH. The SBH contains the following fields:
Dumrny Bit This bit is a durnmy bit (hence the name). Its value is aiways set to zero.
This bit is required to preven: loss of data at the start of each Starburst packet The Ioss
of data occurs due to the appearance of End-Of-Packet (EOP) bit in the control sequence
(Figure 9). Once the EOP bit is set, it causes al1 the elements in the Sort, Trap, Banyan,
and Delay networks to be reset, at each stage of the Starburst chip. EOP bit also
controls the length of the Starburst packet
Figure 8: Starburst Packet Format
Split Bit: This bit is used to indicate a unique (S = 'O1) or duplicate (S = '1') packet of a set
of packets with the same destination address. The packets must be inside the Starburst
chip at the same time. The input module assigns zero to this bit by default
Active Bit: This field indicates an active (A = 'O8) packet or an inactive (A = '1') packet
Inactive packeb may be sent through the input ports of the switch to have a synchronous
operation. This bit can be assigned to be low or high by the input module.
Destination Bits: This field indicates for which output port of the Starburst chip a packet is
destined. The bits in this field can be assigned to indicate a value from '0000" to '1 II ln
by the input module.
Priority Bits: These bits Gan be used to give pnority to packets with respect to other
packets.
Age Bits: Each time a packet fails to reach its desireci output (due to cornpetition with
packets with the same destination bits), it is aged. The packet that enters the switch for
the first time has the age bits set to '1 3". Every unsuccessful trip through the &tch
reduces the Age Bits by one. Eacti packet, at most, can be aged to '00". These packets
will circulate through the &ch and eventually leave the CSF.
Figure 9: EOP Control Bit Timing
Payload: These bits correspond to the original ATM cell that entered the input module.
The header information for the ATM cell may be modified by the input module, based on
its destination and information.
2.2.2 Sort Networks
Each Sort network reorders Starburst packets at its input such that the packets at the output of
the sort network are in ascending order. This sorting is based on the bit order of the entire
packet
The Trap nenivork compares each incoming packet with its irnmediate higher numbered input port
If the destination of the two packets are the same, the packet at the higher numbered input is
tagged, by setting the Split Bit to '1'. If the destination of the two packets are not the same, the
Split Bit of packet on the lower numbered input is set to 'O'. This prevents two packets to appear
at the same output port
2.2.4 Banyan Network
This network examines the address bits of the input packets that are active, and routes the
packets to the appropriate output ports. The Banyan network [3] can route the packets to their
desired destination, if al1 the packets at its input ports are sorted in an ascending order and have
unique destination bits. If a packet is inactive, it wili be routed to any one of the availabie output
ports. This is due to the fact that the Banyan network has 16 inputs and 16 outputs.
f'Mnary , 32 Sort Network
A
Figure 10: Sbrburst Chip Architecture Overview
2.3 Stanburst Chip Operation
A simple example of the operation of the Starburst chip is shown in Figure 1 1. This operation of
the chip can be simplifieci as foilows:
Primary Sort network sorts the randorn input packets in an increasing order.
Trap network recognizes at most one unique packet for each output port of the
Starburst cbip.
Secondary Sort network sorts the unique and duplicate packets again so to direct the
unique packets to the Banyan network and the duplicate and inactive packets to the
Delay network.
Banyan network routes the ordered packets to their appropriate output ports (O to 15),
mets the Split bits to 'O' after ignoring any duplicate or inactive packet.
Delay network routes the duplicate and inactive packets to the lower (16 to 31).
resets the Split bits to 'O1, and reduces the Age bits.
Figure i l : An Example of a 4x4 Starburst Chip Switching
2.4 Sfarburst CSF
A Shrburst ceIl switch fabric was developed at the University of Toronto in 1994 161. In general,
multiple Starburst chips c m be cascaded to improve performance of the CSF (Figure 12).
However, the basic switch design uses two Slarburst chips in senes to improve the performance
of the Starburst chips. As it was mentioned in the previous section, Starburst chip does not
cuntain any intemal buffers. As a result, it requires some extemal buffenng to reduce cell loss
probability. Cell loss may occur if, in a Sbrburst Time Slot (Tirne between two consecutive
EOPs), two or more packets are destheci for the same output port of the Sbrburst switch. The
architecture shown below reduces this probabil@ by delaying these packets by at least 2
Starburst Time Slots (SBTS). The amount of delay is bas& on the number of packets with the
same Destination Bits that arrive to the Starburst chips in each SB-TS.
Figure 12: A Multiatage Starburst Switch
1 I
16 16 16 16 1 1 1 I f
l6 FIFO - ; FIFO * I
r 1
The FIFOs are used to provide just enough delay for each set of 16 packets, in a SB-TS, so that
the packets in consecutive SB-TSs would not be interfere with each other and data is not
CO mr pted .
Starbutst m~
The Stahurst CSF nins at bit rate of 155.52 Mbps. It consists of four Starburst Witch Boards
(SB-SB) that run in parallel (Le. each board nins at 38.88 Mbps). And each SB-SB consists of
two 2-stage Starburst switches similar to the one shown in Figure 12. As a result, each Starburst
switch runs at 19.44 MHz dock frequency. Two-phase non-overlapping clocks are used on each
S&SB to synchronize various components of Starburst CSFs.
1 1 1 1 1 I 1 1 t S t a ~ u n t
2 : I m e .
smbum 2 : I chip Chip I
1 1 4 : 1 1 1 1 1 1 1
l 1 I
l
1 1
16 t6 16 16
1
I I ,---- --------- port 16 Stahurst 1 ' 1 :
CSFO
--------- i 8
Port 16 Starburst
CSF1
0 8 0 i :--4 Port 16
Starûurst : @ . csn
Figure 13: Starburst and UO Module Connections
ATM cells are processed in byte format, Le. the senal input to the input module is transformeci into
an &bit line. This results in eight parallel53-bit long packets (Figure 14).
Figure 'I4: Serial to Parallel Conversior. of ATM Cells
16 15 8 7 O
The input module adds the sarne SBH to al1 these packets (Figure 15). Each of these Stahurst
packets will be routed separately and in the same SB-TS, using one of the eight Startiurst
switches. At the output port of the Starburst CSF, the SBHs are removed and the &bit-wide ATM
cell is transformeci into a serial bit stream (Figure 16).
GFC VCI
Figure 15: Starburst Data Stream
416 O
16 15 8 7 O
= 9 . -) Y-] . . . 1 VCI VPI VPI GFC
423 7
VPI
Figure 16: Parallel to Serial Conversion of ATM Cells
VPI
2.4.1 Sbrburst CSF Requirements
As it was pointed out in the previous chapter, the input modules to the Starburst CSF are required
to rnake some modifications to the ATM cells to generate Starburst packets. These requirements
are as follows:
The Input modules should provide a SBH for al1 the packets that enter the Starburst
CSF. This header is used to route the packets to the correct output port on the
Starburst CSF.
The packets generated by the rnodu1es should be synchronized with the control
sequence (EOP bit) that is used for routing the Starburst packets, Le. the Starburst
packets should be of fixed length (ô4 bits) and the Dummy Bit of each packet should
be synchron~ed with the hign-EOP of the control sequence (Figure 9).
The input modules must provide buffenng to reduce cell Ioss probability.
3. I l 0 Module
3.1 Introduction
As it was discussed in earlier chapters, any ATM switch would require an input module and an
output module to provide a network interface for the switch as well as other functions. Due to the
fact that most connedons to the network are full duplex connections, most switches, adapter, and
other products have placed the input and output modules on the physical connection for the same
port As a result, we will refer to IM and OM as il0 Module (IOM) in mis document The IOM
design for the Starburst ATM switch will perform the following functions, based on the ATM
network standards:
Parailel to seriai conversion of transmit data.
Serial to parallel conversion of receive data.
lmplementation of TC and PMD fundons for 155.52 Mbps SON- over Category 5
U nshielded Twisted Pair (UTP-5)-
Provides cell insertion/extraction for type F4lF5 OAM cells.
Provides an expandable look up table for 1024 VPlNCl connections.
VPI and VCI mask capabil'rty for each table entry. This enables W N C routing.
Provides rnulticasting capability by allowing the incorning VPlNCl connection to be
mapped to more than one outgoing VPINCI.
Provides CLP and congestion detection, indication and rernoval for each look up
table entry.
Provides a DMA Controller to transfer data to and from the host without system
intervention ove rhead.
InserWrernoves routing tags for the Starburst CSF headers.
Inserts/removes inactive Starburst packets.
Pravides buffering f6r a maximum of three ATM cells in receive and transmit
dirm-ons.
3.2 Design Overview
Figure 17 provides an overview of the IOM design. As can be seen, the IOM consists of a UTP-5
connectorltransceiver, set of ATM Transceiverç (XVRs), Network Termination Controller (NTC),
Address Translation Contraller (ATC). and the Starburst Adapter (SBA) '. The functions of each
block of the IOM is discussed in the later sections of this chapter.
System Controüer Interface Module (SCW
C -
Adapter Smburst
Figure 17: UO Module for the Starburst SwÏtch
The ATM ûansceivers, NTC, and ATC are products rnanufactured by Fujitsu Inc.
30
The interfaces between different wrnponents of the IOM are defined as follows:
XVR-XVR Interface: Dïfkrential receive and transmit data and data signal detection indicators
connect the high speed line transceivers and the Rxrrx ATM transceivers.
Figure 18: XVR-XVR Interface
XVR-NTC Interface: TTL level8-bit receive and transmit data, M x data clocks, data ready
signals define the interface between the M x ATM transceivers and the NTC.
Controller TRDY
b
RLOS b
Figure 19: XVR4TC Interface
Network Temination
NTGATC Interface: An Mit data bus, Data Ready (NTC-DAWATC-DAV), and Ready for
Data (WC-RFDIATC-RFD) handshaking signals define the interface between the NTC and
ATC. These signals are used to provide ATC with the incoming ATM cefl headers and
transfer the rnapped VPINCI values and routing tags to NTC.
ATC-DAV ATC RFD
Address Network Translation Termination Conboller Controller
M C DAV
Figure 20: NTC-ATC Interface
r, NTGSBA Interface: This is a UTOPlA Level 1 interface between the NTC and the Starburst
Adapter. The interface is defined by Bbit M x data buses. W x Start of Cell (SOC)
indicators, Rx FIFO empty, Tx FIFO Full, readfwrite, and M x docks. Tagged ATM cells
are transferred through this interface.
Figure 21 : NTC-SBA Interface
SCIM-IOM Interface: A l&bit data bus, 24-bit address bus, read, wnte, chip select, and other
handshaking and control signals provide access to the IOM registen and look up table. The
NTC DMA controller uses this interface to transfer network statisb'cs and other information to
and from the host The details of these operations are discussed in later sections.
Figure 22: SClM-IOM Interface
3.3 Operation
This &on describes the operation of the I l0 module based on the architecture that was
introduced in Section 3.2. The operation of the IOM can be categorized into two independent sets
of functions. The first set of functions deals with transfemng user data cetls through the Starburst
CSF and al! its requirernerits. The second set of functions wmplete the operation of the ATM
switch by providing accesç to ATC look up table, NTC registers, and System Controller
information on the host tfirough the SCIM-IOM interface.
Chapter 4 will provide detailed discussion on the System Controller Interface fun&-ons as well as
the operational fundons that effect the look up table, register a-, and DMA transfers. In this
section, the focus will be on providing a good understanding of the user data cell ûansfer through
the Starburst celt switch fabrÏc.
The high speed line transceive? (Figure 17) implernents the PMD functional requirements such
as signal encodingldecoding, adaptive equalization, DC restoration, filtering, and isolation, It,
also, provides differential PECL level signals to be interfaced to the ATM PHY layer transceivers
r-123. The line transceivers in combination with the PHY transceivers satisfy the ATM Physical
Media Dependent sub-layer standards.
The ATM Rx transceiver, shown in Figure 17, uses an intemal PLL circuit to extract and
synchronize to the incorning high speed senal data clock and provide the NTC with a byte-wide
data bus. While the ATM Tx transceiver uses a similar PLL circuit to generate a high frequency
clock signal from a reference clock provided with the byte-wide transmit data bus at the XVR-NTC
interface. The Tx transceiver multiplexes the &bit bus into a high speed serial data line.
3.3.2 Network Temination Controller
This section describes the data flow and the basic operation of the NTC in the receive and
transmit directions.
Receive Operation
Parallel data amving at the XVR-NTC interface is sarnpled by the SONET receive framer. The
receive framer circuit detects the SONm frame and synchronizes to the frame. The OAM data
enclosed in the SONET frame is extracted and stored in the NTC registers. The ATM cells in the
frame payload are transferred to the ceIl receiver block The cell receiver block perforrns ceIl
delineation, HEC checking and single bit error correction, cell type recognition, idle cell removal,
and OAM ceIl extraction/insertion. The ceIl rece~er block, also, requests a look up table search
through ATC. The new heâders and #e routing tags for the incoming cells are added to the ce11
payload and the cells are m e n into receive FIFO at the NTCSBA interface.
The look up table response time is l e s than a ceIl arriva1 tirne- This will prevent any loss of data
due to look up table search. The 2-byte routing tags provided by the ATC contain appropriate
values that are used by the Starburst Adapter to generate Starburst header for each cell. The first
11 bits of the routing tags are used in aie LSB to MSB order to generate the Starburst header and
the remaining 5 bits are discarded.
Transmit Ope ration
The amving data at the NTC-SBA interface is sampled from the transmit FlFO and delivered to
the cell transmitier block. The cell transmitter block provides a constant stream of ATM cells to
the SONET transmit framer. The cell transrnitter uses three sources to provide this constant
stream of cells. The fist source is the outgoing cells from the NTC-SBA interface. The second
source is the OAM cells provided by the DMA for insertion in the cell stream. If neitber of these
two sources have data available, ldle or unassigned celis will be sent to the transmit framer. The
cell transmitter block calculates and inserts HEC for each outgoing cell before it is transferred to
the transmit SONET frarner.
The transmit frarner packs the amving ATM cells in the payload of the SONET frames, adds the
framing information to the SONET frame, includes the SONET OAM information. and delivers the
frames in byte format to the transceiver at the XVR-NTC interface. The OAM information for the
This product is rnanufactured by Pulse Engineering Inc.
SONET ftames can be generated intemally based on the information provided with the incoming
frames.
3.3.3 Address Tmnslation Controller
This module provides VPlNCl address translation and can suppiy routing tags based on how it is
configureci. The ATC is used in combination with the Network Termination Controller to
implement VPINCl mapping and replacement. The NTC provides ATC with the first four bytes of
the ATM cell header (Figure 2) in a burst of four bytes via the MC-ATC interface. This transfer of
data takes place by using the handshaking signais as show in Figure 23.
Figure 23: NTC to ATC Data Transfer
Upon receiving that ATM cell header, ATC will start a search in the look up table based on the
unmasked VPlNCl bits. The GFC field is always rnasked in the UNI mode. If a match is
detected, ATC asserts the ATC-DAV signal and waits for the assertion of the NTC-RFD signal
from NTC (Figure 24). On assertion of the ready signal from NTC, ATC starts transferring the
new ATM cell header and the associated two bytes of b g .
The retum of the first rnatched header does not terminate the look up table search. As a result, if
there are more than one entries that have the same input header, the ATC will detect al1 the
entries and retum ail the mapped VPlNCl values and the corresponding routing tags following aie
first data transfer from ATC to NTC. The NTC module will not request a new search until the
ATC-RFD is asserted. As long as the ATC-RFD is not asserted the current cell payload is held
by NTC. This method provides a simple way of implementing rnulticasting andfor broadcasting,
Updating ATC look up tables at any given time will not disrupt the search. It is possible to
cascade ATCs to increase the size of the look up table to multiples of 1024 entnes.
Figure 24: ATC to NTC Data Transfer
As can be seen from Figure 24, the rouüng tag provided by the ATC contains 16 bits while the
Starburst packet header requires only 11 bits. The S8A design will discard the extra bits, as
explained in the next section.
3.3.4 Starburst Adapter
This section describes the basic operation of the Starburst Adapter in the receive and transmit
directions. The receive operation of the Starburst Adapter is designed to insert a Starburst packet
header, based on the routing tags provided by the ATC module, for each incoming ATM ceIl. The
Starburst header replaces the routing tags provided by the ATC. The receive operation inserts
inactive Starburst packet in the Starburst packet stream sent to the CSF, when necessary,
37
The transmit operation is designed to replace the Starûurst header of the cells k ing received
fmm the CSF with the appropriate 2-byte routing tags. The ATM cells with the rouüng tags are
written to the NTC FlFO via the NTCSBA interface. The transmit operation discards the inactive
Starburst packets received from the CSF module.
SBA Module
NTC Starburst
CSF
Figure 25: Starburst Adapter Module Architecture
As it can be seen from Figure 25, the SBA module mntains a receive and a transmit FIFO. These
FlFOs are mainly used to synchronize operation of the SBA module and the NTC. However, the
receive FlFO is also used to ensure that a complete cell is available inside the FlFO before
transmission of a valid Starburst packet starts. This is very similar to ceIl rate decoupling in ATM
networks, The receive operation state machine will insert inactive Sbrburst packet as long as
there is no wmplete cell available in the -ive FIFO.
The SBA was implemented on an XC4013EPG223-1 device, Table 2, provides the resource
utilkation generated by Xilinx Design Manager and Timing Analyzer. The SBA design was
esb'rnated to operate at 32.2 MHz with the worst critica 1 path delay of 3f. 1 ns.
Il0 pins 44 Y
FG Function Generators 80 H Fundion Generators 32
F i i ~ F l o ~ s 16
Table 2: FPGA Resource Utilization for SBA Design
Figure 26: NTCSBA Interface Controller Receive State Diagram
3.3.4.1 NTC-SBA Interface Controller
The NTC-SBA interface conîmller module essentially transfers incorning and outgoing NTC
packets6 between the Starburst Adapter M x FlFOs and NTC M x FlFOs respectively. In the
An NTC packet is defined as ATM cells plus the routing tags.
39
receive direction, the NTC-SBA interface controller reads the data from the NTC Rx FIFO and
writes it into the SBA Rx FlFO if the SBA FIFO is not full and the NTC FlFO is not empty. The
state diagram for the receïve operation of this controller is show in Figure 26.
In the transmit direction, the NTC-SBA interface controller reads data from the SBA Tx FlFO and
writes it into the NTC Tx FlFO if the S5A FIFO is not empty and the NTC FlFO is not full. The
state diagram for the transmit operation is shown in Figure 27.
Figure 27: NTC-SBA Interface Controller Transmit State Diagram
3.3.4.2 SBA Receive Operaüon
The receive operation of the Starburst adapter is best describeci by the state diagram provided in
Figure 28. The state diagram provides only the transition conditions and the variable
assignments at the transition. However, an explanation of the operation of the circuit while it
remains in each state follows:
Hunt The operation of the receive SBA starts in this state and returns to this state with reset
The arriva1 of Start of Packet (SOP) control signal causes a transition to either Send Valid
Header or Send ldle Header state. Start of Cell (SOC) signal indicates that the curent byte
of the data inside the SBA Rx FIFO is the first byte of the NTC packet The CELLRDY signal
indicates that there is at least one WC packet (55 bytes) available inside the SBA Rx FIFO.
If the CELLRDY signal is not asserted, the state machine continues transrnitting inactive
Starburst packets, irrespective of SBA Rx FIFO not k ing empty-
, Send ldle ; t ; Send Vaiid
I i header ' header
Figure 28: Starbutst Adapter Transmit State Diagram
. Send ldle Header: In this state, a Starbunt inactive7 header (Figure 8) is being bansmitted to
the Starburst CSF. The SBA receive circuit also generates the End of Packet (EOP) control
signal for the Starburçt CSF and transmits this bit concurrent with the first bit of the Starburst
header. While in this state, the bit counter is increased at each dock cycle. The byte counter
also increases every eig ht ctock cycles.
ldle Payload: The payload of an inactive Starburst packet is being transrnitted to the CSF.
The ldle payload (53 bits) is assigned to logic '0'. The value of the byte counter is increased
at every clock cycle while the bit counter will hold a constant value.
61 Bytes with value '(Y
i l
Figure 29: Idle Starburst Packet
SendValidHeader:Inthisstate,~gsofthevalidNTCpacketsarereadfromtheSBARx
FIFO and each bit of the tags are used as a byte for the outgoing Starburst packet Bits 3-7
of the second tag are not used, hence they are discarded (Figure 30). While in this state. the
bit wunter is increased at each dock cycie, The byte counter also increases every eight
dock cycles.
Figure 30: Valid S&rburst Packet Generation
Valid Payload: The payload of an active Starûurst packet is the incorning ATM ceII. This ceIl
is read from the SBA Rx FIFO and appended to the Stahurst packet header genemted based
' The active bit is set to logic '1 ' and the remaining bits are set to '0'.
42
on the routing tag provided by the NTC packet The vaIue of the byte counter is increased at
every dock cyde while the bit munter will hold a constant value.
3.3.4.3 SBA Transmit Operation
The transmit operation of the Starburst adapter is best described by the state diagram provided in
Figure 31. The state diagram provides only the transition condiions and the variable
assignments at the transition. However, an explanation of the operation of the circuit while it
remains in each state follows:
Hunt The operation of the transmit SBA starts in this state and retums to this state with
reset The arriva1 of the EOP control signal from the CSF causes a transition to the Check
Headerstate. The EOP signal indicates that the incoming data, concurrent with the EOP
signal, is the first bit of the incoming Starburst packet from the CSF.
f- /- r Hunt 4 7 (üyte-m53 Bit-ent=i)
(EO-13 (Byle-ait=O = ((Bi-cnt=i! aa T*DIW1') II (eir-~m7 aa ~ ~ r w 1 9 ) ) -
(~i-cnt c O i --ait a O) t ~ ( B ~ - a i t - - l & B ~ a i t = 2 & & T h W I ~ ~
(Bit-- cf 7 a @?te-Qit = 2)
i Check Pay load
I
, Dummy Header
f
Pa yload
Figure 37: Starburst Adapter Transmit State Diagram
Check Header In this state, the transmit SBA checks the active bit of the incorning Starburst
packet to ensure that the packet is active before transfem'ng the packet to the NTC. If the
Active bit is set, the inmming invalid packet is discarded and the transmit SBA goes to the
Hunf state. However, if the incoming packet is a valid packet, the transmit SBA generates the
NTC routing tags from the Starburst packet header and trançfers an NTC packet to the NTC
module (Figure 32). While in this state, the bit counter is increased every clock cycle and the
byte counter is increased every eight cycles.
Valid Payloact The payload of an active Starburst packet is the outgoing ATM cell. This cell
is appended to the routing tags, generated based on the incoming Starburst header from the
CSF, and written to the SBA Tx FIFO. The value of the byte counter is increased at every
dock cycle while the bit counter will hold a constant value,
Figure 32: M C packet Generation
Dummy Payload: The transmit SBA enters this state only if the SBA Tx FIFO is full and it is
not possible to write the correct data into aie FIFO. To prevent generating short NTC packets
( les than 55 bytes) this state will write dummy bytes to the Tx FIFO, when there is space
available. And retums to Hunf state when a complete NTC packet is wntten to the SBA Tx
FIFO. This will result in synchronous operation of the NTC and SBA with respect to ceII
timing. However, due to FlFO ovemn valid ATM cells will be lost The value of the byte
counter is increased at every clock cycle if the SBA Tx FlFO is not full, while the bit counter
will hold a constant value.
4. System Control Interface
4.1 Introduction
The System Control Interface Module (SCIM) is the last module that is required to enable the
implementation of the Starburst ATM switch. This module is responsible for initialkation,
registerdook up table updates, system management, and network interface. The SCIM design is
based on the 10M requirements and using an AMCC PCI bus controller (13, 141. It is possible to
design the SCIM interface using a microprocesso~ or other bus types. However, the use of the
PCI bus for this application was based on the fact that PCI bus c m operate at 33 MHz and higher.
The a b i l i to transfer networking and controt data over the system bus at hig h speeds (more than
the switch dock frequency of 19.44 MHz) is an advantage and a system design requirement It is
essential for any system to be able to transfer control information at the least at the same speed
as the user data, atthough the system control software may not need to access the registers and
networking information very of€en-
The SClM was not designed using direct connection to microprocessors. It is more feasible to
upgrade the externat PC (or any other system with 33 MHz, 32-bit PCI bus) than upgrade a
rnicroprocessor. A rnicroprocessor based design would require extemal mernones as the sue of
the design increases. Tbe future expansion in the switch size, look up table size, and functions
that will be supported by the CAC and SM blocks witl define the system hardware requirements.
This expandability requirement is more easity manageabte based on the industry trend if an
externat PCI-based PC is used. As we know, more powerful and cost effective PCs are and will
be available. Another advantage of the PCI based SCIM design is that it is possible to upgrade, if
Network Termination Conboller data book [il] explains various micmprocwor interfaces that cm directly connect to the NTC.
required, the 33 MHz, 32-bit PCI bus to 66 MHz with 32 or 64 bit data bus. It is, also, possible to
use extended addressing mode of the PCI bus to expand the switch size. The AMCC PCI
wntroller is used due to aie fact that at the time of SCIM design this was the most cost effective
solution availa ble.
This chapter will provide a detailed discussion of the Systern Controller Interface Module design,
Section 4-2 presents an overview of the SCIM design. A general introduction to AMCC PCI
controller is provided in Section 4.3, Memory rnap and ttie implemented software funcüons are
presented in Section 4.4, while the hardware design of the SCIM is discussed in Section 4.5
4.2 Design Overview
The System Contraller Interface Module consists of hardware and software components The
SCIM hardware architecture is show in Figure 33. The hardware implernentation design provides
the following through the target controller circuit
Read and write access to the NTC controüstatus registers,
Write access to the ATC look up table,
Read access to the ATC status register.
However, the master and intempt controller circuit can provide the hllowing functions:
DMA write access to the host memory for transfer of network statistics and
receive/transrnit extracted cells from the NTC,
DMA read access to the host rnemory for transfer of the NTC DMA Iink descriptors
and receiveftransmit cells to be inserted in the outgoing cell stream by the NTC,
Trançfer of NTC Intempts to the software intempt handler.
The software portion of the SCIM is required to integrate the network and system management
functions with the hardware functions to provide a seamless operation for the user. The following
are the functions the SClM software provides:
PCI controller configuration test,
Base address dewon from the PCI contmller configuration register,
Network Temination Controller DMA link descriptor initialization in the host,
Init iaf i ion of the ATC look up table,
Initiaiiiation of the NTC control register,
InitiaSiahion of the Intenupt handler routine,
Provide start comrrtand for the operation of the Starburst switch,
Provide a user interface to enable monitoring the switch operation.
IOM
Master & Intempt Controller
AMCC ?CI
Controller
Figure 33: SClM Hardware Structure
4.3 PCI Bus ControIIer
The AMCC PCI controller consists of the PCI bus and the peripheral bus interfaces. The PCI bus
interface performs PCI data transfer funchions between the application and the host software
based on the PCJ standards and specifications. lssuing commands on the PCI bus and hnsfer
of dab through the PCI bus is the function of the operating systern and neither SClM hardware
nor software is involved in exact implernentation of the PCI functions.
The peripheral bus interface is the portion that is of interest to this project. This interface provides
a PCI Master and a PCI Target interface to the peripheral device. The PCI master operationsg
(read and write) are performed via an interface called Add-on FI FOI0 controller. PCI Master read
. operation is performed using the following steps:
The address of the memory location that is to be accessed is written to the bus
master read address register in the PCI controller.
The size of the burst is written in the bus master read counter register.
The bus master read enable (AMREM') signal is asserted.
The data will be available when the FlFO empty signal (RDEMPTY) is deasserted.
PCI Master Write operation is perfomied in a similar manner, as follows:
The data is written to the PCI mntroller FIFO.
The addres of the rnemory location that is to be accessed is written to the bus
master write register of the PCI controller.
The burst size of the wnte operation is written to the bus master write counter
reg ister.
PCI Master and Target operations can not be performed concunently, Le. Me peripheral deviœ can be master if and only if it is not a target at any given time. 'O A tenn used by AMCC to define the PCI Master intehce. " Signal names that are mentioned here refer to the signal name in Figure 33.
The bus master write enable signal ( A M E N ) is asserted to complete the
transaction.
The PCI Controller Target interface is generally used to read statusldata registers and update the
control registers of the application device, The PCI target operations of the AMCC PCI controller
is performed through the Pass- th~ '~ controller. The PCI target read operation is performed as
follows:
r The target operation active signal (PTATM 'j) is asserted with read signal indication
(PM = '03.
The address of the memory address on the peripheral can be read from the Pas-thnr
address register by asserüng the read address signal (PTADR#). - When the data is ready to be transferred to the PCI controller, aie data is wrÏtten to
the Pass-thru data register and the data ready signal is asserted (P7RDY#).
The PCI target write operation is perfomied in a similar manner, as follows: - The target operation active signal (PTATM) is asserted with write signal indication
( P M = '7'). - The address of the memory address on the peripheral can be read from the Pas-thru
address register by asserüng the read address signal (PTADM). - When the target is ready to transfer the data from the PCI controller, the data is read
from the Pass-thru data register and written to the appropriate peripheral register and
the data ready signal is asserted (PTRDY#).
The AMCC PCI controller provides a set of incoming and outgoing mailbox registers. These
registers can be used to transfer wmmand and data to the peripheral device or the host These
'* A tenn used by AMCC to define the PCI Target interface. '' The active low signals are indicated using the '# ' in this document
register are used in the SClM design to transfer intermpts generated by the VU module to the host
intempt handler. The intemrpt request transfer is performed by writing to an outgoing rnailbo~'~.
The PCI controller generates an intempt to the host to indicate a read operation from the mailbox
is required. The operation is completed when the host reads the mailbox This PCI host read will
generate an intempt to the peripheral interface to indicate the cornpletion of the transaction.
4.4 Memory Map/Software Functions
Every PCI bus deviœ contains a set of configuration registers that can be read and configured by
the system BlOS at power up. These registers provide various information to the system to
ensure the plug and play capabilzties of the PCI bus devices. Sorne of the information that the
PCI configuration registers contain, and is of interest to this document, are as follows:
Mernory and If0 base address registers,
PCI cornmand and Status registers,
Vendor and Device Identification.
The Vendor and Device Identification registers are used to uniquely identify the PCI device
manufacturers and their products, The PCI command and Status registers are indicative of what
PCI functions the device is capable of. The most important register for implementation of the
memory mapping and soîtware functions is the Memory and 110 base address registers. The
Memory base address register is read by aie system BIOS at the power up. The default value of
this register indicates the arnount memory space that is required by the PCI device. The system
BlOS writes aie starting address of the required memory space back to this register. The default
mernory required by the AMCC PCI controller is 32 K bytes. This default memory allocation is
large enough to handle the present design of the Starburst switch. However, it is possible to
AMCC PCI controller defines incomingloutgoing maifbox from Me point of view of the peripheral device.
change the defauit values of the AMCC PCI controller via a serial PPROM provided with the
developers kit, as rnaybe required in the future.
The mernory mapping for this implementation of the SClM is based on the number of registers in
the NTC and ATC devices. Each NTC component contains 64 control and 64 status, word size'?
registers- Due to the ske of the Starburst switch (16 110 ports) the totat number of required
address spaces for the NTC registerç are 8 K bytesq6. As a result, the assigned mernory space is
divided into 4 blocks of 8 K bytes. Therefore, the SCIM hardware will require only 2 bits to
decode which memory block is k i n g accessed. Table 3 provides the necessary memory
rnapping information. The 17 higher order address bits represent a constant base address that is
assigned by the BlOS at the power up.
Table 3: SClM Memory Map
I
C
To reduce the complexity of the SCIM hardware design the lower two bits of al1 addresses are
ignored and should ahivays be assigned to logic '0'. This will, aiso, prevent any conflict between
l5 16 bit registers; Le. bit O of the address is ignored.
51
2AOOW 2COOW 2EOO\H
5 6 7
OAOOW OC00ü-i OEOOW
memory rnap addressing and PCI bus specificaüon for addreçs cycles? The A 8 4 2 address bits
of are used to refer to the appropriate registers inside each NTC component The remaining h o
mernory rnap blocks are not used in the present design of the SCIM.
31 15 13 9 2 O
Memory Base Address
Memory block decoding (A1 3-A1 4) " 0 0 => NTC access "01 " => ATC access "1 0 & "1 1" => Not used
IOM port decoding (ASAI 2) => 1 6 ports
NTC => Internai register addresses ATC => OOW (fuhire use)
(Al-AO) are not used t Figure 34: Starburst Switch Address Decoding Structure
The sofhAlare written for this design of the SCIM does not provide full functionality with respect to
Call Admission Control and System Management functions. The software for mis thesis design
only provides basic fundons required to communicate with the IOM and transfer the required
data to and from the IOM components. The CAC, SM, and interrupt service routines will have to
be written based on the device driver software that is provided by this thesis. However, it is
recommended that the modifications to the device driver software be irnplemented as neceççary.
This implementation assumes Me registers are 32 bits wide to simplify the design. l7 PCI requires the addres provided on the bus during the address cycle have the Iower two bits set to logic 'O', i.e. long word addressing must be used.
The basic operation of the SCIM device driver starts with performing a ?CI configuration test on
the PCI controller device. The Memory base address register is obtained from the PCI
configuration register. The mernory base address is appended to the memory rnapped addresses
to access the required registers in the Starburst switch (Figure 34). The Starburst switch driver
will setup the chained link descriptors for the NTC DMA controllers [If). The ATC look up table
and NTC controt registers initialkation is the next task that the software driver completes. The
intempt handler routine is started and the user interface program is invoked to provide the
system manager with the necessary information,
4.5 SCIM Hardware Design
The AMCC Matchmaker kit provides a set of daughter cards with the PCI controller card. These
daughter cards a n be used to implement the SCIM hardware on an FPGA or PLD device. The
SCIM hardware design implements target readhrite, master readlwrite, and internrpt request
transfer to the PCI controller. The description of aie above funcüons and the state diagrams are
provided in the following sections18. The state diagrams for the SCIM functions are presented
individually to provide a better understanding of the operation of the circuit However. the actual
implementation will need to combine these state diagrams to generate only one state machine
with &firent branches. Due to the fact that the PCI Target functions are not perfonned as often
as the Master readiwrite operations, the Target functions are given priority over Master
operations. It is possible to design a more complex arbiter to provide a different type of priority
scheme as required, in the future.
4.5.1 System Controller Master Read
The SClM master read (SCMR) function is used to implement the DMA controller read operation
of the NTC cornponents of the IOM ports. The SCIM-IOM interface signals are similar to the lntel
The signals names used in Figures 35-39 are the same as the signals in Figure 33.
53
16 bit microprocessor. The M e diagram in Figure 35 provides oniy aie transition conditions and
the variable assignments at the transition. An explanation of the operation of the circuit is given
beiow:
f ldle 4.
Figure 35: SCIM Master Read State Diagram
Idle: The operation of the SCMR function starts in this state and retums to this state with
reset The assertion of Pas-thru inactive (PTATN#='I ') and bus request (HOU)) frorn the
DMA controlier signals causes a transition to Wait Read state. At the transition, the hold
acknowledge ( H U A ) is asserted and SCIM target functions (TAKEN)'' are disabled.
Wait Read: This wait state is introduced to ensure that the M C DMA controller issues a read
wrnmand and provides aie address for the read command. The assertion of the read
command causes a transition to the Waif Data state while SCMR assigns appropriate values
to the PCI controller signais.
Wait Da&: The SCMR remains in this state until it receives the requested data from the PCt
controller via the Add-on FIFO interface of the AMCC chip set The deassertion of read FIFO
empty signal indicates that the data is available. The data is read from the PCI controller
FlFO More the SClM goes to the Send Data &te.
Send Data: The DMA is notified of the data availability by asserting the READY# signal. The
SClM master read state machine is capable of providing back to back reads. If the target
active signal is not asserted by the PCI controller, the SClM master read operation goes to
the Waif Read state to start another read cycle. However. if the PCI controller asserts the
PTATM signal, the SClM Target Controller is activated, In this case, if the DMA bus request
is still active. the bus clear (BCLR#) signal is asserted. The bus clear signal causes the NTC
DMA controller to stop transmission and wait for hold acknowledge before continuing to
transfer the remaining data.
4.5.2 System Conboller Master Write
The SCIM master write (SCMW) function is used to implement the DMA controller write operation
of the NTC cornponents of the IOM ports. The state diagram in Figure 36 provides only the
transition conditions and the variable assignments at the transition. An explanation of the
operation of the circuit is given below:
Idfe: The operation of the SCMW function starts in this state and returns to this state with
reset The assertion of Pass-thru inactive (PTATWJ1 ') and bus request (HOLD) from the
DMA controller signals causes a transition to Waif Wnte state. At the transition, the hold
acknowledge (HLDA) is asserted and SClM target functions (TAR-EN) are disabled.
Wait Write: This wait state is introduçed to ensure that the NTC DMA controller issues a wrïte
comrnand. The assertion of the write command causes a transition to the Lafch Data state
while assigning appropnate values to the PCI controller signals.
'9 This is an intemal signal that is used to enable or disable SCIM target operations.
55
Latch Data: The SCMW remains in this state b r only one dock cycle. The data is latched in
and held to ensure the data value does not change by the DMA controller before it is written
to the PCI controller FIFO.
Figure 36: SClM Master Write State Diagram
PCI Wnte: in this state, the SClM issues write FIFO cornrnand to the PCI controller to write
saved data to the PCI controller FIFO. The master write state machine asserts the data
ready signal to alert the DMA controller of completion of the transaction before moving to the
Send Data state.
Send Data: The S C W state machine is capable of providing back to back wrÏte operations.
If the target active signal is not asserted by the PCI controller, the master write state machine
goes to the Wait Wnte state to start another write cycle. However, if the PCI controller
asserts the PTATM signal, the SClM Target Controller is activateci. in this case, if the D M .
bus request is still active, the bus clear (BCLR#) signal is asserted. The bus clear signal
causes the NTC DMA controller to stop transmission and wait for hoId acknowledge before
continuing to transfer the remaining data.
4.5.3 System ConfmIIer Target Read
The SClM target fundons are different from the master operations in their neeâ to decode the
memory address for the requested access. The SClM Target Read (SCTR) fundion performs the
read function for the Starburst switch driver. The state diagram in Figure 37 provides oniy the
transition conditions and the variable assignments at the transition. An explanation of the
operation of the circuit is given below
ldle: The operation of the SCTR function startç in this state and retums to this state with
reset The assertion of Pas-thni active (PTATM) along with read request (PTWR='O') and
target enable will result in a transition to iatch Address state. At the transition, an address
read request (PTADR#) is issued to the PCI controller Pass-thni interface.
Latch Addmss: In this state, SCTR circuit decodes the address provided by the Pass-th ru
interface based on the SClM memory map (Table 3). The SCTR state machine can move to
Read NTC or Read ATC states depending on the address provided. ln either case, the Pass-
thru address read request is deasserted and the ASA2 address bits are latched and held.
Read NTC: The chip sel& and NTC read command is asserted while the saved address is
assigned to the IOM address lines,
Waif NTC: The SCTR sbte machine will remain in this state until it recenles the confirmation
of data availability (RDYOUT='l? at the output of the NTC module. The assertion of the
RDYOUT signal will result in the transition to the Write PCI state. The SCTR issues a write
wrnmand to the PCI controller while asserb'ng the data ready signal (PTRDY#) for the Pass-
thm interface.
Read AT%: The chip select and ATC read cornmand is asserted while the saved address is
assigned to the IOM address lines. The ATC modules do not require any address lines for
The chip select signals for both ATC and NTC modules are provided based on the combination of CS#, ICS[l:O], and BS[2:0] signals. This is due to the fact that there are 16 ATC and 16 NTC modules that needs to be accessed. The BS[2:O] signals distinguish bebeen eight IOM boards, while the ICS[l:O] signals select which of the four modules (2 ATC and 2 NTC) on each board is to be accesçed.
the read or write operation. This is due to the fact that the ATC modules are designed such
that it provides oniy one readable register.
(NTCADR-1') * (TEMP-A C= P C I O ( 8 ~ 8 PTADRAI '1')
Address
(MC-RD#- '0. & sw_A[s:a] - 7EMP-A 8 iCSI1:q - t2\H or Ni) & =Fol = (o-T) a cs#cr]'& 1
f
Wait NTC
* f Y
\ Write d
PCI
Figure 37:SCIM Target Read State Diagram
Wait ATC: The SCTR state machine will remain in this state for only one cycle. Based on the
timing specifications of the ATC, the data is available within one dock cycle. The transition to
the Write PCI state is cornpleted by isçuing a write command to the PCI controller while
asserting the data ready signal (PTRDY#) for the Pass-ttiru interface.
Write PCI: This is a wait state to ensure that the correct data is transferred to the PCI
controller. The SCTR will move to the idle state after this state al1 the signals will resurne
their default values.
58
4.5.4 System ContmIIer Target Write
The SClM Target Wnte (SCTW) function is difkrent for ATC and NTC modules due to the timing
requirements of each module. However, the SCTW perfom the write function for the SClM
software driver. The &te diagram for NTC and ATC target write operations are provided in
Figure 38 and Figure 39, respectively. These state diagrarns only provide the transition
conditions and the variable assignments at the transition. An explanation of the operation of the
NTC target write state machine is provided below
Idle: The operation of the SCTW function for the NTC module starts in this state and returns
to this *te with reset The assertion of Pas-thru active ( P T A W along with write request
( P M = ' ? ') and target enable will result in a transition to Latch Addms state. At the
transition, an address read request (PTADR#) is issued to the PCI controller Pass-thni
interface.
iatch Addfess: In this state, SCTW circuit decodes the address provided by the Pass-thru
interface based on the SClM rnemory map (Table 3). The SCTW remains in this state for
only one dock cycle and moves to the 1-Cycle Wait state, while the A&A2 address bits are
latched and held, the PCI read signal is asserted and the Pasthni address read request is
deasserted.
?-Cycle Wait= This wait cycle provides sufficient time to ensure that the PCI controller data is
available. The SCTW issues a write command to the NTC module by providing the chip
select, write enable, valid data and address.
Hold Daîa: The SCTW circuit will remain in this &te until it receives the confirmation of
wmmand completion (RDYOUT='I') at the output of the NTC module. The assertion of the
RDYOUT signal will result in the transition to the Wrote NTC state- The SCTW deasserts the
write enable signal while asserting the write command completion flag (PTRDY#) for the
Pass-thru interface. The register address is incremented to enable back to back writes to the
NTC reciisters.
l -Cycle Wait
Figure 38: SCIM Target Write to NTC State Diagram
Wrote W C : The SCTW state machine can move to either Hold Data or ldle state depending
on the value of the PTBURST# signal. If the burst write request signal is asserted, the target
write circuit asse& the W C write enable, new address, and data, while deasserting the write
completion fiag (PTRDY#) to the Pass-#ni interface. However, if the burst wnte Rag is
disabled, the SCNV will move to the idle state and al1 the signals will hold their default values.
The SCW state machine is different for the ATC modules due to different timing requirernents
and the manner in which the wnte transactions are treated. The ATC look up table entries are
m e n without requiring extemal address lines. The ATC module requires seven consecutive
write comrnands to update one of the look up table entries, Every write command increments an
intemal counter to generate the address for the following write command into the ATC Control
Word registers? After the final wrÏte is issued, the ATC will transfer the data in al1 the Contral
Word registers to the next available look up table entry and asseris a ready flag. The SCTW state
diagram for the ATC modules are provided in Figure 39. An explanation of the operation of the
ATC target Mite state machine is provided below
ldle: The operation of the SCTW function for ATC module starls in this state and retums to
this state with reset The assertion of Pass-thru active (PTATN#) along witfi write request
(PfWR='l? and target enable will result in a transition to Lafch Address state. At the
transition, an address read request (PTADR#) is issued to the PCI controller Pass-thni
interface.
Latch Address: In this state, SCTW circuit decodes the address provided by the Pass-thru
interface based on the SClM memory map (Table 3). The SCTW remains in this state until
the data request flag (DREQ) is asserted by the ATC. Riis will cause the transition to the 3-
Cycle Wait state, white the write counter is set to zero, the PCI read signal is asserted and the
Pasç-thru address read request is deasserted.
&Cycle Wait: This wait state provides sufficient ornep to ensure that the ATC is ready for a
new cycle of seven wnte cornmands- At the transition to the Hold Data state, the SCTW
issues a write comrnand to the ATC module by providing the chip select, write enable, and
valid data. The wnte counter is also incremented.
Hold Da&: The SCTW circuit will remain in this state for only one cycle and moves to the
Wmte ATC state. The SCTW deasserts the write enable and chip select signals white
asserthg the write command completion flag (PTRDY#) to the Pass-thru interface.
" Control Word register is a terni used in the ATC data book There is approxirnately a maximum delay of 100 ns frorn the rising edge of the DREQ signal to
the actual time that the AT% is ready to accept new data. With the assumption that the PCI clock is running at 33 MHz, three clock cycles is sufficient to ensure correct operation of the modules.
Figure 39: SClM Target Write to ATC State Diagram
Wrote ATC: The target write state machine can rnove to either Hold Data or ldle state
depending on the value of the PTBURST#, and write counter. If the burst write request signal
is asserted and the nurnber of writes is less #an seven, the target write circuit asserts the
ATC write enable, chip select, and data, while deasserthg the write completion fl ag
(PTRD Y#) to the Pass-thru interface. However, if the burst write flag is disa bled or the write
counter equals seven, the SCTW will move to the idle state and al1 the signals will hold their
expected values.
5. Conclusions
Based on the fact that ATM technology is s ü H evoiving, many of the standards developed up to
this point in time are not complete. This provides a challenge in design and irnplementation of an
ATM switch that would be cornpliant with standards and initiates a platform for design and
development of products that have practical implications. The initial goals of this project were to
understand vanous important design issues on developing a complete system that can implement
ATM switctiing and move forward with completing the Starburst project that had started a few
years ago. It has since been a long joumey, studying various articles and documents,
researching component availability and their functions, discussing ideas with friends and
wlleagues, and leaming vanous aspects of systern design requirernenis.
The Starburst ATM Swiich architecture ernerged from the these efforts. The challenge in
designing the switch system lay in meeting Starburst cell switch fabnc requirements and ATM
network specifications. Availability of products that can provide ATM Physical Layer functions,
look up table and routing tags, while perforrning seamless operation with other systern
wrnponents via predefined interfaces, was a major part of decision rnaking process in how
sophisticatéd and robust the Starburst ATM switch design can be. Many different modules
manufactured by various companies were studied and the feasibility of their utilkation on reducing
the complexity and cost of the switch design were considered.
Section 5.1 provides a brief summary of the contributions. Finalîy, some suggestions for future
research and development are presented in Section 5.2.
5.1 Contributions
In Chapter 1, ATM network concepts, Physical Layer specifications. an overview of a general
ATM switch architecture including required nehnrork Connection Admission Control and System
Management functions, and the Stahurst ATM Switch structure were presented. The
architecture and functionality of the output buffered, non-blocking Starburst packet switching IC
was introduced in Chapter 2-
Chapter 3 presented a cbmplete design of the Starburst Switch I f0 Modules that included an
overview of the IOM data path, functional description of the components, and design of the
Starburst Adapter circuit In Chapter 4, the design of the Systern Control Interface Module was
discussed. All the required SCIM hardware and software functions, including PCI controller
Interface Masterrïarget operations, and the Starburçt Switch Memory Mapping were described.
The circuit design of the SBA was simulated, synthesized and routed to ensure the functionality of
the module and the correcbiess of the implementation. The SCIM software functions were tested
by transferring data to and from the PCI controller device.
5.2 Future Directions
There are several directions in which this project w n proceed. This thesis only sets the ground
work for development and implementation of an ATM switch. However, the first step is to
implement the design provided. Without any doubt, improvements can be made to enable the
Starburst switch to become a more complete solution by writing the required SM and CAC
functions and modifying the hardware design as required to becorne more efficient. The Starburst
switch was designed to be modular and this rnodularity can be an advantage in having a robust
and expandable ATM switch- One of the known disadvantages to the design is the inability of the
switch to obtain statistical data from the CSF and to use aiis information to improve the
performance of the system. This inability is due to existing design of the Starburst CSF. It may
be possible to impiement a different design for the CSF that increases the size of Starburst
header and uses the extra bits for transfemng statistical information.
The purpose of this thesis is to provide a starting point for implernentation of an ATM switch. It is
hop& that this work can generate interest and encourage other researchers to innovate and
irnplernent new ideas.
Appendix A: Starburst Switch Schematics and Codes
The Starburst &ch design, as was presented in this thesis, is accompanied with a technical
report document [la that provides:
The schematics for Il0 Module Printed Circuit Board (PCB) design-
PCB layout guidelines for the iOM.
The PL0 equations for the chip select decoder for each IOM PCB.
Pin assignment for the back plane bus connection for the IOM, CSF, and Clock
generator PCB.
The VHDL code for the Starburst Adapter module of the IOM-
The C code for the sofhrvare functions of the SCIM.
This technical report can be obtained from Professor Alberto Leon-Garcia at the Communications
group of the Department of Elecnical and Cornputer Engineering at the University of Toronto.
The schematics of the 110 Module, VHDL code for the Starburst Adapter, and the C code for the
System Controller Interface Module software fundons can, also, be obtained from Professor
LeonGarcia if required.
References
IlW-T Recommendation 1.361, '&ISDN ATM Layer Specification", March 1993.
ITU-T Recommendation 1.432, 'B-ISDN User-Network Interface: Physical Layer
Specification*, March 1993.
Indra Widjaja, 'High-Speed Packet Switching: Architectures and Performance", 1992.
Paul Chow, Paul Hodgins, David Karchmer, Tony Ngai, Jeewika Ranaweera, Ron White,
David Yeh, "ELEf 823s VLSl Systems Design: ATM Chip", JuIy 1993.
Axe1 Garcia, Massoud Hadjiahmad, "Modifications to The ATM Chip Test Circuitry",
August 1993.
Massoud Hadjiahmad, "ATM Switch Board: A Report on The PCB Design and
Functionality of The Board", August 1994.
Thomas M. Chen, Stephen S. Liu, "ATM Switching Systerns", 1995.
The ATM Forum Technical Committee, "UTOPIA Specification", Level 1, Version 2.01,
March 1994.
Fujitsu Inc., uAddress Translation Controller Product Data Sheet", Version 4.0, July 1996.
Fujitsu Inc., '155-Mbps SDWSONET ATM Transceiver Product Data Sheet", Version 4.1,
November 1 996-
Fujitsu Inc., "Network Temination Controller Product Data Sheet", Version 2.0, July 1996.
Pulse Engineering Inc., "FASTPULSE High Speed LAN Transceivers (PE68538G) Data
Sheet", JuIy 1996.
Applied Micro Circuits Corporation, 'S5933 PCI Contralier Data BOOK, 1996.
Applied Micro Circuits Corporation, "PCI Matchmaker Developer's Kit Technical
Reference Manual", 1996.
Massoud Hadjiahrnad, "Starburst Switch Design Technical Repofl, January 1998.
l MAGE EVALUATION TEST TARGET (QA-3)
APPLIED sr IMAGE. Inc S 1653 East Main Street