Abstract— This paper presents system level specifications of

an 8–channel CMOS analog front-end (AFE) with an 11-bit

analog to digital converter, which is used for acquiring certain

biopotential signals such as EEG, ECoG, ECG, and EMG, i.e.

signals for brain activities, heart activities, and muscle activities.

I. INTRODUCTION iopotentials are electrical signals; they are generated due

to action potentials produced from certain types of cells

which are composed of nerve, muscle, or heart tissues.

Among all kinds of biopotentials, the most common ones are

EEG, ECoG, ECG, and EMG. EEG and ECoG are introduced

by brain cells, ECG is generated by the heart, and EMG is

from muscle activity [1]. Thus, the signals are of great value in

obtaining information about structure and function of tissues

from which they are generated from. However, these medical

benefits largely depend on the accurate acquisition of the

electrical signals. In addition, with the growing number of the

global aging population, demand for health monitoring

devices has never been higher. Hospitals have invested

substantial resources and capital to track various kinds of

biopotential signals for everyone, because each type of

electrical signals requires different kinds of medical

equipment. Thus, it is a logical choice to build a general-

purpose and accurate analog front-end for a biopotential signal

recording system.

The AFE presented in this paper will be used to record

EEG, ECoG, ECG and EMG signals whose amplitudes range

from 5μV to 5mV and bandwidths range from dc to 2 kHz as

shown in Table 1 [1]. Thus, the system must introduce very

little noise, have a high common-mode rejection ratio

(CMRR), and have a high-power supply rejection ratio

(PSRR). Regarding the extremely low range of target signals,

a low-pass filter with 2 kHz will be developed. As biopotential

signals are collected through physical electrodes, the input of

the system must have huge input resistance to minimize

loading effect. Moreover, the differential DC offset created by

tissue-electrode interface should also be eliminated to avoid

output saturation. It is done by a chopper low noise amplifier

(LNA).

Per Table 1, the smallest amplitude of the four signals is

5μV and the common bandwidth is around from 0.01 Hz to 2

kHz. Consequently, the bandwidth of the whole system is

from 0.01Hz to 2 kHz. An analog to digital converter (ADC)

has a step size granularity of 12.89μV (before amplification) is

chosen to be 8 bits (256 steps).

The block diagram of the proposed system is given in

Fig. 1 and the system level specifications are summarized in

Table 2. This section will address each of the blocks

individually.

B

An 8-Channel General-Purpose Analog Front-End

for Biopotential Signal Measurement

Xue Yang, Jinming Hu, Zengweijie Chen, Hang Yang

Fig. 1. System block diagram (the first amplifier is a Chopper Low Noise Amplifier; the amplifier before ADC is Programmable Gain

Amplifier; the multiplexer is a 16-2 Multiplexer; the 16 Electrodes will go through Pre- Amplifier with 8 Channels).

II. BIASING CIRCUIT

We propose to use the short channel version of the beta-

multiplier reference (BMR), shown in the Fig. 2 below, to bias

the whole system because the BMR is a self-biasing circuit

and it has very good VDD sensitivity. [5] Compared to the

bandgap reference, the BMR has better power supply rejection

ratio (PSRR) and consume less power. Moreover, the

temperature sensitivity of the BMR can be improved by using

resistors whose resistances depend on temperatures.

III. PRE-AMPLIFIER

The pre-amplifier requires a chopper stabilized amplifier with

negative feedback setting the gain with different values with the

input capacitor and the feedback capacitor [1][6]. The goal of this

stage is to provide moderate gain while eliminating 1/f noise which

can be detrimental in low frequency applications. The realization

of this stage can be divided into two main components: the

chopper stabilizing modulators and the low power amplifier for

gain, combined with the negative feedback.

A. Design Considerations

The design considerations for this circuit is towards the need

to suppress 1/f noise, dc-offsets from input, and rejection of

CMRR signals to ultimately increase the SNR of the input signals

[7]. Some amplification of the signal (around 20-40 dB, closed

loop gain) is done and can be adjusted in accordance to later

amplification stages. A CMRR of 80 dB or greater should provide

enough common mode rejection for an implantable device [7].

PSRR is also a concern and is set at greater than 60 dB. The

bandwidth is set by the maximum bandwidth of the possible

detected signals, which encompasses dc-2k. Input-referred noise is

at minimum less than the extracellular and electrode background

noise, approximately 5-10 µVrms [10]. However, judging by the

results of more current designs, it seems that an input referred

noise of less than 2 µVrms is ideal [7]. Power is less of a concern

than SNR in this stage but it would be highly preferable to be

extremely low power for this application. Again, gauging from

recent designs, a power consumption of under 10 µW is very

desirable.

Lastly, a high input impedance is desired to not load the

electrodes used to supply the input signals.

Parameter Specification

Supply Voltage 3.3 V

Closed-Loop DC Gain 40 dB

CMRR > 80 dB

PSRR > 60 dB

Bandwidth > 4 kHz

IRN Voltage < 2 µVrms

B. Chopper Stabilization

Chopper stabilization is a very effective technique that shows

good noise performance under low power, low frequency

operations [8]. The chopper circuit operates by modulating the

input frequency to a much higher frequency where flicker noise is

negligible. The modulated signal is then amplified and

demodulated back to the baseband, while the flicker noise remains

at the specified chopper frequency [8]. A low pass filter would

TABLE III

PRELIMINARY DESIGN PARAMETERS

Fig. 2. Schematic of the Biasing Circuit.

suffice to eliminate the up-converted flicker noise, as well as

potential dc-offsets from input signals [7].

Preliminary simulations have been done to demonstrate the

functionality of the chopper circuits. A low voltage input signal

within the specified bandwidth is inserted into a modulator with a

set chopper frequency of 15 kHz. The topology for one of the

choppers is seen in Figure 4 below.

Afterwards, demodulation is applied with the same chopper

circuit. A low pass filter is added at each of the differential outputs

to eliminate unwanted distortion. Simulation results can be seen in

Appendix A.

C. Amplifier Design

The design of the amplifier is a folded cascode amplifier with

cross-coupled active loads, and can be seen in Figure 5 [9]. Using a

cascode structure is advantageous as the currents are partitioned

for the maximization of the noise efficiency, which is ideal for this

application [11]. Another advantage of this specific topology is

that it has a very high CMRR, although common mode feedback is

required to compensate for the high common mode amplification

in the second stage. The high CMRR is accomplished with the

cross coupled transistors, which offers a low impedance for

common mode signals but a high impedance for differential signals

[9].

Preliminary simulations have led to an open loop gain of 72

dB for varying frequencies from 100-1kHz. Further sizing

adjustments will be made to account for noise, CMRR, stability,

and power consumption. Simulation schematic and results can be

seen in Appendix A.

D. Feedback Circuit

The feedback circuit is accomplished by putting capacitive

feedback with pseudo-resistors prior to the input of the amplifier,

as seen in Figure 6 [6]. The feedback capacitor sets the gain along

with the input capacitor, at the ratio of Cin/Cfeedback. The modulator

and demodulator in this case would be placed before and after the

feedback nodes.

As previously mentioned, a common mode feedback circuit is

needed to offset the high common mode gain of the fully

differential circuit. A switched capacitor topology will be utilized

as it is highly linear [9].

Fig. 3. Amplifier with choppers/modulators for noise reduction [8].

Fig. 4. Modulator circuit for chopper network.

Fig. 5. Folded cascode amplifier topology [9].

Fig. 6. Negative feedback circuit [9].

The operation of the feedback is to achieve a common

mode voltage of (Vdd + Vss)/2. To do so, C3 and C4 are pre-

charged to Vdd when the clock is high, while C5 is discharged to

ground. As clock goes low, C5 is charging to Vdd, and the charge

balance becomes

Setting all capacitances equal, the equation then becomes:

IV. 16-to-2 MULTIPLEXER

As aforementioned, there will be 16 channels of

electrode inputs. Particularly, 8 probes, with 2 channels of

signal per probe. The multiplexer should be capable of

providing output signals as input of CMOS switches, and

therefore control the switches of each probe channel.

The multiplexer module is comprised of a CMOS

switching array, a switch control unit, and differential

difference amplifier serves as a buffer (Fig. 11). The switching

rate of the switches is set to 500k channels/s. Hence, a 𝑓𝑐𝑙𝑘 =

500 𝑘𝐻𝑧 is needed for such a module [1] [5]. In accordance to

Table IV, there are 3 control signals that have different

frequencies. As shown in Fig. 9, D1 must be switching at 500

kHz, D1 is switching at 250 kHz, and D2 has the frequency of

125 kHz. In a realistic design, since there is only 1 clock

frequency input, there will be a clock divider module that

processes the 500 kHz clock signal properly. Different clock

signals were used in the simulation for sake of convenience.

During operation, the inputs will be switched to a

channel’s (+) and (-) nodes simultaneously. To avoid

switching mistakes, i.e., signals from IN1+ and IN2- are fed

into the buffer, a mechanism needs to be considered. In our

design, we chose to hook every channel’s (+) and (-) onto the

same switch. Therefore, whenever a channel is chosen to

provide output, the (+) and (-) signals will come from the

same channel. The design and validation of this DDA will be

done per referring [14].

Data Select Signals Output

D2 D1 D0 Y

0 0 0 IN0+/-

0 0 1 IN1+/-

0 1 0 IN2+/-

0 1 1 IN3+/-

1 0 0 IN4+/-

1 0 1 IN5+/-

1 1 0 IN6+/-

1 1 1 IN7+/-

Fig. 7. Common mode feedback circuit [9].

Eq. 1. [9]

Fig. 8. Topology of 16-to-2 multiplexer.

TABLE IV

DIGITAL CONTROL LOGIC

Eq. 2. [9]

V. SAR ADC

A. Overall design

To process and analyze biopotential signals, the analog

signals must be digitized. The analog-to-digital converter in

this AFE receives analog signals from the PGA and convert

them into digital codes.

We considered four types of ADC, and decided to use an

SAR ADC in our system because it is frequently the

architecture of choice for 8 to 16-bit resolution applications

with sample rates under 5 Mbps [2]. A pipeline ADC is

undesirable because our input signals do not have large

bandwidth, and it has huge power consumption and large die

area [3]. A delta-sigma ADC is seemingly suitable for our

application as it is low power, high resolution and low cost.

However, considering the workload required to understand

and implement the delta-sigma structure, we thought it would

be inefficient to apply it. As the bandwidth of our signals of

interest is below 2k, and the whole system does not require

extremely high resolution, an SAR structure is chosen to be

the ADC in our design.

Our group is going to design an 8-bit successive

approximation routine (“SAR”) ADC. It has an LSB value of

12.89 mV, given the VDD to be 3.3V. Since the smallest

amplitude of the four biopotential signals, which is EEG per

Table 1, is 5μV, at most a total gain of 68.23 dB from all the

gain stages preceded is required.

The topology of a SAR ADC is presented in Fig. 12. The

SAR employs a binary search algorithm, and the above

topology is very area-efficient, very fast and power efficient.

The walden figure of merit (FOM) definition for ADCs is

defined as [4]:

fs represents the sampling frequency, and the ENOB stands for

effective number of bits and is calculated as:

ENOB stands for effective number of bits, and fs is the

sampling frequency. Since we are working on the 0.6 μm, the

Eq. 3. [4]

Eq. 4. [4]

Fig. 12. SAR ADC topology.

Fig. 9. Switching logic corresponds to clock signals.

Fig. 11. Schematic of DDA [1].

Fig. 10. Switch control signals vs. switch CMOS lines.

proposed ADC will try to achieve a FoM of 1 according to the

figure below [4].

B. Clock Divider Since the track and hold circuit and the SAR logic are

clocked at different rates, a clock divider is required to divide

the external clock frequency. The slower clock operates on the

S/H and the faster one acts on the SAR logic during the hold

period.

VI. PROGRAMMABLE GAIN AMPLIFIER

For benefits of the entire analog front-end, a

programmable gain amplifier in Fig. 14 is selected. The

selected differential switched-capacitor amplifier has a good

amount of advantages: offset voltage cancellation without

requiring the output to slew to ground each time the amplifier

is reset (see Fig. 15), insensitivity to low op-amp gain, clock

feedthrough cancellation, and both inputs of this differential

amplifier can be sampled at the same time [12].

Fig. 14. A switched-capacitor differential amplifier.

Fig. 15. Switched- capacitor simulation graph, with Vp = 51.34 V.

If assuming infinite gain for the switched- capacitor

amplifier,

Eq. 5.

Vout is independent of op-amp offset voltage, because of

the application of Correlated Double Sampling (CDS)

technique, where C1 and C2 are charged to offset voltage,

Voff, during amplifier reset (ɸ1), while C3 was sampled to be

Vout(n-1), i.e. Vout of previous cycle, during previous ɸ2.

During reset stage, Vout is changed only by the op amp input

offset voltage. This means that the amplifier does not need to

slew to ground during reset stage, which suggests a low slew

rate requirement. In valid output (ɸ2), Vout is independent of

Voff. See Fig. 16 below [13].

Fig. 16. Simplified version of top part of selected circuit; first graph: reset

stage; the second graph: regular output.

Because a gain of 30 – 40dB is expected of this

amplifier, A is set to be 150 for ideal op amp model Spice

simulation. With a finite gain, the gain error is set to be

proportional to A-2. The following transfer function is

presented for low frequencies:

Eq. 6.

This could allow the usage of low-gain single- stage

amplifiers [12].

In the switched- capacitor circuit, 𝑓𝑐𝑙𝑘 = 500𝑘𝐻𝑧, and

the following circuit, Fig. 17 is implemented for clock signal

generation. See Appendix A for clock generation Spice model

implementation.

Fig. 13. CMOS fabrication technology vs. FoM.

Fig. 17. Clock generation graph.

Fig. 18. Clock generation Spice signal

The primed clock signals happen before nonprime

signals to prevent charge escaping through C3 and C3_2. Cdelay

in the circuit graph can be tweaked to adjust time delay values.

The delay will leave the op amp open-loop the set delay time

at the end of ɸ’1, but it will only cause output “glitches” at

clock transitions [12].

Because the amplifier will be used to process signals

from EEG, ECoG, ECG and EMG, the amplification level of

Vin can be adjusted by varying C1 values, i.e. arranging other

C1_EEG, C1_ECG, etc. to be in parallel with existing C1 with

switch signals sent by other clock signals. Below shows an

example:

A single-ended output folded cascade op amp with slew-

rate enhancement will be used for transistor level op-amp

design. See Fig. 20.

Fig. 20. Folded cascode with gain enhancement op amp design [12]

VII. TIMELINE

See Appendix A for timeline.

Fig. 19. Variable C1 capacitor sample graph built upon Fig. 14

References

[1] Chen, Wei-Ming, et al. “The Design of CMOS General-

Purpose Analog Front-End Circuit with Tunable Gain and

Bandwidth for Biopotential Signal Recording Systems.” 33

Annual International Conference of the IEEE EMBS.

Boston, Massachusetts: IEEE, 30 Aug. 2011. 4784–4787.

Available:

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6091

185. Accessed: Feb. 3, 2017.

[2] "Understanding SAR ADCs: Their architecture and

comparison with other ADCs - Tutorial - maxim," in

maxim integrated, 2017. [Online]. Available:

https://www.maximintegrated.com/en/app-

notes/index.mvp/id/1080#. Accessed: Mar. 6, 2017.

[3] "Choose the right A/D converter for your application," in

Texas Instrument. [Online]. Available:

https://www.ti.com/europe/downloads/Choose%20the%20

right%20data%20converter%20for%20your%20applicatio

n.pdf. Accessed: Mar. 6, 2017.

[4] Posted, "ADC performance evolution: Walden figure-of-

merit (FOM)," Converter Passion, 2012. [Online].

Available:

https://converterpassion.wordpress.com/2012/08/21/adc-

performance-evolution-walden-figure-of-merit-fom/.

Accessed: Mar. 6, 2017.

[5] J. R. Baker, CMOS: Circuit design, layout, and simulation

- 3rd edition, 3rd ed. United States: Wiley, John & Sons,

2010.

[6] C. Charles. and R. Harrison, "A floating gate common

mode feedback circuit for low noise amplifiers - IEEE

Xplore document,". [Online]. Available:

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1190

422&tag=1. Accessed: Mar. 6, 2017.

[7] V. Das, D. Lie, and T. Nguyen, "A fully integrated low

noise CMOS instrumentation amplifier design for low-

power biosensors - IEEE Xplore document," 2014.

[Online]. Available:

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6908

470. Accessed: Mar. 6, 2017.

[8] D. Yates and E. Rodriguez-Villegas, "An ultra low power

low noise chopper amplifier for wireless EEG,". [Online].

Available:

https://spiral.imperial.ac.uk/bitstream/10044/1/6107/1/ultra

-wireless-EEG.pdf. Accessed: Mar. 6, 2017.

[9] J. Arias, L. Quintanilla, L. Enriquez, J. Vicente, and J.

Barbolla, "Design of a CMOS fully differential switched-

op-amp for SC circuits at very low power supply voltages -

IEEE Xplore document," 2017. [Online]. Available:

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9575

10. Accessed: Mar. 6, 2017.

[10] S. Cerida, E. Raygada, C. Silva, and M. Monge, "A low-

noise fully differential recycling folded cascode neural

amplifier - IEEE Xplore document," 2017. [Online].

Available:

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=72

50497. Accessed: Mar. 6, 2017.

[11] T. Denison, K. Consoer, A. Kelly et. al.,” A 2.2 µW 94

nV, rt. Hz, Chopper-Stabilized Instrumentation

Amplifier for EEG Detection in Chronic Implants”

ISSCC Dig. Tech. Papers pp.162-163, 2007.

[12] Martin, K. et al, “A differential switched-capacitor

amplifier”, IEEE J. Solid-State Circuits, vol. 22, no. 1,

pp. 104-106, February 1987.

[13] D. Johns and K. Martin, “Switched- Capacitor Circuits,”

in Analog Integrated Circuit Design, 2nd ed. New York,

John Wiley & Sons, 1997, ch. 14, p. 591 - 593.

[14] H. Alzaher and M. Ismail, "A CMOS fully balanced

differential difference amplifier and its applications,"

in IEEE Transactions on Circuits and Systems II: Analog

and Digital Signal Processing, vol. 48, no. 6, pp. 614-

620, Jun 2001.

doi: 10.1109/82.943332

Appendix A

Folded Cascode Amplifier

Simulation of Folded Op-Amp

Modulator/Demodulator circuit

Modulated input signal

Demodulated signal vs. input signal

Clock generation Spice model.

Timeline

Individual Simulation Kick-off

Complete Individual Simulation

System Level Simulation and Optimization

Complete System Simulation

ADC Layout

Project Wrap-up

Mar. 6th Mar. 19th Mar. 20th April 14th April 15th May 1st