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04/25/2003

AN-6003“Shoot-through” in Synchronous BuckConverters

Jon Klein Power Management Applications

AbstractThe synchronous buck circuit is in widespread use toprovide “point of use” high current, low voltagepower for CPU’s, chipsets, peripherals etc. In thesynchronous buck converter, the power stage has a“high-side” (Q1 below) MOSFET to charge theinductor, and a “Low-side” MOSFET which replacesa conventional buck regulator’s “catch diode” toprovide a low-loss recirculation path for the inductorcurrent.

+

–

V IN

PW

M C

ON

TR

OL

LE

R

L1

H igh-S ideQ 1

Low-S ideQ 2

VOUT

Figure 1. Synchronous Buck output stage

Shoot-through is defined as the condition when bothMOSFETs are either fully or partially turned on,providing a path for current to “shoot through” fromVIN to GND. To minimize shoot-through,synchronous buck regulator IC’s employ one of twotechniques to ensure “break before make” operationof Q1 and Q2 to minimize shoot-through:

1. Fixed “dead-time”: A MOSFET is turned off,then a fixed delay is provided before the low-side is turned on. This circuit is simple andusually effective, but suffers from its lack offlexibility if a wide range of MOSFET gatecapacitances are to be used with a givencontroller. Too long a dead-time means highconduction losses. Too short a dead time cancause shoot-through. A fixed dead-timetypically must err on the “too long” side to allowhigh CGS MOSFETs to fully discharge beforeturning on the complementary MOSFET.

2. Adaptive gate drive: This circuit looks at theVGS of the MOSFET that’s being driven off todetermine when to turn on the complementaryMOSFET. Theoretically, adaptive gate drivesproduce the shortest possible dead-time for agiven MOSFET without producing shoot-through.

In practice, a combination of adaptive and fixedproduces the best results, and is typically what is intoday’s PWM controllers and gate drivers as shownin Figure 2

SW

LDRV

HDRV

Delay

1V

PGND

+

1V

PW M

+

PW M

Delay

D1+5

BOOT RG

GR GATE

C GS

C GD

VIN

D

S

R GATE

C GS

C GD

D

S

G

Q1

Q2

C BOOT

Figure 2. Typical Adaptive Gate drive

Even though there apparently is a “break beforemake” action by the controller, shoot-through canstill occur when the High-side MOSFET turns on,due to Gate Step.

Shoot-through is very difficult to measure directly.Shoot-through currents persist for only a few nS,hence the added inductance in a current probedrastically affects the shoot-through waveform.Shoot-through manifests itself typically as increasedringing, reduced efficiency, higher MOSFETtemperatures (especially in Q1) and higher EMI.This paper will provide analytical techniques topredict shoot-through, and methods to reduce it.

Shoot-through in Synchronous Buck Regulators AN-6003

04/25/2003 2

“Gate Step” – The shoot-through culpritIf the adaptive circuits are working, then weshouldn’t see any shoot-through, right?

Not exactly. Most shoot-through occurs when thehigh-side MOSFET is turned on. The high dv/dT onthe SW node (Drain of the low-side MOSFET)couples charge through CGD. This drives the gatepositive at the very moment when the driver is tryingto hold the gate low. CGD and CGS form a capacitivevoltage divider, which attenuates the gate step suchthat the worst case peak amplitude of the gate step(VSTEP) seen is:

−•••≈

+•−

)CC(RT

R

INGDT)PK(STEP

GSGDT

R

e1TV

CR V

(1a)

Where RT = RDRIVER + RGATE + RDAMPING (see Figure 5),and TR is the rise-time of the SW node.

The limiting case is when TR = 0. Then

GSGD

GDIN)MAX(STEP CC

CV V

+•≈ (1b)

This expression only illustrates the AC portion of thegate step. The gate step is injected onto whatevervoltage the MOSFET’s gate has discharged to. Forexample, if the switch node rises when VGS = 1V,and the gate step amplitude is 2V, instantaneouslythere will be 3 VGS which is more than enough tohave a high instantaneous current through bothMOSFETs. It’s important, therefore that adaptivegate drive circuits allow sufficient delay to preventthe high side from turning on before the low-side VGS

is discharged down to a few hundred mV.

An illustration of gate step is seen below.

0

1

2

3

4

5

6

0 20 40 60 80

t (nS)

VG

S

-2

0

2

4

6

8

10

12

14

V

SW NODE VOLTAGE

LS MOSFET GATE

Figure 3. Gate Step for VIN .=12V.

0

1

2

3

4

5

6

0 20 40 60 80

t (nS)

VG

S

-5

0

5

10

15

20

25

V

SW NODE VOLTAGE

LS MOSFET GATE

Figure 4. Gate Step for VIN .=20V

Further exacerbating the problem for adaptivecircuits is the fact that the adaptive comparator is notactually sensing the voltage at the internal gatejunction of the MOSFET. As seen in Figure 5, theinternal MOSFET’s gate voltage has an unavoidableinternal RGATE resistance. In addition, some designerslike to have a “damping” resistor in series with thegates of MOSFETs that are located physically faraway from their gate drives. This creates a biggerproblem for the adaptive gate drive circuit. Theseseries resistances form a voltage divider with theinternal pull-down resistance of the low-side gatedrive of the IC, causing it to think the gate voltage islower than it really is when it decides to release theHigh-side driver.

RDRIVER

RDamping

H.S. MOSFET

1V

HDRV

LDRV RGATE

CGS

CGD

D

S

G

Q2

Delay

Figure 5. Resistance in the gate drive pathattenuates the voltage at the MOSFET gate node.

When there is 1V at the pin of the IC, the internalMOSFET VGS is:

( )DampingGATEDRIVERDRIVER

)I(GS RRR R

V1V ++•=

Consider an example where:

RDRIVER = 2Ω , RGATE = 1.2ΩRDAMPING = 5Ω

Shoot-through in Synchronous Buck Regulators AN-6003

04/25/2003 3

When the adaptive gate circuit switches, the internalMOSFET gate voltage will be:

( ) V1.452.122V1 =Ω++•Ω

In this example, if there were no delay in the circuit,the HDRV would turn on when the low-sideMOSFET has just begun to discharge, causing a veryhigh shoot-through current.

Much of the problem in the above circuit is thedamping resistor. If a damping resistance isnecessary, place a Schottky diode across the resistor(as shown below) to reduce the effect the dampingresistor will have on the adaptive gate drive.

RDRIVER

RDamping

H.S. MOSFET

1V

HDRV

LDRVDelay

H.S. MOSFET

RGATE

CGS

CGD

D

S

G

Q2

Figure 6. Schottky diode reduces dampingresistor error in adaptive gate drive

When using the schottky, the internal gate node willbe at:

( )GATEDRIVERDRIVER

)I(GS RRR

V15.0V +•+=

or 2.1V for our example. A dramatic improvement.Furthermore, the Schottky reduces the duration of theshoot-through step, since only RGATE + RDRIVER will bedischarging CGS, rather than the sum ofRGATE + RDAMPING + RDRIVER .

Table 1 below illustrates the performanceimprovement in our example with and without theSchottky diode:

No Schottky

With Schottky

Comparator Flips @ VGS(INT) = 4.1 2.1 VVGS(INT) after 20nS delay 2.23 1.14 VVSTEP Peak 2.50 1.25 VPeak current 36 0.29 APower Loss @ FSW=300KHz 1100 20 mW

Conditions: Typical low-side MOSFET, 25nSdelay from comparator sense to beginning of SWnode rise, 19VIN, 10nS SW node rise time.

Table 1 . Peak Currents with and withoutSchottky with RDAMPING = 5Ω .

MOSFET ChoicesMOSFET characteristics can have a dramatic effecton how much shoot-through current can be inducedby the gate step. The worst case for shoot-through isan infinitely fast (0 rise time) on the drain node. Theamount of gate step is largely determined by theration of CGS and CGD . Once the size of the gate stepis determined (eq. 1 above), the peak magnitude ofthe shoot-through current can be calculated as :

( ))MIN(THSTEP(MAX)M)MAX(PEAK VVGK I −••≈ (2)

where GM is the transconductance (in S, or A/V)given in the datasheet. While only a smallpercentage of MOSFETs exhibit VTH(MIN) at roomtemperature, VTH goes down with increasing junctiontemperature, therefore VTH(MIN) is a good proxy for theVTH at the operating junction temperature of theMOSFET. Subsequent calculations use VTH(MIN) forthis reason.

GM is not really a contstant, however, and its value isgreatly reduced low enhancement voltages (VGS-VTH).In these calculations we use a factor "K" from thegraph below, which is typical of GM with low valuesof enhancement. The X axis of Figure 7 is calculated

as )MIN(TH

)MIN(THGSV

VV −

0.0

0.2

0.4

0.6

0.8

1.0

0% 50% 100% 150% 200% 250% 300%Normalized Enhancement Voltage

K (G

M M

ultip

ler)

Figure 7 GM factor (K)

Table 2 shows the relevant MOSFET characteristicswhich determine the maximum shoot-throughcurrent.

MOSFET CGS CGDTypical

VTH

Min VTH

GM

MOSFET1 3,514 307 1.6 1 86MOSFET2 5,070 230 1.2 0.8 97MOSFET3 4,942 315 1.6 1 80MOSFET4 3,888 401 1.6 1 135MOSFET5 6,324 281 1.15 0.6 90

Table 2 . Low-Side MOSFET Characteristics

Shoot-through in Synchronous Buck Regulators AN-6003

04/25/2003 4

Each of the MOSFETs represented is from a differentprocess and has different ratios of internalcapacitance.

MOSFET VSTEP(MAX) VTH(MIN)VSTEP

VTH(MIN)

IPEAK

(max)MOSFET1 1.53 1 0.53 0.31MOSFET2 0.82 0.8 0.02 0.02MOSFET3 1.14 1 0.14 0.07MOSFET4 1.78 1 0.78 16.37MOSFET5 0.81 0.6 0.21 0.13

Table 3. Maximum VSTEP and ISHOOTTHROUGH @VIN = 19V and VGS(START) = 0V.

Table 3 assumes that the VGS has dropped to 0 beforethe SW node rises when HDRV turns on. Asdemonstrated above, the smallest amplitude of VSTEP

comes from MOSFET2 and MOSFET5, which arelow-threshold devices. Low threshold in large part isdue to a thin gate oxide, giving the MOSFET a high

GD

GS

CC

ratio, which attenuates VSTEP. more than other

MOSFETs.

Also, Table 3 only shows the theoretical peak currentin Q2 due to the gate step. In a real converter,parasitic inductance limits the rise in current to4A/nS. Even for the MOSFET4, the gate pulse onlystays above threshold for about 5nS, so the shoot-through current would be further limited.

An additional shortcoming of the simplifiedcalculations of Table 3 is the assumption that SWnode turn-on begins when VGS of the low-side is at 0.As we saw from the earlier discussion, this may notbe the case.

Reducing gate step by slowingdown Q1 rise timeUsually, designers attempt to achieve the fastest rise-time possible on the High-Side MOSFET in order tominimize switching losses. A simplified expressionfor turn-on losses (P(TURN-ON)) for the high-sideMOSFET is:

••

•≈− 2

IVTFP OUTINR

SWONTURN (3)

where TR is the rise-time of the MOSFET. A very

fast rise-time (high dtdV

on SW) is desirable to

minimize high-side power dissipation, but if it resultsin a large gate-step, causing shoot-through, thedissipation effect can be greater than the dissipationinduced by slowing the rise time. In some situationsthis is the only practical approach to eliminate shoot-through.

As can be seen in Figure 8, slowing down the risetime has a dramatic effect on the amplitude of VSTEP

that is coupled into the Low-side MOSFET gate. TR

slowdown has the added benefit of reducing EMI, butcomes at a cost of efficiency loss . Figure 8 andsubsequent tables were simulated with MOSFETstypical of those used in notebook PC’s (2 in parallel)with 15A output current and 19VIN. Figure 8 assumesthat the SW node begins to rise when the internalgate node has discharged down to 0.5V.

Shoot-through in Synchronous Buck Regulators AN-6003

04/25/2003 5

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 5 10 15 20 25 30 3519V RiseTime(nS)

V(S

TE

P) P

eak

MOSFET4MOSFET1MOSFET3MOSFET5MOSFET2

Figure 8 . Effect of SW node rise-time on VSTEP

VIN=19V, SW rise starts @ VGS(Q2) = 0.5V

Table 4 shows the power loss due to shoot-throughfor each MOSFET.

The major component of switching loss during Q1turn-on is:

2IV

FtP OUTINSWRONTURN

•••≈− (3)

and is computed in the right-most column for eachrise-time in Table 4 for IOUT = 15A.

TR(SW) FET1 FET2 FET3 FET4 FET5 Q1 tR Loss5 18 10 10 56 27 214

10 12 6 6 39 24 42815 7 3 3 28 19 64120 3 0 0 19 16 85525 0 0 0 11 12 1,06930 0 0 0 4 8 1,283

Table 4. Worst case (Min VTH) shoot-throughpower loss (mW)

SW rise starts @ VGS(Q2) = 0.5V

In most cases, the shoot-through is negligble, soslowing down high-side rise-time would not be aprudent choice, since the more power would be lostin slowing down the rise time than power saved byeliminating shoot-through.

If, the controller's gate drive starts to turn Q1 onbefore allowing the internal node of Q2 to discharge,

SW will rise when there is still a substantial VGS onQ2 as shown is Table 5. Slowing down Q1 can thenbe an effective strategy to reduce shoot-throughlosses.

TR(SW) FET1 FET2 FET3 FET4 FET5 Q1 tR Loss5 90 62 29 380 551 214

10 30 31 24 127 266 42815 23 26 18 61 58 64120 16 21 13 50 54 85525 8 16 7 39 51 1,06930 0 11 1 25 47 1,283

Table 5. Worst case (Min VTH) shoot-throughpower loss (mW)

SW rise starts @ VGS(Q2) = 1V

This is typically achieved by adding resistance (RGin Figure 2) in series with CBOOT . An approximationfor TR provides a good starting point for choosing avalue of RG:

( ) RGR CT )HL(DRIVEGSR +•≈ − (4)

where RDRIVE(L-H) is the resistance of the IC’s high-sideMOSFET gate driver when driving from low to high.

Shoot-through in Synchronous Buck Regulators AN-6003

04/25/2003 6

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