Physics116A,12/4/06

Draft Rev. 1, 12/12/06

D. Pellett

Amplifier Frequency Response, Feedback, Oscillations;

Op-Amp Block Diagram and Gain-Bandwidth Product

2

Negative Feedback and Voltage Amplifier

• See solution of assigned Prob. 10.35 for proof of relations. (I did AF ingeneral before. May do RiF on board if time permits.)

• Note RiF is increased (improved) and RoF is decreased (also improved).

• Example: If A = 200000, Rin = 2 M!, Ro = 75 ! and B = 1/20,then A = 20, RiF = 20 G! and RoF = 7.5 m!.

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(see solutions to Prob. 10.35 for proofs)

AB is called the loop gain.

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Voltage Amplifier: AF dependence on AB = 1/20, AF = A/(1 + AB) = [A!1 + B]!1:

A AF

200000 19.998100000 19.99610000 19.961000 19.6500 19.2200 18.2100 16.750 14.3

• AFmax= 20. If A >> AFmax

, AF is insensitive to A. AF is down "3 dB frommaximum when A = 50.

• Reduces distortion due to A nonlinearity, allows for variations in amplifiergain from device to device. (What Black wanted back in the 1920’s forhis telephone long-distance line amplifiers)

• Suppose A is 200000 at low frequency (say 1 Hz) but falling with fre-quency like 1/f at high frequencies due to a built-in low-pass filter withfc = 5 Hz. With feedback, the -3 dB bandwidth would be improved,since AF remains high until A has fallen many orders of magnitude.

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Phase-Shift Oscillator and AB = -1

Phase-Shift Oscillator

• See solution of assigned Prob. 10.35 for proof of relations. (I did AF ingeneral before. May do RiF on board if time permits.)

• Note RiF is increased (improved) and RoF is decreased (also improved).

• Example: If A = 200000, Rin = 2 M!, Ro = 75 ! and B = 1/20,then A = 20, RiF = 20 G! and RoF = 7.5 m!.

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Sinusoidal oscillation when AB=-1

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Amplifier Low Frequency Limitations

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Amplifier Low Frequency Limitations (continued)

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Amplifier High Frequency Limits• Model for parallel (shunt) capacitances to ground in amplifier

circuit:

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Amplifier High Frequency Limits

Where are these shunt capacitances?

• Model for parallel (shunt) capacitances to ground in amplifier circuit:

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Common Emitter Amplifier HF Limits

• At high frequencies, must consider BE and BC diode capacitances

CBC

CBE

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Shunt Capacitances In Small-Signal AC Models

• How to deal with Cc (or Cgd) which connects input and output?

Base-Emitter Diode Capacitance Base-Collector Diode Capacitance

Simple BJT Model at High Frequencies:

Simple HF JFET Model:

10

Use Miller’s Theorem to Split Cc (or Cgd)

Apply to HF BJT model in a common emitter amplifier with gain = -A:

• Input circuit (be) and output circuit (ce) are now separated11

Miller’s Theorem Proof

• QED

Given:

Node 2 (write in terms of v2):Node 1(write in terms of v1):

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Common Emitter Amplifier Input Stage

CE Amplifier

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Common Emitter Amplifier Output Stage

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FET HF Model and Analysis

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Input Circuit Upper Corner Frequency for 9.54

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Output Circuit Upper Corner Frequency for 9.54

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MOSFET Amplifier Example

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Effect of CS on Low Frequency Response

Simple HF JFET Model:

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Upper Corner Frequency: Input StageSimple HF JFET Model:

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Output Stage Upper Corner FrequencySimple HF JFET Model:

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Ways to Improve Amplifier HF Response

• Reduce Miller effect

• Common Base amplifier (see solution to Problem 9.21)

• Differential Amp using non-inverting input with inverting input grounded

• Cascode circuit – similar to above

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Common Base Detector Amplifier

• No Miller effect since cc, cc grounded at base; fast if use fast BJT (small cc, cc etc.)

*small signal AC model

*

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Can We Understand Amplifier Operation?

• This is an amplifier for short pulses of width ~1 ns.

• Pulse response is covered in 116B (i.e., beyond the scope of this course) but we can understand its operation based on what we have learned so far in Physics 116A plus basic physics.

• We want the output pulse to have a fast risetime (sharp leading edge).

• If Rs ≈ 50 Ω, the input emitter circuit has fc ≈ 2 GHz so the BJT delivers a short current pulse at the collector which follows the input voltage: ic(t)≈ αvin(t)/re.

• The collector current is integrated: ∫pulse ic(t) dt = Q = Cv′ to charge the combined capacitance C = 2 Cc of the input BJT and the first BJT in the Darlington pair, producing the rapidly rising leading edge of v′ and the output pulse.

• Integration occurs because the time constant of the BJT collector circuit is τ = RC = 20 kΩ x 2 pF = 40 ns, much longer than the input pulse width (assume the base current of the Darlington input transistor is negligible).

• The pulse height of the output pulse is proportional to the charge of the input pulse.

• The output is thus expected to look like the sketch. The tail can be shortened using a “speedup” RC network following the emitter follower output (not shown).

(this page is supplementary material – not on final)

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Check Simple Model With SPICE

• Uses MPSH10 RF amplifier BJT: cc = 1 pfce = 1.5 pf

• SPICE BJT model for MPSH10 is available from Fairchild web site:www.fairchildsemi.com

• vin = V(5) (red)vout = V(8) (green)

• Good agreement with simple model

time

voltage

XXX

0.0 20.0 40.0 60.0 80.0 100.0

ns

-20.0

-0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

mV V(5) V(8)

Page 1 of 1Fast_Pulse_Amp.cir

Printed: Sunday, December 10, 2006 5:06:46 PM

Fast Pulse Amplifier

********************

VEE!4! 0! DC! -12

VBB!2! 0! DC! -6

RC! 0! 1! 20K

Q1! 1! 2! 3! QMPSH10

RE1!3! 4! 20K

C1! 5! 3! .01u

VS! 9! 0! PWL ( 0 0V 1ns 0.05V 2ns 0V )

RS! 9! 5! 50

Q2! 0! 1! 6! QMPSH10

Q3! 0! 6! 7! QMPSH10

RE2!7! 4! 500

C2! 7! 8! .01u

RO! 8! 0! 1K

RI! 5! 0! 10K

********************

.model QMPSH10 NPN(Is=69.28E-18 Xti=3 Eg=1.11 Vaf=100 Bf=308.6 Ne=1.197 Ise=69.28E-18

+ Ikf=22.83m Xtb=1.5 Br=1.11 Nc=2 Isc=0 Ikr=0 Rc=4 Cjc=1.042p Mjc=.2468 Vjc=.75 Fc=.5

+ Cje=1.52p Mje=.3223 Vje=.75 Tr=1.558n Tf=135.8p Itf=.27 Vtf=10 Xtf=30 Rb=10)

********************

.TRAN! .1ns! 100ns

.control

run

plot! V(5) V(8)

.endcontrol

.END

(this page is supplementary material – not on final)

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Other Possibilities to Avoid Miller Effect

• Note the common base circuit lurking in both

High Av here

High Av here

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BiFET Op-Amp Simplified Diagram

• The differential amplifier and common emitter amplifier use the large Thévenin equivalent AC resistance of a current source along with the input resistance of the following stage to achieve large gain. See text, Sec. 10.2.

• Note C1 makes use of the Miller Effect to achieve a large effective capacitance for a dominant low-pass filter.

BJTs have identical characteristics

p-channel JFETs

Current source and input resistance of next stage play role of RD or RC for amplifier

S

DC

E

IREFVOUT

+VCC

-VEE

C1

Three-stage amplifier:

Effect of Dominant Low-Pass Filter

Upper corner frequency is multiplied by (loop gain +1)≈loop gain

Finally,

• The maximum phase shift is 90°∘(won’t oscillate for resistive B).

• The product of gain and bandwidth is constant.

• High frequency performance is compromised. 28

Bode Plot: AF and Bandwidth

AF(dB) ≈ A(dB) - (AB)(dB)

At low frequencies in the example above,

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741 Specifications

Input Bias Current 80 nAInput O!set Current 20 nAInput O!set Voltage 1 mV

Max. Slew Rate 0.5 V/µsOpen Loop Gain 200000Gain-BW Product 1 MHzInput Resistance 2 M"

Output Resistance 75 "CMRR typ. 80-100 dB

• Output protected against short-circuits

• Input o!set voltage can be balanced out with external pot

• See Sec. 10.2 for details

10

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Bode Plot for µA702A Op-Amp

• No large C1: Could make amplifier with BW of several MHz.

• Considerable gain left when phase shift equals 180 degrees at 12.5 MHz.

• Not fool-proof: A unity gain voltage follower would oscillate.

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No dominant pole: has 3 low-pass filters in series.Amplifier phase shift >180°with significant gain and can oscillate with a resistive feedback network.

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BJT CE Large Signal Performance

• The maximum output voltage swing is set by BJT cuto! and saturation

• Start with the BJT curves of IC vs. VCE for various values of IB, locateQ point

• Draw straight line through Q point with slope dIC/dVCE for midband ACsignals (AC Load Line) to determine useful range

• For AC, vc = !RCic so AC load line slope = ic/vc = !1/RC in this case.Output voltage swing follows AC load line.

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CE Amplifier: DC and AC Load Lines

0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

IC vs VCE for 2N2222A npn BJT (SPICE simulation)

I C (

mA

)

VCE (V)

IB = 8 µA

IB = 0 µA

IB = 4 µA

IB = 12 µA

IB = 16 µA

Q Point

AC Load Line

DC Load Line

VCC

RC + RE

VCC

• Max. symmetrical voltage swing when Q point centered on AC load line

• At Q, no input, BJT power dissipation p ! VCEIC = 4 V"2 mA = 8 mW

• If the Q point is centered, the average power dissipated by the BJT ismax. with no AC input – actually less when producing a signal. (Seesec. 9.4 in text for details)

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Push-Pull Emitter Follower

• Base bias chain keeps both BJTs just at cuto! (or slightly “on”) at Qpoint – ! No BJT power dissipated if no input signal.

• AC input causes one or the other BJT to provide the output.

• Maximum average BJT power now 0.1VCEQiC(sat) – much more e"cient

use of BJTs and power – useful for driving low impedance loads at highpower

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