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L4: Verilog Design of Sequential Logic 2012/2013-1
VERILOG DESIGN OF
SEQUENTIAL LOGIC
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L4: Verilog Design of Sequential Logic 2012/2013-1
⋅ Synchronous sequential logic circuits rely on storage elements for their operations.
⋅ Flipsflops (FFs) and latches are two commonly used onebit storage elements.
⋅ Others as registers, shift registers, and counters. ⋅ Only synchronous sequential logic is considered.
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L4: Verilog Design of Sequential Logic 2012/2013-1
LATCHES & FLIPFLOPS
⋅ A latch is a levelsensitive memory device (transparent). o As long as the pulse remains at the active high level, any
changes in the data input will change the state of the latch. o A flipflop (FF) is an edgetriggered memory device.
⋅ An edgetriggered FF ignores the pulse while it is at a constant level (nontransparent).o Triggers only during a transition of the clock signal.o Could on the positive edge of the clock (posedge), or negative
edge (negedge).
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L4: Verilog Design of Sequential Logic 2012/2013-1
D Latch
⋅ A latch is inferred because the IF statement is incomplete.⋅ The notion of implied memory is instantiated in this case.
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…
always @ (S or Data_In)if ( S ) Data_out = Data_In;
…
L4: Verilog Design of Sequential Logic 2012/2013-1
Signal edge detection in Verilog
⋅ The always blocks are sensitive to the levels of the signals that appear in the sensitivity list.
⋅ FF changes only as a result of a clock transition of the clock signal, rather than its level.
⋅ Verilog uses event qualifier posedge and negedge⋅ E.g., always @ (posedge clock).
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L4: Verilog Design of Sequential Logic 2012/2013-1
Basic positiveedge triggered D flipflop:
Note: Synthesis tools do not support mixed sensitivity, for example:always @ (posedge clock or reset).
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f/fD
Q
d
CLKq
module FF (CLK, d, q) ;input CLK, d ; output q ;
reg q ;
always @ (posedge CLK)q = d ;
endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Blocking and NonBlocking Assignments
⋅ In a sequential block, blocking assignment statements (=) are evaluated immediately in the order they are specified.
⋅ Called blocked assignments because a statement must complete execution (i.e. update memory) before the next statement can execute.
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module shiftregY (A, B, C, D, clk) ;input D, clk ; output A, B, C ;reg A, B, C ;always @ (posedge clk) begin
C = D ;B = C ;A = B ;
endendmodule
qdD A
clk
L4: Verilog Design of Sequential Logic 2012/2013-1
⋅ A nonblocking assignment ( <=) is called concurrent procedural assignments.
⋅ Allows scheduling of assignments without blocking execution of the statements that follow.
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module shiftregX (A, B, C, D, clk) ;input D, clk ; output A, B, C;reg A, B, C ;
always @ (posedge clk) begin
A <= B ;B <= C ;C <= D ;
endendmodule
module shiftregY (A, B, C, D, clk) ;input D, clk ; output A, B, C;reg A, B, C;
always @ (posedge clk) begin
C <= D ;B <= C ;A <= B ;
endendmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Executed concurrently rather than sequentially.⋅ The order has no effect. ⋅ The statements are evaluated using the values when the always
block is entered. ⋅ The result of each nonblocking assignment is not seen until the end
of the always block.
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q q qd d dD C B A
clk
Fig. 4-1
L4: Verilog Design of Sequential Logic 2012/2013-1
Recommendation:
When modelling logic that includes edgetriggerred register transfers:⋅ The synchronous (i.e. edgesensitive) operations be described by
nonblocking assignments⋅ The combinational logic be described with blocking assignment
statements.
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L4: Verilog Design of Sequential Logic 2012/2013-1
Example 44: D flipflop with asynchronous reset.
Exercise: Modify to include activelow asynchronous reset (RST) and preset (PST) inputs.
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f/fD
Q
Data_in
CLKData_out
clr
RST
module FF2 (CLK, Data_in, RST, Data_out);input CLK, Data_in, RST; output Data_out;reg Data_out;
always @ (posedge RST or posedge CLK)if ( RST ) Data_out <= 0 ;else Data_out <= Data_in ;
endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Example 45: Flipflop with a tristate output
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f/f
D
Q
CLK
Data_outEN
Data_In
C
OE
module tri_DFF (CLK, EN, OE, Data_In, Data_Out ); input CLK, EN, OE, Data_in;output Data_Out ;
reg Temp ;
always @ (posedge CLK) if (EN) Temp = Data_In;
assign Data_Out = OE ? Temp : 1‘bz ; // tristate function
endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Registers
⋅ Registers are just nbit (n >1) structures consisting of FFs. ⋅ A common clock is used for each FF in the register.
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L4: Verilog Design of Sequential Logic 2012/2013-1
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module reg8 (clock, load, rst, pst, data, Q);input clock, load ;
input rst, pst ; input [7:0] data ;
output [7:0] Q ;reg [7:0] Q ;
always @ (posedge rst or posedge pst or negedge clock)
if (rst) Q <= 0 ;else if (pst) Q <= 1 ;else if (load) Q <= data ;
endmodule
reg8load
clock
data D
en
clkclr
rst
q Q8
8
pst
pre
L4: Verilog Design of Sequential Logic 2012/2013-1
The timing diagram?
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clk
load
pst
rst
Q
data1 data2 data3data
L4: Verilog Design of Sequential Logic 2012/2013-1
Shift registers
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module shiftLreg8 (clk, rst, en, ldsh, w, d, q) ;
input [7:0] d ;input clk, rst, en, ldsh, w ;output [7:0] q ;integer k;
....
always @ (negedge rst or posedge clk) beginif ( !rst )
q <= 0 ;else if ( en )
if ( ldsh ) q <= d; else begin q[0] <= w; for ( k = 1; k <8; k = k+1 )
q[k] <= q[k – 1]; end
endendmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
If replaced with this code, what is now the shift direction?
...for ( k = 0; k < 7; k = k+1 )
q[k] <= q[k + 1] ;q[7] <= w ;
...
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L4: Verilog Design of Sequential Logic 2012/2013-1
Example 48: 4bit Universal Shift Register
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module univShiftReg (MSBin, LSBin, s1, s0, clock, rst, DataIn, MSBout, LSBout, DataOut)
input MSBin, LSBin, s1, s0 ; input clock, rst ; input [3:0] Datain ;
output MSBout, LSBout ;output [3:0] Dataout ;
reg [3:0] Dataout ;
assign MSBout = DataOut[3] ;assign LSBout = DataOut[0] ;
...
...always @ (negedge clock) begin
if ( rst ) // synchronous resetDataOut <= 0 ;
else case ( {s1, s0} ) 2’b00 : DataOut <= DataOut ; // hold // shift right 2’b01 : DataOut <= { MSBin,DataOut[3:1] } ; // shift left 2’b10 : DataOut <= { DataOut[2:0], LSBin } ;
2’b11 : DataOut <= DataIn ; // parallel loadendcase
end endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Exercise: ⋅ Sketch the iobd of this universal shift register⋅ Obtain its functional block diagram in terms of FFs and the
associated glue logic.
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L4: Verilog Design of Sequential Logic 2012/2013-1
Synchronous Counters
Example 49: A 5bit upcounter with a parallel load
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module upcount5 ( data, Q, clk, rst, ld, inc) ;input [4:0] data ;output [4:0] Q ;input clk, rst ;input ld, inc ;reg [4:0] Q ;
always @ ( posedge rst or posedge clk ) if ( rst ) Q <= 0 ;else if ( ld ) Q <= data ;else if ( inc ) Q <= Q + 1;
endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Exercise: Provide the I/O block diagram, and derive the operations table for this counter.
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L4: Verilog Design of Sequential Logic 2012/2013-1
Example 410:
⋅ Explain the counter.
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module U_D_counter ( data, count, clk, rst, dir ) ;input [7:0] data ;output [7:0] count ;input clk, rst ;input [1:0] dir ;reg [7:0] count ;
always @ ( negedge rst or negedge clk ) if ( rst == 0 ) count <= 8’b00000000 ;
else if (dir == 2’b00 || dir == 2’b11) count <= count ; else if ( dir == 2’b01 ) count <= count + 1;
else if ( dir == 2’b10 ) count <= count 1;endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Simple Sequential Logic
Example 411:
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module PULSER (CLK, PB, PB_Pulse) ;input CLK, PB ;output PB_Pulse ;reg Q1, Q2 ;
always @ (posedge CLK) begin
Q1 <= PB;Q2 <= Q1;
end
assign PB_Pulse = ~ ( ~Q1 | Q2 ) ; endmodule
CLK
PB_Pulse
PBQ2
L4: Verilog Design of Sequential Logic 2012/2013-1
Example 412: Derive the circuit synthesized from this Verilog code fragment.
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module circuit4_12 (S1, CLK, A, B, C, S3, S2, OU) ;input S1, CLK ;input [7:0] A, B, C, S3 ;output [7:0] S2, OU ;reg [7:0] S2, OU ;wire [5:0] TEMP1, TEMP2 ; // internal signals
always @ (posedge CLK)if ( S1 )
if (TEMP1 < 8) S2 <= A + B;else S2 <= C;
always @ (TEMP2 or TEMP1 or S3 or A)if (TEMP2 > TEMP1) OU <= S3 + A;
...endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
It is important that the designer have good knowledge on hardware mapping.
⋅ Depending on the resource constraints, the logic synthesis will generate one or two adders to execute the two addition operations.
⋅ A circuit for comparing a variable and a constant is different from a circuit for comparing two variables.
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L4: Verilog Design of Sequential Logic 2012/2013-1
Finite State Machine (FSM)
⋅ A circuit type with memory.⋅ Usually as datapath controller unit. ⋅ Via algorithmic state machine (ASM) flowchart, an FSM is readily
modelled in HDL. ⋅ We focus only on synthesizable models in this book.
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L4: Verilog Design of Sequential Logic 2012/2013-1
⋅ There are two basic models of FSMs: Moore and Mealy. ⋅ In a Mealy machine, the next state (NS) and the outputs depend on
both the present state (PS) and the inputs. ⋅ The NS of a Moore machine depends on the PS and the inputs, but
the outputs depend on only the PS. ⋅ All FSMs have the general feedback structure.⋅ We will deal only with synchronous FSMs, hence the state
transitions of the machine are synchronized by the active edge of a common clock. In this case, the state register is consisted of edgetriggered flipflops.
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L4: Verilog Design of Sequential Logic 2012/2013-1
Example 413: Verilog Modelling of an FSM (version A coding).
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ZA
A
A
A
S0
S1
S2
S3
1
0
0 1
0 1
0
1
Z
A
CLK
NSLogic
NS
Outputlogic
PS
Y1
Y0
y1
y0Z
Stateregister
L4: Verilog Design of Sequential Logic 2012/2013-1
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module FSM1 ( A, CLK, reset, Z );input A, CLK, reset ;output Z ;reg [1:0] y, Y ;parameter [1:0] S0 = 2’b00, S1 = 2’b01, S2 = 2’b10, S3 = 2’b11;
// NS logic module:always @ (A or y)
case ( y ) S0 : if ( A ) Y = S1; else Y = S0; S1 : if ( A ) Y = S3; else Y = S2; S2 : if ( A ) Y = S3; else Y = S2; S3 : if ( A ) Y = S0; else Y = S3;
endcase// state register module:always @ ( negedge reset or posedge CLK )
if ( !reset ) y <= S0 ;else y <= Y ;
// define the Output Logic: assign Z = ( y == S0 ) | (y == S3) ; endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
Example 414: Verilog Modelling of FSM (version B coding).
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A
A
A
S0
S3
S2
1
0
1
reset
A
S1
Z
Z
0
0
1
0
1
L4: Verilog Design of Sequential Logic 2012/2013-1
module FSM2 ( A, CLK, reset, Z );input A, CLK, reset ;output Z ;reg [1:0] y, Y ;parameter [1:0] S0 = 0, S1 = 1, S2 =2, S3=3;
// define STATE_REG: always @ (negedge reset or negedge CLK)
if ( reset == 0 ) y <= A ;else y <= Y ;
...
...// define NS_OUTPUT and OUTPUT
LOGIC: always @ ( y or A ) begin
case ( y )S0 : if (A ) begin Y = S3 ; Z = 1; end
else begin Y = S0 ; Z = 0; endS1 : if ( A ) begin Y = S0 ; Z = 1; end
else begin Y = S1 ; Z = 0; endS2 : if ( A ) begin Y = S1 ; Z = 0; end
else begin Y = S2 ; Z = 0; endS3 : if ( A ) begin Y = S1 ; Z = 0; end
else begin Y = S2 ; Z = 0; endendcaseend
endmodule
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L4: Verilog Design of Sequential Logic 2012/2013-1
Another version? ⋅ Will this work?
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module FSM2 ( A, CLK, reset, Z );input A, CLK, reset ;output Z ;reg [1:0] y ;parameter [1:0] S0 = 0, S1 = 1, S2 =2, S3=3;// define STATE_REG: always @ (negedge reset or negedge CLK)
beginif ( reset == 0 ) y <= A ;else case ( y )S0 : if (A ) begin y <= S3 ; Z = 1; end
else begin y <= S0 ; Z = 0; endS1 : if ( A ) begin y <= S0 ; Z = 1; end
else begin y <= S1 ; Z = 0; endS2 : if ( A ) begin y <= S1 ; Z = 0; end
else begin y <= S2 ; Z = 0; endS3 : if ( A ) begin y <= S1 ; Z = 0; end else begin y <= S2 ; Z = 0; end
endcase;end;endmodule
L4: Verilog Design of Sequential Logic 2012/2013-1
DIY Problems⋅ P41⋅ P42⋅ P46⋅ P47⋅ P411
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